Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/mn10300/mn10300.md @ 67:f6334be47118
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author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
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date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | 77e2b8dfacca |
children | 04ced10e8804 |
rev | line source |
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0 | 1 ;; GCC machine description for Matsushita MN10300 |
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2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
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3 ;; 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
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4 ;; Free Software Foundation, Inc. |
0 | 5 ;; Contributed by Jeff Law (law@cygnus.com). |
6 | |
7 ;; This file is part of GCC. | |
8 | |
9 ;; GCC is free software; you can redistribute it and/or modify | |
10 ;; it under the terms of the GNU General Public License as published by | |
11 ;; the Free Software Foundation; either version 3, or (at your option) | |
12 ;; any later version. | |
13 | |
14 ;; GCC is distributed in the hope that it will be useful, | |
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 ;; GNU General Public License for more details. | |
18 | |
19 ;; You should have received a copy of the GNU General Public License | |
20 ;; along with GCC; see the file COPYING3. If not see | |
21 ;; <http://www.gnu.org/licenses/>. | |
22 | |
23 ;; The original PO technology requires these to be ordered by speed, | |
24 ;; so that assigner will pick the fastest. | |
25 | |
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
27 | |
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28 (define_constants [ |
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29 (PIC_REG 6) |
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30 (SP_REG 9) |
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31 (MDR_REG 50) |
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32 (CC_REG 51) |
0 | 33 |
34 (UNSPEC_PIC 1) | |
35 (UNSPEC_GOT 2) | |
36 (UNSPEC_GOTOFF 3) | |
37 (UNSPEC_PLT 4) | |
38 (UNSPEC_GOTSYM_OFF 5) | |
67
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39 |
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40 (UNSPEC_EXT 6) |
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41 (UNSPEC_BSCH 7) |
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42 |
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43 ;; This is used to encode LIW patterns. |
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44 (UNSPEC_LIW 8) |
0 | 45 ]) |
46 | |
47 (include "predicates.md") | |
48 (include "constraints.md") | |
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49 |
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50 ;; Processor type. This attribute must exactly match the processor_type |
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51 ;; enumeration in mn10300.h. |
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52 (define_attr "cpu" "mn10300,am33,am33_2,am34" |
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53 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu"))) |
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54 |
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55 ;; Used to control the "enabled" attribute on a per-instruction basis. |
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56 (define_attr "isa" "base,am33,am33_2,am34" |
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57 (const_string "base")) |
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58 |
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59 (define_attr "enabled" "" |
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60 (cond [(eq_attr "isa" "base") |
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61 (const_int 1) |
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62 |
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63 (and (eq_attr "isa" "am33") |
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64 (ne (symbol_ref "TARGET_AM33") (const_int 0))) |
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65 (const_int 1) |
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66 |
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67 (and (eq_attr "isa" "am33_2") |
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68 (ne (symbol_ref "TARGET_AM33_2") (const_int 0))) |
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69 (const_int 1) |
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70 |
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71 (and (eq_attr "isa" "am34") |
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72 (ne (symbol_ref "TARGET_AM34") (const_int 0))) |
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73 (const_int 1) |
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74 ] |
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75 (const_int 0)) |
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76 ) |
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77 |
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78 (define_mode_iterator INT [QI HI SI]) |
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79 |
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80 |
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81 ;; Bundling of smaller insns into a long instruction word (LIW) |
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82 (define_automaton "liw_bundling") |
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83 (automata_option "ndfa") |
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84 |
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85 (define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling") |
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86 |
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87 (define_attr "liw" "op1,op2,both,either" |
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88 (const_string "both")) |
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89 ;; Note: this list must match the one defined for liw_op_names[]. |
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90 (define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max" |
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91 (const_string "none")) |
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92 |
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93 (define_insn_reservation "liw_op1" 1 |
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94 (and (ior (eq_attr "cpu" "am33") |
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95 (eq_attr "cpu" "am33_2") |
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96 (eq_attr "cpu" "am34")) |
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97 (eq_attr "liw" "op1")) |
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98 "liw_op1_u"); |
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99 (define_insn_reservation "liw_op2" 1 |
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100 (and (ior (eq_attr "cpu" "am33") |
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101 (eq_attr "cpu" "am33_2") |
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102 (eq_attr "cpu" "am34")) |
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103 (eq_attr "liw" "op2")) |
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104 "liw_op2_u"); |
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105 (define_insn_reservation "liw_both" 1 |
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106 (and (ior (eq_attr "cpu" "am33") |
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107 (eq_attr "cpu" "am33_2") |
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108 (eq_attr "cpu" "am34")) |
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109 (eq_attr "liw" "both")) |
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110 "liw_op1_u + liw_op2_u"); |
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111 (define_insn_reservation "liw_either" 1 |
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112 (and (ior (eq_attr "cpu" "am33") |
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113 (eq_attr "cpu" "am33_2") |
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114 (eq_attr "cpu" "am34")) |
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115 (eq_attr "liw" "either")) |
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116 "liw_op1_u | liw_op2_u"); |
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117 |
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118 ;; ---------------------------------------------------------------------- |
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119 ;; Pipeline description. |
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120 ;; ---------------------------------------------------------------------- |
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121 |
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122 ;; The AM33 only has a single pipeline. It has five stages (fetch, |
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123 ;; decode, execute, memory access, writeback) each of which normally |
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124 ;; takes a single CPU clock cycle. |
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125 |
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126 ;; The timings attribute consists of two numbers, the first is the |
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127 ;; throughput, which is the number of cycles the instruction takes |
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128 ;; to execute and generate a result. The second is the latency |
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129 ;; which is the effective number of cycles the instruction takes to |
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130 ;; execute if its result is used by the following instruction. The |
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131 ;; latency is always greater than or equal to the throughput. |
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132 ;; These values were taken from the Appendix of the "MN103E Series |
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133 ;; Instruction Manual" and the timings for the AM34. |
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134 |
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135 ;; Note - it would be nice to use strings rather than integers for |
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136 ;; the possible values of this attribute, so that we can have the |
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137 ;; gcc build mechanism check for values that are not supported by |
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138 ;; the reservations below. But this will not work because the code |
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139 ;; in mn10300_adjust_sched_cost() needs integers not strings. |
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140 |
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141 (define_attr "timings" "" (const_int 11)) |
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142 |
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143 (define_automaton "pipelining") |
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144 (define_cpu_unit "throughput" "pipelining") |
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145 |
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146 (define_insn_reservation "throughput__1_latency__1" 1 |
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147 (eq_attr "timings" "11") "throughput") |
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148 (define_insn_reservation "throughput__1_latency__2" 2 |
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149 (eq_attr "timings" "12") "throughput,nothing") |
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150 (define_insn_reservation "throughput__1_latency__3" 3 |
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151 (eq_attr "timings" "13") "throughput,nothing*2") |
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152 (define_insn_reservation "throughput__1_latency__4" 4 |
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153 (eq_attr "timings" "14") "throughput,nothing*3") |
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154 (define_insn_reservation "throughput__2_latency__2" 2 |
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155 (eq_attr "timings" "22") "throughput*2") |
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156 (define_insn_reservation "throughput__2_latency__3" 3 |
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157 (eq_attr "timings" "23") "throughput*2,nothing") |
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158 (define_insn_reservation "throughput__2_latency__4" 4 |
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159 (eq_attr "timings" "24") "throughput*2,nothing*2") |
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160 (define_insn_reservation "throughput__2_latency__5" 5 |
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161 (eq_attr "timings" "25") "throughput*2,nothing*3") |
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162 (define_insn_reservation "throughput__3_latency__3" 3 |
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163 (eq_attr "timings" "33") "throughput*3") |
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164 (define_insn_reservation "throughput__3_latency__7" 7 |
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165 (eq_attr "timings" "37") "throughput*3,nothing*4") |
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166 (define_insn_reservation "throughput__4_latency__4" 4 |
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167 (eq_attr "timings" "44") "throughput*4") |
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168 (define_insn_reservation "throughput__4_latency__7" 7 |
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169 (eq_attr "timings" "47") "throughput*4,nothing*3") |
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170 (define_insn_reservation "throughput__4_latency__8" 8 |
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171 (eq_attr "timings" "48") "throughput*4,nothing*4") |
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172 (define_insn_reservation "throughput__5_latency__5" 5 |
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173 (eq_attr "timings" "55") "throughput*5") |
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174 (define_insn_reservation "throughput__6_latency__6" 6 |
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175 (eq_attr "timings" "66") "throughput*6") |
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176 (define_insn_reservation "throughput__7_latency__7" 7 |
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177 (eq_attr "timings" "77") "throughput*7") |
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178 (define_insn_reservation "throughput__7_latency__8" 8 |
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179 (eq_attr "timings" "78") "throughput*7,nothing") |
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180 (define_insn_reservation "throughput__8_latency__8" 8 |
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181 (eq_attr "timings" "88") "throughput*8") |
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182 (define_insn_reservation "throughput__9_latency__9" 9 |
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183 (eq_attr "timings" "99") "throughput*9") |
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184 (define_insn_reservation "throughput__8_latency_14" 14 |
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185 (eq_attr "timings" "814") "throughput*8,nothing*6") |
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186 (define_insn_reservation "throughput__9_latency_10" 10 |
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187 (eq_attr "timings" "910") "throughput*9,nothing") |
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188 (define_insn_reservation "throughput_10_latency_10" 10 |
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189 (eq_attr "timings" "1010") "throughput*10") |
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190 (define_insn_reservation "throughput_12_latency_16" 16 |
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191 (eq_attr "timings" "1216") "throughput*12,nothing*4") |
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192 (define_insn_reservation "throughput_13_latency_13" 13 |
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193 (eq_attr "timings" "1313") "throughput*13") |
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194 (define_insn_reservation "throughput_14_latency_14" 14 |
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195 (eq_attr "timings" "1414") "throughput*14") |
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196 (define_insn_reservation "throughput_13_latency_17" 17 |
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197 (eq_attr "timings" "1317") "throughput*13,nothing*4") |
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198 (define_insn_reservation "throughput_23_latency_27" 27 |
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199 (eq_attr "timings" "2327") "throughput*23,nothing*4") |
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200 (define_insn_reservation "throughput_25_latency_31" 31 |
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201 (eq_attr "timings" "2531") "throughput*25,nothing*6") |
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202 (define_insn_reservation "throughput_38_latency_39" 39 |
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203 (eq_attr "timings" "3839") "throughput*38,nothing") |
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204 (define_insn_reservation "throughput_39_latency_40" 40 |
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205 (eq_attr "timings" "3940") "throughput*39,nothing") |
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206 (define_insn_reservation "throughput_40_latency_40" 40 |
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207 (eq_attr "timings" "4040") "throughput*40") |
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208 (define_insn_reservation "throughput_41_latency_42" 42 |
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209 (eq_attr "timings" "4142") "throughput*41,nothing") |
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210 (define_insn_reservation "throughput_42_latency_43" 44 |
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211 (eq_attr "timings" "4243") "throughput*42,nothing") |
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212 (define_insn_reservation "throughput_43_latency_44" 44 |
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213 (eq_attr "timings" "4344") "throughput*43,nothing") |
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214 (define_insn_reservation "throughput_45_latency_46" 46 |
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215 (eq_attr "timings" "4546") "throughput*45,nothing") |
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216 (define_insn_reservation "throughput_47_latency_53" 53 |
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217 (eq_attr "timings" "4753") "throughput*47,nothing*6") |
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218 |
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219 ;; Note - the conflict between memory load/store instructions |
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220 ;; and floating point instructions described in section 1-7-4 |
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221 ;; of Chapter 3 of the MN103E Series Instruction Manual is |
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222 ;; handled by the mn10300_adjust_sched_cost function. |
0 | 223 |
224 ;; ---------------------------------------------------------------------- | |
225 ;; MOVE INSTRUCTIONS | |
226 ;; ---------------------------------------------------------------------- | |
227 | |
228 ;; movqi | |
229 | |
230 (define_expand "movqi" | |
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231 [(set (match_operand:QI 0 "nonimmediate_operand") |
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232 (match_operand:QI 1 "general_operand"))] |
0 | 233 "" |
234 { | |
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235 /* One of the ops has to be in a register. */ |
0 | 236 if (!register_operand (operand0, QImode) |
237 && !register_operand (operand1, QImode)) | |
67
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238 operands[1] = force_reg (QImode, operand1); |
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239 }) |
0 | 240 |
67
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241 (define_insn "*movqi_internal" |
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242 [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m") |
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243 (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D"))] |
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244 "(register_operand (operands[0], QImode) |
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245 || register_operand (operands[1], QImode))" |
0 | 246 { |
247 switch (which_alternative) | |
248 { | |
249 case 0: | |
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250 return ""; |
0 | 251 case 1: |
252 case 2: | |
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253 return "mov %1,%0"; |
0 | 254 case 3: |
255 case 4: | |
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256 return "movbu %1,%0"; |
0 | 257 default: |
258 gcc_unreachable (); | |
259 } | |
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260 } |
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261 [(set_attr_alternative "timings" |
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262 [(const_int 11) |
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263 (const_int 11) |
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264 (const_int 11) |
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265 (if_then_else (eq_attr "cpu" "am34") |
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266 (const_int 13) (const_int 24)) |
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267 (if_then_else (eq_attr "cpu" "am34") |
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268 (const_int 11) (const_int 22)) |
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269 ])] |
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270 ) |
0 | 271 |
272 ;; movhi | |
273 | |
274 (define_expand "movhi" | |
67
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275 [(set (match_operand:HI 0 "nonimmediate_operand") |
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276 (match_operand:HI 1 "general_operand"))] |
0 | 277 "" |
278 { | |
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279 /* One of the ops has to be in a register. */ |
0 | 280 if (!register_operand (operand1, HImode) |
281 && !register_operand (operand0, HImode)) | |
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282 operands[1] = force_reg (HImode, operand1); |
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283 }) |
0 | 284 |
67
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285 (define_insn "*movhi_internal" |
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286 [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m") |
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287 (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D"))] |
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288 "(register_operand (operands[0], HImode) |
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289 || register_operand (operands[1], HImode))" |
0 | 290 { |
291 switch (which_alternative) | |
292 { | |
293 case 0: | |
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294 return ""; |
0 | 295 case 1: |
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296 /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes. |
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297 We have "MOV imm16,Dn" at 3 bytes. The only win for the 4 byte |
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298 movu is for an 8-bit unsigned move into Rn. */ |
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299 if (TARGET_AM33 |
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300 && CONST_INT_P (operands[1]) |
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301 && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff) |
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302 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) |
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303 return "movu %1,%0"; |
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304 /* FALLTHRU */ |
0 | 305 case 2: |
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306 return "mov %1,%0"; |
0 | 307 case 3: |
308 case 4: | |
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309 return "movhu %1,%0"; |
0 | 310 default: |
311 gcc_unreachable (); | |
312 } | |
67
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313 } |
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314 [(set_attr_alternative "timings" |
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315 [(const_int 11) |
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316 (const_int 11) |
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317 (if_then_else (eq_attr "cpu" "am34") |
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318 (const_int 11) (const_int 22)) |
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319 (if_then_else (eq_attr "cpu" "am34") |
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320 (const_int 13) (const_int 24)) |
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321 (if_then_else (eq_attr "cpu" "am34") |
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322 (const_int 11) (const_int 22)) |
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323 ])] |
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324 ) |
0 | 325 |
326 ;; movsi and helpers | |
327 | |
328 ;; We use this to handle addition of two values when one operand is the | |
329 ;; stack pointer and the other is a memory reference of some kind. Reload | |
330 ;; does not handle them correctly without this expander. | |
67
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331 (define_expand "reload_plus_sp_const" |
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332 [(set (match_operand:SI 0 "register_operand" "=r") |
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333 (match_operand:SI 1 "impossible_plus_operand" "")) |
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334 (clobber (match_operand:SI 2 "register_operand" "=&A"))] |
0 | 335 "" |
336 { | |
67
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337 rtx dest, scratch, other; |
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338 |
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339 dest = operands[0]; |
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340 scratch = operands[2]; |
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341 |
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342 other = XEXP (operands[1], 1); |
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343 if (other == stack_pointer_rtx) |
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344 other = XEXP (operands[1], 0); |
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345 |
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346 if (true_regnum (other) == true_regnum (dest)) |
0 | 347 { |
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348 gcc_assert (true_regnum (scratch) != true_regnum (dest)); |
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349 emit_move_insn (scratch, stack_pointer_rtx); |
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350 emit_insn (gen_addsi3 (dest, dest, scratch)); |
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351 } |
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352 else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS) |
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353 { |
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354 emit_move_insn (dest, stack_pointer_rtx); |
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355 if (other == stack_pointer_rtx) |
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356 emit_insn (gen_addsi3 (dest, dest, dest)); |
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357 else if (other != const0_rtx) |
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358 emit_insn (gen_addsi3 (dest, dest, other)); |
0 | 359 } |
360 else | |
361 { | |
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362 emit_move_insn (scratch, stack_pointer_rtx); |
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363 if (other == stack_pointer_rtx) |
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364 { |
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365 emit_move_insn (dest, scratch); |
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366 emit_insn (gen_addsi3 (dest, dest, dest)); |
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367 } |
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368 else if (other != const0_rtx) |
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369 { |
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370 emit_move_insn (dest, other); |
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371 emit_insn (gen_addsi3 (dest, dest, scratch)); |
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372 } |
0 | 373 else |
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374 emit_move_insn (dest, scratch); |
0 | 375 } |
376 DONE; | |
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377 }) |
0 | 378 |
379 (define_expand "movsi" | |
67
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380 [(set (match_operand:SI 0 "nonimmediate_operand") |
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381 (match_operand:SI 1 "general_operand"))] |
0 | 382 "" |
383 { | |
67
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384 /* One of the ops has to be in a register. */ |
0 | 385 if (!register_operand (operand1, SImode) |
386 && !register_operand (operand0, SImode)) | |
67
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387 operands[1] = force_reg (SImode, operand1); |
0 | 388 if (flag_pic) |
389 { | |
390 rtx temp; | |
391 if (SYMBOLIC_CONST_P (operands[1])) | |
392 { | |
67
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393 if (MEM_P (operands[0])) |
0 | 394 operands[1] = force_reg (Pmode, operands[1]); |
395 else | |
396 { | |
397 temp = (!can_create_pseudo_p () | |
398 ? operands[0] | |
399 : gen_reg_rtx (Pmode)); | |
67
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400 operands[1] = mn10300_legitimize_pic_address (operands[1], temp); |
0 | 401 } |
402 } | |
403 else if (GET_CODE (operands[1]) == CONST | |
404 && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
405 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) | |
406 { | |
407 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); | |
67
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408 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), |
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409 temp); |
0 | 410 operands[1] = expand_binop (SImode, add_optab, temp, |
411 XEXP (XEXP (operands[1], 0), 1), | |
412 (!can_create_pseudo_p () | |
413 ? temp | |
414 : gen_reg_rtx (Pmode)), | |
415 0, OPTAB_LIB_WIDEN); | |
416 } | |
417 } | |
67
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418 }) |
0 | 419 |
67
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420 (define_insn "*movsi_internal" |
0 | 421 [(set (match_operand:SI 0 "nonimmediate_operand" |
67
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422 "=r,r,r,r,m,r, A,*y,*y,*z,*d") |
0 | 423 (match_operand:SI 1 "general_operand" |
67
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424 " 0,O,i,r,r,m,*y, A, i,*d,*z"))] |
0 | 425 "register_operand (operands[0], SImode) |
426 || register_operand (operands[1], SImode)" | |
427 { | |
428 switch (which_alternative) | |
429 { | |
430 case 0: | |
67
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431 return ""; |
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432 case 1: /* imm-reg. */ |
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433 case 2: |
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434 /* See movhi for a discussion of sizes for 8-bit movu. Note that the |
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435 24-bit movu is 6 bytes, which is the same size as the full 32-bit |
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436 mov form for An and Dn. So again movu is only a win for Rn. */ |
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437 if (TARGET_AM33 |
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438 && CONST_INT_P (operands[1]) |
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439 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) |
0 | 440 { |
441 HOST_WIDE_INT val = INTVAL (operands[1]); | |
67
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442 if (IN_RANGE (val, 0x80, 0xff) |
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443 || IN_RANGE (val, 0x800000, 0xffffff)) |
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444 return "movu %1,%0"; |
0 | 445 } |
67
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446 /* FALLTHRU */ |
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447 case 3: /* reg-reg */ |
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448 case 4: /* reg-mem */ |
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449 case 5: /* mem-reg */ |
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450 case 6: /* sp-reg */ |
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451 case 7: /* reg-sp */ |
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452 case 8: /* imm-sp */ |
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453 case 9: /* reg-mdr */ |
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454 case 10: /* mdr-reg */ |
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455 return "mov %1,%0"; |
0 | 456 default: |
457 gcc_unreachable (); | |
458 } | |
67
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459 } |
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460 [(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*") |
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461 (set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*") |
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462 (set_attr "liw_op" "mov") |
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463 (set_attr_alternative "timings" |
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464 [(const_int 11) |
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465 (const_int 22) |
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466 (const_int 22) |
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467 (const_int 11) |
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468 (if_then_else (eq_attr "cpu" "am34") |
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469 (const_int 11) (const_int 22)) |
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470 (if_then_else (eq_attr "cpu" "am34") |
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471 (const_int 13) (const_int 24)) |
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472 (if_then_else (eq_attr "cpu" "am34") |
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473 (const_int 11) (const_int 22)) |
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474 (if_then_else (eq_attr "cpu" "am34") |
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475 (const_int 13) (const_int 24)) |
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476 (const_int 11) |
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477 (const_int 11) |
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478 (const_int 11) |
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479 ])] |
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480 ) |
0 | 481 |
67
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482 (define_expand "movsf" |
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483 [(set (match_operand:SF 0 "nonimmediate_operand") |
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484 (match_operand:SF 1 "general_operand"))] |
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485 "TARGET_AM33_2" |
0 | 486 { |
67
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487 /* One of the ops has to be in a register. */ |
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488 if (!register_operand (operand1, SFmode) |
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489 && !register_operand (operand0, SFmode)) |
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490 operands[1] = force_reg (SFmode, operand1); |
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491 }) |
0 | 492 |
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493 (define_insn "*movsf_internal" |
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494 [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q") |
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495 (match_operand:SF 1 "general_operand" " 0,F,F,r,f,f,r,m,r,Q,f"))] |
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496 "TARGET_AM33_2 |
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497 && (register_operand (operands[0], SFmode) |
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498 || register_operand (operands[1], SFmode))" |
0 | 499 { |
500 switch (which_alternative) | |
501 { | |
67
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502 case 0: |
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503 return ""; |
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504 case 1: |
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505 case 3: |
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506 case 7: |
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507 case 8: |
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508 return "mov %1,%0"; |
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509 case 2: |
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510 case 4: |
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511 case 5: |
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512 case 6: |
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513 case 9: |
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514 case 10: |
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515 return "fmov %1,%0"; |
0 | 516 default: |
517 gcc_unreachable (); | |
518 } | |
67
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519 } |
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520 [(set_attr_alternative "timings" |
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521 [(const_int 11) |
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522 (const_int 22) |
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523 (if_then_else (eq_attr "cpu" "am34") |
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524 (const_int 47) (const_int 25)) |
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525 (const_int 11) |
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526 (if_then_else (eq_attr "cpu" "am34") |
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527 (const_int 13) (const_int 14)) |
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528 (if_then_else (eq_attr "cpu" "am34") |
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529 (const_int 13) (const_int 12)) |
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530 (if_then_else (eq_attr "cpu" "am34") |
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531 (const_int 13) (const_int 14)) |
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532 (if_then_else (eq_attr "cpu" "am34") |
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533 (const_int 13) (const_int 24)) |
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534 (if_then_else (eq_attr "cpu" "am34") |
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535 (const_int 13) (const_int 24)) |
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536 (if_then_else (eq_attr "cpu" "am34") |
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537 (const_int 13) (const_int 24)) |
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538 (if_then_else (eq_attr "cpu" "am34") |
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539 (const_int 13) (const_int 24)) |
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540 ])] |
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541 ) |
0 | 542 |
67
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543 ;; If the flags register is not live, generate CLR instead of MOV 0. |
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544 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal |
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545 ;; but not a win for ADDRESS_REGS. |
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546 (define_peephole2 |
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547 [(set (match_operand:INT 0 "register_operand" "") (const_int 0))] |
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548 "peep2_regno_dead_p (0, CC_REG) |
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549 && (REGNO_DATA_P (REGNO (operands[0]), 1) |
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550 || REGNO_EXTENDED_P (REGNO (operands[0]), 1))" |
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551 [(parallel [(set (match_dup 0) (const_int 0)) |
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552 (clobber (reg:CC CC_REG))])] |
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553 ) |
0 | 554 |
67
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555 (define_insn "*mov<mode>_clr" |
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556 [(set (match_operand:INT 0 "register_operand" "=D") |
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557 (const_int 0)) |
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558 (clobber (reg:CC CC_REG))] |
0 | 559 "" |
67
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560 "clr %0" |
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561 ) |
0 | 562 |
563 ;; ---------------------------------------------------------------------- | |
564 ;; ADD INSTRUCTIONS | |
565 ;; ---------------------------------------------------------------------- | |
566 | |
67
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567 (define_insn "addsi3" |
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568 [(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r") |
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569 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r") |
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570 (match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r"))) |
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571 (clobber (reg:CC CC_REG))] |
0 | 572 "" |
67
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573 { return mn10300_output_add (operands, false); } |
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574 [(set_attr "timings" "11,11,11,11,22") |
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575 (set_attr "liw" "either,either,*,*,*") |
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576 (set_attr "liw_op" "add")] |
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577 ) |
0 | 578 |
67
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579 ;; Note that ADD IMM,SP does not set the flags, so omit that here. |
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580 (define_insn "*addsi3_flags" |
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581 [(set (match_operand:SI 0 "register_operand" "=r,!r") |
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582 (plus:SI (match_operand:SI 1 "register_operand" "%0, r") |
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583 (match_operand:SI 2 "nonmemory_operand" "ri, r"))) |
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584 (set (reg CC_REG) |
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585 (compare (plus:SI (match_dup 1) (match_dup 2)) |
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586 (const_int 0)))] |
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587 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" |
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588 { return mn10300_output_add (operands, true); } |
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589 [(set_attr "timings" "11,22")] |
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590 ) |
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591 |
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592 ;; A helper to expand the above, with the CC_MODE filled in. |
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593 (define_expand "addsi3_flags" |
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594 [(parallel [(set (match_operand:SI 0 "register_operand") |
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595 (plus:SI (match_operand:SI 1 "register_operand") |
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596 (match_operand:SI 2 "nonmemory_operand"))) |
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597 (set (reg:CCZNC CC_REG) |
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598 (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2)) |
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599 (const_int 0)))])] |
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600 "" |
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601 ) |
0 | 602 |
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603 (define_insn "addc_internal" |
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604 [(set (match_operand:SI 0 "register_operand" "=D,r,r") |
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605 (plus:SI |
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606 (plus:SI |
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607 (ltu:SI (reg:CC CC_REG) (const_int 0)) |
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608 (match_operand:SI 1 "register_operand" "%0,0,r")) |
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609 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))) |
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610 (clobber (reg:CC CC_REG))] |
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611 "reload_completed" |
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612 "@ |
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613 addc %2,%0 |
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614 addc %2,%0 |
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615 addc %2,%1,%0" |
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616 [(set_attr "isa" "*,am33,am33")] |
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617 ) |
0 | 618 |
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619 (define_expand "adddi3" |
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620 [(set (match_operand:DI 0 "register_operand" "") |
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621 (plus:DI (match_operand:DI 1 "register_operand" "") |
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622 (match_operand:DI 2 "nonmemory_operand" "")))] |
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623 "" |
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624 { |
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625 rtx op0l, op0h, op1l, op1h, op2l, op2h; |
0 | 626 |
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627 op0l = gen_lowpart (SImode, operands[0]); |
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628 op1l = gen_lowpart (SImode, operands[1]); |
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629 op2l = gen_lowpart (SImode, operands[2]); |
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630 op0h = gen_highpart (SImode, operands[0]); |
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631 op1h = gen_highpart (SImode, operands[1]); |
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632 op2h = gen_highpart_mode (SImode, DImode, operands[2]); |
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633 |
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634 if (!reg_or_am33_const_operand (op2h, SImode)) |
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635 op2h = force_reg (SImode, op2h); |
0 | 636 |
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637 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); |
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638 DONE; |
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639 }) |
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640 |
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641 ;; Note that reload only supports one commutative operand. Thus we cannot |
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642 ;; auto-swap both the high and low outputs with their matching constraints. |
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643 ;; For MN103, we're strapped for registers but thankfully the alternatives |
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644 ;; are few. For AM33, it becomes much easier to not represent the early |
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645 ;; clobber and 6 permutations of immediate and three-operand adds, but |
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646 ;; instead allocate a scratch register and do the expansion by hand. |
0 | 647 |
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648 (define_insn_and_split "adddi3_internal" |
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649 [(set (match_operand:SI 0 "register_operand" "=r, r, r") |
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650 (plus:SI (match_operand:SI 2 "register_operand" "%0, 0, r") |
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651 (match_operand:SI 3 "nonmemory_operand" "ri,ri,ri"))) |
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652 (set (match_operand:SI 1 "register_operand" "=D, D, r") |
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653 (plus:SI |
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654 (plus:SI |
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655 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2)) |
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656 (match_operand:SI 4 "register_operand" " 1, D, r")) |
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657 (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri"))) |
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658 (clobber (match_scratch:SI 6 "=X, X,&r")) |
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659 (clobber (reg:CC CC_REG))] |
0 | 660 "" |
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661 "#" |
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662 "reload_completed" |
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663 [(const_int 0)] |
0 | 664 { |
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665 rtx op0l = operands[0]; |
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666 rtx op0h = operands[1]; |
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667 rtx op1l = operands[2]; |
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668 rtx op2l = operands[3]; |
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669 rtx op1h = operands[4]; |
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670 rtx op2h = operands[5]; |
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671 rtx scratch = operands[6]; |
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672 rtx x; |
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673 |
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674 if (reg_overlap_mentioned_p (op0l, op1h)) |
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675 { |
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676 emit_move_insn (scratch, op0l); |
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677 op1h = scratch; |
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678 if (reg_overlap_mentioned_p (op0l, op2h)) |
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679 op2h = scratch; |
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680 } |
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681 else if (reg_overlap_mentioned_p (op0l, op2h)) |
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682 { |
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683 emit_move_insn (scratch, op0l); |
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684 op2h = scratch; |
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685 } |
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686 |
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687 if (rtx_equal_p (op0l, op1l)) |
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688 ; |
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689 else if (rtx_equal_p (op0l, op2l)) |
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690 x = op1l, op1l = op2l, op2l = x; |
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691 else |
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692 { |
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693 gcc_assert (TARGET_AM33); |
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694 if (!REG_P (op2l)) |
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695 { |
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696 emit_move_insn (op0l, op2l); |
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697 op2l = op1l; |
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698 op1l = op0l; |
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699 } |
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700 } |
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701 emit_insn (gen_addsi3_flags (op0l, op1l, op2l)); |
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702 |
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703 if (rtx_equal_p (op0h, op1h)) |
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704 ; |
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705 else if (rtx_equal_p (op0h, op2h)) |
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706 x = op1h, op1h = op2h, op2h = x; |
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707 else |
0 | 708 { |
67
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709 gcc_assert (TARGET_AM33); |
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710 if (!REG_P (op2h)) |
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711 { |
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712 emit_move_insn (op0h, op2h); |
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713 op2h = op1h; |
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714 op1h = op0h; |
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715 } |
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716 } |
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717 emit_insn (gen_addc_internal (op0h, op1h, op2h)); |
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718 DONE; |
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719 } |
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720 [(set_attr "isa" "*,*,am33")] |
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721 ) |
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722 |
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723 ;; The following pattern is generated by combine when it proves that one |
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724 ;; of the inputs to the low-part of the double-word add is zero, and thus |
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725 ;; no carry is generated into the high-part. |
0 | 726 |
67
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727 (define_insn_and_split "*adddi3_degenerate" |
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728 [(set (match_operand:SI 0 "register_operand" "=&r,&r") |
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729 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) |
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730 (set (match_operand:SI 1 "register_operand" "=r , r") |
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731 (plus:SI (match_operand:SI 3 "register_operand" "%1 , r") |
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732 (match_operand:SI 4 "nonmemory_operand" "ri, r"))) |
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733 (clobber (reg:CC CC_REG))] |
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734 "" |
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735 "#" |
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736 "" |
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737 [(const_int 0)] |
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|
738 { |
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739 rtx scratch = NULL_RTX; |
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740 if (!rtx_equal_p (operands[0], operands[2])) |
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741 { |
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742 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); |
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743 if (reg_overlap_mentioned_p (operands[0], operands[3]) |
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744 || reg_overlap_mentioned_p (operands[0], operands[4])) |
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745 { |
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746 scratch = gen_reg_rtx (SImode); |
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747 emit_move_insn (scratch, operands[2]); |
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748 } |
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749 else |
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750 emit_move_insn (operands[0], operands[2]); |
0 | 751 } |
67
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752 emit_insn (gen_addsi3 (operands[1], operands[3], operands[4])); |
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753 if (scratch) |
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754 emit_move_insn (operands[0], scratch); |
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755 DONE; |
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756 }) |
0 | 757 |
758 ;; ---------------------------------------------------------------------- | |
759 ;; SUBTRACT INSTRUCTIONS | |
760 ;; ---------------------------------------------------------------------- | |
761 | |
67
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762 (define_insn "subsi3" |
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763 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") |
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764 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r") |
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765 (match_operand:SI 2 "nonmemory_operand" "r,O,i,r"))) |
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766 (clobber (reg:CC CC_REG))] |
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767 "" |
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768 "@ |
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769 sub %2,%0 |
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770 sub %2,%0 |
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771 sub %2,%0 |
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772 sub %2,%1,%0" |
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773 [(set_attr "isa" "*,*,*,am33") |
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774 (set_attr "liw" "either,either,*,*") |
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775 (set_attr "liw_op" "sub") |
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776 (set_attr "timings" "11,11,11,22")] |
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|
777 ) |
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|
778 |
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779 (define_insn "*subsi3_flags" |
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780 [(set (match_operand:SI 0 "register_operand" "=r, r") |
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781 (minus:SI (match_operand:SI 1 "register_operand" "0, r") |
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782 (match_operand:SI 2 "nonmemory_operand" "ri,r"))) |
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783 (set (reg CC_REG) |
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784 (compare (minus:SI (match_dup 1) (match_dup 2)) |
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785 (const_int 0)))] |
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786 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" |
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787 "@ |
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788 sub %2,%0 |
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789 sub %2,%1,%0" |
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790 [(set_attr "isa" "*,am33") |
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791 (set_attr "timings" "11,22")] |
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792 ) |
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793 |
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794 ;; A helper to expand the above, with the CC_MODE filled in. |
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795 (define_expand "subsi3_flags" |
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796 [(parallel [(set (match_operand:SI 0 "register_operand") |
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797 (minus:SI (match_operand:SI 1 "register_operand") |
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798 (match_operand:SI 2 "nonmemory_operand"))) |
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799 (set (reg:CCZNC CC_REG) |
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800 (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2)) |
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801 (const_int 0)))])] |
0 | 802 "" |
67
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803 ) |
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804 |
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805 (define_insn "subc_internal" |
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806 [(set (match_operand:SI 0 "register_operand" "=D,r,r") |
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807 (minus:SI |
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808 (minus:SI (match_operand:SI 1 "register_operand" " 0,0,r") |
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809 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")) |
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810 (geu:SI (reg:CC CC_REG) (const_int 0)))) |
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811 (clobber (reg:CC CC_REG))] |
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812 "reload_completed" |
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813 "@ |
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814 subc %2,%0 |
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815 subc %2,%0 |
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816 subc %2,%1,%0" |
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817 [(set_attr "isa" "*,am33,am33")] |
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818 ) |
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819 |
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820 (define_expand "subdi3" |
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821 [(set (match_operand:DI 0 "register_operand" "") |
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822 (minus:DI (match_operand:DI 1 "register_operand" "") |
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823 (match_operand:DI 2 "nonmemory_operand" "")))] |
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824 "" |
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825 { |
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826 rtx op0l, op0h, op1l, op1h, op2l, op2h; |
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827 |
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828 op0l = gen_lowpart (SImode, operands[0]); |
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829 op1l = gen_lowpart (SImode, operands[1]); |
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830 op2l = gen_lowpart (SImode, operands[2]); |
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831 op0h = gen_highpart (SImode, operands[0]); |
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832 op1h = gen_highpart (SImode, operands[1]); |
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833 op2h = gen_highpart_mode (SImode, DImode, operands[2]); |
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834 |
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835 if (!reg_or_am33_const_operand (op2h, SImode)) |
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836 op2h = force_reg (SImode, op2h); |
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837 |
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838 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h)); |
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839 DONE; |
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840 }) |
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841 |
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842 ;; As with adddi3, the use of the scratch register helps reduce the |
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843 ;; number of permutations for AM33. |
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844 ;; ??? The early clobber on op0 avoids a reload bug wherein both output |
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845 ;; registers are set the same. Consider negate, where both op2 and op3 |
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846 ;; are 0, are csed to the same input register, and reload fails to undo |
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847 ;; the cse when satisfying the matching constraints. |
0 | 848 |
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849 (define_insn_and_split "subdi3_internal" |
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850 [(set (match_operand:SI 0 "register_operand" "=&r, r") |
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851 (minus:SI |
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852 (match_operand:SI 2 "register_operand" " 0, r") |
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853 (match_operand:SI 4 "nonmemory_operand" " ri,ri"))) |
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854 (set (match_operand:SI 1 "register_operand" "=D , r") |
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855 (minus:SI |
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856 (minus:SI |
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857 (match_operand:SI 3 "register_operand" " 1, r") |
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858 (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri")) |
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859 (ltu:SI (match_dup 2) (match_dup 4)))) |
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860 (clobber (match_scratch:SI 6 "=X ,&r")) |
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861 (clobber (reg:CC CC_REG))] |
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862 "" |
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863 "#" |
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864 "reload_completed" |
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865 [(const_int 0)] |
0 | 866 { |
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867 rtx op0l = operands[0]; |
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868 rtx op0h = operands[1]; |
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869 rtx op1l = operands[2]; |
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870 rtx op1h = operands[3]; |
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871 rtx op2l = operands[4]; |
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872 rtx op2h = operands[5]; |
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873 rtx scratch = operands[6]; |
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874 |
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875 if (reg_overlap_mentioned_p (op0l, op1h)) |
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876 { |
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877 emit_move_insn (scratch, op0l); |
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878 op1h = scratch; |
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879 if (reg_overlap_mentioned_p (op0l, op2h)) |
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880 op2h = scratch; |
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881 } |
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882 else if (reg_overlap_mentioned_p (op0l, op2h)) |
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883 { |
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884 emit_move_insn (scratch, op0l); |
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885 op2h = scratch; |
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886 } |
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887 |
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888 if (!rtx_equal_p (op0l, op1l)) |
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889 { |
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890 gcc_assert (TARGET_AM33); |
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891 if (!REG_P (op2l)) |
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892 { |
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893 emit_move_insn (op0l, op1l); |
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894 op1l = op0l; |
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895 } |
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896 } |
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897 emit_insn (gen_subsi3_flags (op0l, op1l, op2l)); |
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898 |
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899 if (!rtx_equal_p (op0h, op1h)) |
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900 { |
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901 gcc_assert (TARGET_AM33); |
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902 if (!REG_P (op2h)) |
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903 { |
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904 emit_move_insn (op0h, op1h); |
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905 op1h = op0h; |
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906 } |
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907 } |
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908 emit_insn (gen_subc_internal (op0h, op1h, op2h)); |
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909 DONE; |
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910 } |
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911 [(set_attr "isa" "*,am33")] |
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912 ) |
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913 |
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914 ;; The following pattern is generated by combine when it proves that one |
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915 ;; of the inputs to the low-part of the double-word sub is zero, and thus |
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916 ;; no carry is generated into the high-part. |
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917 |
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918 (define_insn_and_split "*subdi3_degenerate" |
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919 [(set (match_operand:SI 0 "register_operand" "=&r,&r") |
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920 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) |
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921 (set (match_operand:SI 1 "register_operand" "=r , r") |
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922 (minus:SI (match_operand:SI 3 "register_operand" " 1, r") |
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923 (match_operand:SI 4 "nonmemory_operand" " ri, r"))) |
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924 (clobber (reg:CC CC_REG))] |
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925 "" |
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926 "#" |
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927 "" |
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928 [(const_int 0)] |
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929 { |
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930 rtx scratch = NULL_RTX; |
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931 if (!rtx_equal_p (operands[0], operands[2])) |
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932 { |
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933 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); |
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934 if (reg_overlap_mentioned_p (operands[0], operands[3]) |
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935 || reg_overlap_mentioned_p (operands[0], operands[4])) |
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936 { |
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937 scratch = gen_reg_rtx (SImode); |
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938 emit_move_insn (scratch, operands[2]); |
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939 } |
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940 else |
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941 emit_move_insn (operands[0], operands[2]); |
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942 } |
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943 emit_insn (gen_subsi3 (operands[1], operands[3], operands[4])); |
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944 if (scratch) |
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945 emit_move_insn (operands[0], scratch); |
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946 DONE; |
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947 }) |
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948 |
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949 (define_insn_and_split "negsi2" |
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950 [(set (match_operand:SI 0 "register_operand" "=D,&r") |
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951 (neg:SI (match_operand:SI 1 "register_operand" " 0, r"))) |
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952 (clobber (reg:CC CC_REG))] |
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953 "" |
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954 "#" |
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955 "&& reload_completed" |
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956 [(const_int 0)] |
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957 { |
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958 /* Recall that twos-compliment is ones-compliment plus one. When |
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959 allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33) |
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960 this is 3+3 bytes. |
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961 |
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962 For AM33, it would have been possible to load zero and use the |
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963 three-address subtract to have a total size of 3+4*N bytes for |
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964 multiple negations, plus increased throughput. Not attempted here. */ |
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965 |
0 | 966 if (true_regnum (operands[0]) == true_regnum (operands[1])) |
67
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967 { |
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968 emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); |
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969 emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx)); |
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970 } |
0 | 971 else |
972 { | |
67
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973 emit_move_insn (operands[0], const0_rtx); |
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974 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1])); |
0 | 975 } |
976 DONE; | |
67
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977 }) |
0 | 978 |
979 ;; ---------------------------------------------------------------------- | |
980 ;; MULTIPLY INSTRUCTIONS | |
981 ;; ---------------------------------------------------------------------- | |
982 | |
67
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983 ;; ??? Note that AM33 has a third multiply variant that puts the high part |
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984 ;; into the MDRQ register, however this variant also constrains the inputs |
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985 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering |
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986 ;; the existance of the 4-operand multiply. Nor is there a set of divide |
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987 ;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would |
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988 ;; have been very handy for starting udivmodsi4... |
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989 |
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990 (define_expand "mulsidi3" |
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991 [(set (match_operand:DI 0 "register_operand" "") |
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992 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) |
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993 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))] |
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994 "" |
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995 { |
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996 emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]), |
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997 gen_highpart (SImode, operands[0]), |
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998 operands[1], operands[2])); |
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999 DONE; |
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1000 }) |
0 | 1001 |
67
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1002 (define_insn "mulsidi3_internal" |
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1003 [(set (match_operand:SI 0 "register_operand" "=D,r") |
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1004 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") |
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1005 (match_operand:SI 3 "register_operand" " D,r"))) |
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1006 (set (match_operand:SI 1 "register_operand" "=z,r") |
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1007 (truncate:SI |
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1008 (ashiftrt:DI |
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1009 (mult:DI (sign_extend:DI (match_dup 2)) |
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1010 (sign_extend:DI (match_dup 3))) |
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1011 (const_int 32)))) |
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1012 (clobber (reg:CC CC_REG))] |
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1013 "" |
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1014 { |
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1015 if (which_alternative == 1) |
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1016 return "mul %2,%3,%1,%0"; |
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1017 else if (TARGET_MULT_BUG) |
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1018 return "nop\;nop\;mul %3,%0"; |
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1019 else |
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1020 return "mul %3,%0"; |
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1021 } |
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1022 [(set_attr "isa" "*,am33") |
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|
1023 (set (attr "timings") |
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1024 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
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1025 ) |
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|
1026 |
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|
1027 (define_expand "umulsidi3" |
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|
1028 [(set (match_operand:DI 0 "register_operand" "") |
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|
1029 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) |
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|
1030 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) |
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|
1031 (clobber (reg:CC CC_REG))] |
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|
1032 "" |
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|
1033 { |
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|
1034 emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]), |
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|
1035 gen_highpart (SImode, operands[0]), |
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|
1036 operands[1], operands[2])); |
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|
1037 DONE; |
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|
1038 }) |
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|
1039 |
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|
1040 (define_insn "umulsidi3_internal" |
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|
1041 [(set (match_operand:SI 0 "register_operand" "=D,r") |
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|
1042 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") |
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|
1043 (match_operand:SI 3 "register_operand" " D,r"))) |
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|
1044 (set (match_operand:SI 1 "register_operand" "=z,r") |
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|
1045 (truncate:SI |
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|
1046 (lshiftrt:DI |
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|
1047 (mult:DI (zero_extend:DI (match_dup 2)) |
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|
1048 (zero_extend:DI (match_dup 3))) |
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|
1049 (const_int 32)))) |
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|
1050 (clobber (reg:CC CC_REG))] |
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|
1051 "" |
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|
1052 { |
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|
1053 if (which_alternative == 1) |
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|
1054 return "mulu %2,%3,%1,%0"; |
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|
1055 else if (TARGET_MULT_BUG) |
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|
1056 return "nop\;nop\;mulu %3,%0"; |
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changeset
|
1057 else |
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|
1058 return "mulu %3,%0"; |
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|
1059 } |
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|
1060 [(set_attr "isa" "*,am33") |
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|
1061 (set (attr "timings") |
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|
1062 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
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|
1063 ) |
0 | 1064 |
1065 (define_expand "mulsi3" | |
67
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|
1066 [(parallel [(set (match_operand:SI 0 "register_operand") |
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changeset
|
1067 (mult:SI (match_operand:SI 1 "register_operand") |
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changeset
|
1068 (match_operand:SI 2 "reg_or_am33_const_operand"))) |
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|
1069 (clobber (match_scratch:SI 3)) |
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|
1070 (clobber (reg:CC CC_REG))])] |
0 | 1071 "" |
67
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|
1072 ) |
0 | 1073 |
67
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|
1074 (define_insn "*mulsi3" |
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|
1075 [(set (match_operand:SI 0 "register_operand" "=D, r,r") |
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|
1076 (mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r") |
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|
1077 (match_operand:SI 3 "reg_or_am33_const_operand" " D,ri,r"))) |
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|
1078 (clobber (match_scratch:SI 1 "=z, z,r")) |
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55
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|
1079 (clobber (reg:CC CC_REG))] |
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|
1080 "" |
0 | 1081 { |
67
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|
1082 if (which_alternative == 2) |
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|
1083 return "mul %2,%3,%1,%0"; |
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|
1084 else if (TARGET_MULT_BUG) |
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|
1085 return "nop\;nop\;mul %3,%0"; |
0 | 1086 else |
67
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|
1087 return "mul %3,%0"; |
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|
1088 } |
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|
1089 [(set_attr "isa" "*,am33,am33") |
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|
1090 (set (attr "timings") |
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|
1091 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
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|
1092 ) |
0 | 1093 |
67
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|
1094 (define_expand "udivmodsi4" |
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|
1095 [(parallel [(set (match_operand:SI 0 "register_operand") |
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|
1096 (udiv:SI (match_operand:SI 1 "register_operand") |
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|
1097 (match_operand:SI 2 "register_operand"))) |
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|
1098 (set (match_operand:SI 3 "register_operand") |
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|
1099 (umod:SI (match_dup 1) (match_dup 2))) |
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|
1100 (use (const_int 0)) |
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|
1101 (clobber (reg:CC CC_REG))])] |
0 | 1102 "" |
67
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|
1103 ) |
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|
1104 |
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|
1105 ;; Note the trick to get reload to put the zero into the MDR register, |
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|
1106 ;; rather than exposing the load early and letting CSE or someone try |
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|
1107 ;; to share the zeros between division insns. Which tends to result |
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|
1108 ;; in sequences like 0->r0->d0->mdr. |
0 | 1109 |
67
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|
1110 (define_insn "*udivmodsi4" |
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|
1111 [(set (match_operand:SI 0 "register_operand" "=D") |
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|
1112 (udiv:SI (match_operand:SI 2 "register_operand" " 0") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1113 (match_operand:SI 3 "register_operand" " D"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1114 (set (match_operand:SI 1 "register_operand" "=z") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1115 (umod:SI (match_dup 2) (match_dup 3))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1116 (use (match_operand:SI 4 "nonmemory_operand" " 1")) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1117 (clobber (reg:CC CC_REG))] |
0 | 1118 "" |
67
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|
1119 "divu %3,%0" |
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|
1120 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1121 (const_int 3839) (const_int 4243)))] |
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|
1122 ) |
0 | 1123 |
67
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|
1124 (define_expand "divmodsi4" |
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|
1125 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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|
1126 (div:SI (match_operand:SI 1 "register_operand" "") |
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|
1127 (match_operand:SI 2 "register_operand" ""))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1128 (set (match_operand:SI 3 "register_operand" "") |
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|
1129 (mod:SI (match_dup 1) (match_dup 2))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1130 (use (match_dup 4)) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
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|
1131 (clobber (reg:CC CC_REG))])] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1132 "" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
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|
1133 { |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
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|
1134 operands[4] = gen_reg_rtx (SImode); |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1135 emit_insn (gen_ext_internal (operands[4], operands[1])); |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1136 }) |
0 | 1137 |
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1138 ;; ??? Ideally we'd represent this via shift, but it seems like adding a |
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diff
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|
1139 ;; special-case pattern for (ashiftrt x 31) is just as likely to result |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1140 ;; in poor register allocation choices. |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1141 (define_insn "ext_internal" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
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|
1142 [(set (match_operand:SI 0 "register_operand" "=z") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1143 (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))] |
0 | 1144 "" |
67
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diff
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|
1145 "ext %1" |
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|
1146 ) |
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|
1147 |
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55
diff
changeset
|
1148 (define_insn "*divmodsi4" |
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55
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changeset
|
1149 [(set (match_operand:SI 0 "register_operand" "=D") |
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55
diff
changeset
|
1150 (div:SI (match_operand:SI 2 "register_operand" " 0") |
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|
1151 (match_operand:SI 3 "register_operand" " D"))) |
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55
diff
changeset
|
1152 (set (match_operand:SI 1 "register_operand" "=z") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1153 (mod:SI (match_dup 2) (match_dup 3))) |
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55
diff
changeset
|
1154 (use (match_operand:SI 4 "register_operand" " 1")) |
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55
diff
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|
1155 (clobber (reg:CC CC_REG))] |
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|
1156 "" |
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changeset
|
1157 "div %3,%0"; |
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|
1158 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1159 (const_int 3839) (const_int 4243)))] |
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|
1160 ) |
0 | 1161 |
1162 | |
1163 ;; ---------------------------------------------------------------------- | |
1164 ;; AND INSTRUCTIONS | |
1165 ;; ---------------------------------------------------------------------- | |
1166 | |
67
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diff
changeset
|
1167 (define_insn "andsi3" |
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changeset
|
1168 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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changeset
|
1169 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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55
diff
changeset
|
1170 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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changeset
|
1171 (clobber (reg:CC CC_REG))] |
0 | 1172 "" |
67
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|
1173 "@ |
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changeset
|
1174 and %2,%0 |
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1175 and %2,%0 |
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1176 and %2,%1,%0" |
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1177 [(set_attr "isa" "*,*,am33") |
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1178 (set_attr "liw" "*,op1,*") |
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1179 (set_attr "liw_op" "and") |
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1180 (set_attr "timings" "22,11,11")] |
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1181 ) |
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1182 |
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1183 (define_insn "*andsi3_flags" |
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1184 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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1185 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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1186 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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1187 (set (reg CC_REG) |
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1188 (compare (and:SI (match_dup 1) (match_dup 2)) |
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1189 (const_int 0)))] |
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1190 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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1191 "@ |
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1192 and %2,%0 |
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1193 and %2,%0 |
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1194 and %2,%1,%0" |
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1195 [(set_attr "isa" "*,*,am33") |
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1196 (set_attr "timings" "22,11,11")] |
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1197 ) |
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1198 |
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1199 ;; Make sure we generate extensions instead of ANDs. |
0 | 1200 |
67
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1201 (define_split |
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1202 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1203 (and:SI (match_operand:SI 1 "register_operand" "") |
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1204 (const_int 255))) |
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1205 (clobber (reg:CC CC_REG))])] |
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1206 "" |
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1207 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] |
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1208 { operands[1] = gen_lowpart (QImode, operands[1]); } |
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1209 ) |
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1210 |
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1211 (define_split |
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1212 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1213 (and:SI (match_operand:SI 1 "register_operand" "") |
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1214 (const_int 65535))) |
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1215 (clobber (reg:CC CC_REG))])] |
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1216 "" |
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1217 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] |
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1218 { operands[1] = gen_lowpart (HImode, operands[1]); } |
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1219 ) |
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1220 |
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1221 ;; Split AND by an appropriate constant into two shifts. Recall that |
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1222 ;; operations with a full 32-bit immediate require an extra cycle, so |
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1223 ;; this is a size optimization with no speed penalty. This only applies |
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1224 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win. |
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1225 |
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1226 (define_split |
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1227 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1228 (and:SI (match_dup 0) |
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1229 (match_operand:SI 1 "const_int_operand" ""))) |
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1230 (clobber (reg:CC CC_REG))])] |
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1231 "reload_completed |
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1232 && REGNO_DATA_P (true_regnum (operands[0]), 1) |
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1233 && mn10300_split_and_operand_count (operands[1]) != 0" |
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1234 [(const_int 0)] |
0 | 1235 { |
67
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1236 int count = mn10300_split_and_operand_count (operands[1]); |
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1237 if (count > 0) |
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1238 { |
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1239 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count))); |
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1240 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count))); |
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1241 } |
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1242 else |
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1243 { |
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1244 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count))); |
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1245 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count))); |
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1246 } |
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|
1247 DONE; |
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1248 }) |
0 | 1249 |
1250 ;; ---------------------------------------------------------------------- | |
1251 ;; OR INSTRUCTIONS | |
1252 ;; ---------------------------------------------------------------------- | |
1253 | |
67
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1254 (define_insn "iorsi3" |
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1255 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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1256 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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1257 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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1258 (clobber (reg:CC CC_REG))] |
0 | 1259 "" |
67
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1260 "@ |
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1261 or %2,%0 |
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|
1262 or %2,%0 |
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|
1263 or %2,%1,%0" |
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1264 [(set_attr "isa" "*,*,am33") |
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1265 (set_attr "liw" "*,op1,*") |
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1266 (set_attr "liw_op" "or") |
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1267 (set_attr "timings" "22,11,11")] |
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1268 ) |
0 | 1269 |
67
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|
1270 (define_insn "*iorsi3_flags" |
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1271 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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1272 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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|
1273 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1274 (set (reg CC_REG) |
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diff
changeset
|
1275 (compare (ior:SI (match_dup 1) (match_dup 2)) |
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diff
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|
1276 (const_int 0)))] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1277 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1278 "@ |
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55
diff
changeset
|
1279 or %2,%0 |
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changeset
|
1280 or %2,%0 |
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|
1281 or %2,%1,%0" |
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
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|
1282 [(set_attr "isa" "*,*,am33") |
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|
1283 (set_attr "timings" "22,11,11")] |
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1284 ) |
0 | 1285 |
1286 ;; ---------------------------------------------------------------------- | |
1287 ;; XOR INSTRUCTIONS | |
1288 ;; ---------------------------------------------------------------------- | |
1289 | |
67
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|
1290 (define_insn "xorsi3" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1291 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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|
1292 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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|
1293 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1294 (clobber (reg:CC CC_REG))] |
0 | 1295 "" |
67
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|
1296 "@ |
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|
1297 xor %2,%0 |
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|
1298 xor %2,%0 |
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|
1299 xor %2,%1,%0" |
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|
1300 [(set_attr "isa" "*,*,am33") |
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1301 (set_attr "liw" "*,op1,*") |
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|
1302 (set_attr "liw_op" "xor") |
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|
1303 (set_attr "timings" "22,11,11")] |
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1304 ) |
0 | 1305 |
67
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|
1306 (define_insn "*xorsi3_flags" |
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|
1307 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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|
1308 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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|
1309 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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|
1310 (set (reg CC_REG) |
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|
1311 (compare (xor:SI (match_dup 1) (match_dup 2)) |
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|
1312 (const_int 0)))] |
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|
1313 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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|
1314 "@ |
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|
1315 xor %2,%0 |
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|
1316 xor %2,%0 |
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|
1317 xor %2,%1,%0" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1318 [(set_attr "isa" "*,*,am33") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1319 (set_attr "timings" "22,11,11")] |
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|
1320 ) |
0 | 1321 |
1322 ;; ---------------------------------------------------------------------- | |
1323 ;; NOT INSTRUCTIONS | |
1324 ;; ---------------------------------------------------------------------- | |
1325 | |
67
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|
1326 (define_insn "one_cmplsi2" |
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1327 [(set (match_operand:SI 0 "register_operand" "=D") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1328 (not:SI (match_operand:SI 1 "register_operand" " 0"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1329 (clobber (reg:CC CC_REG))] |
0 | 1330 "" |
1331 "not %0" | |
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1332 ) |
0 | 1333 |
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1334 (define_insn "*one_cmplsi2_flags" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1335 [(set (match_operand:SI 0 "register_operand" "=D") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1336 (not:SI (match_operand:SI 1 "register_operand" " 0"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1337 (set (reg CC_REG) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1338 (compare (not:SI (match_dup 1)) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1339 (const_int 0)))] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1340 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1341 "not %0" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1342 ) |
0 | 1343 |
1344 ;; ---------------------------------------------------------------------- | |
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1345 ;; COMPARE AND BRANCH INSTRUCTIONS |
0 | 1346 ;; ---------------------------------------------------------------------- |
1347 | |
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1348 ;; We expand the comparison into a single insn so that it will not be split |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1349 ;; up by reload. |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1350 (define_expand "cbranchsi4" |
67
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55
diff
changeset
|
1351 [(set (pc) |
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diff
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|
1352 (if_then_else |
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diff
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|
1353 (match_operator 0 "ordered_comparison_operator" |
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55
diff
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|
1354 [(match_operand:SI 1 "register_operand") |
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
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|
1355 (match_operand:SI 2 "nonmemory_operand")]) |
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55
diff
changeset
|
1356 (label_ref (match_operand 3 "")) |
55
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1357 (pc)))] |
0 | 1358 "" |
67
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diff
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|
1359 "" |
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|
1360 ) |
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diff
changeset
|
1361 |
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diff
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|
1362 (define_insn_and_split "*cbranchsi4_cmp" |
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diff
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|
1363 [(set (pc) |
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diff
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|
1364 (if_then_else (match_operator 3 "ordered_comparison_operator" |
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|
1365 [(match_operand:SI 0 "register_operand" "r") |
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diff
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|
1366 (match_operand:SI 1 "nonmemory_operand" "ri")]) |
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|
1367 (match_operand 2 "label_ref_operand" "") |
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diff
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|
1368 (pc)))] |
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diff
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|
1369 "" |
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|
1370 "#" |
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|
1371 "reload_completed" |
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|
1372 [(const_int 0)] |
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diff
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|
1373 { |
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55
diff
changeset
|
1374 mn10300_split_cbranch (CCmode, operands[3], operands[2]); |
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diff
changeset
|
1375 DONE; |
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|
1376 }) |
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|
1377 |
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diff
changeset
|
1378 (define_insn "*cmpsi" |
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diff
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|
1379 [(set (reg CC_REG) |
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diff
changeset
|
1380 (compare (match_operand:SI 0 "register_operand" "r,r,r") |
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1381 (match_operand:SI 1 "nonmemory_operand" "r,O,i")))] |
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1382 "reload_completed" |
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1383 { |
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1384 /* The operands of CMP must be distinct registers. In the case where |
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|
1385 we've failed to optimize the comparison of a register to itself, we |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1386 must use another method to set the Z flag. We can achieve this |
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1387 effect with a BTST 0,D0. This will not alter the contents of D0; |
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|
1388 the use of d0 is arbitrary; any data register would work. */ |
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1389 if (rtx_equal_p (operands[0], operands[1])) |
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|
1390 return "btst 0,d0"; |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1391 else |
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|
1392 return "cmp %1,%0"; |
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|
1393 } |
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1394 [(set_attr_alternative "timings" |
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1395 [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) |
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|
1396 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) |
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1397 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))]) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1398 (set_attr "liw" "either,either,*") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1399 (set_attr "liw_op" "cmp")] |
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|
1400 ) |
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|
1401 |
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|
1402 (define_insn "*integer_conditional_branch" |
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|
1403 [(set (pc) |
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|
1404 (if_then_else (match_operator 0 "comparison_operator" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1405 [(match_operand 2 "int_mode_flags" "") |
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|
1406 (const_int 0)]) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1407 (label_ref (match_operand 1 "" "")) |
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|
1408 (pc)))] |
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|
1409 "reload_completed" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1410 "b%b0 %1" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1411 ) |
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|
1412 |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1413 (define_insn_and_split "*cbranchsi4_btst" |
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parents:
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|
1414 [(set (pc) |
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|
1415 (if_then_else |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1416 (match_operator 3 "CCZN_comparison_operator" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1417 [(and:SI (match_operand:SI 0 "register_operand" "D") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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|
1418 (match_operand:SI 1 "immediate_operand" "i")) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
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|
1419 (const_int 0)]) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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|
1420 (match_operand 2 "label_ref_operand" "") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1421 (pc)))] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1422 "" |
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|
1423 "#" |
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|
1424 "reload_completed" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1425 [(const_int 0)] |
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parents:
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|
1426 { |
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1427 mn10300_split_cbranch (CCZNmode, operands[3], operands[2]); |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1428 DONE; |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1429 }) |
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parents:
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|
1430 |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1431 (define_insn "*btstsi" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1432 [(set (reg:CCZN CC_REG) |
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|
1433 (compare:CCZN |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1434 (and:SI (match_operand:SI 0 "register_operand" "D") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1435 (match_operand:SI 1 "immediate_operand" "i")) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
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|
1436 (const_int 0)))] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1437 "reload_completed" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1438 "btst %1,%0" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1439 ) |
0 | 1440 |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1441 (define_expand "cbranchsf4" |
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1442 [(set (pc) |
55
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1443 (if_then_else |
67
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diff
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|
1444 (match_operator 0 "ordered_comparison_operator" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1445 [(match_operand:SF 1 "register_operand") |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1446 (match_operand:SF 2 "nonmemory_operand")]) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1447 (label_ref (match_operand 3 "")) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1448 (pc)))] |
55
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1449 "TARGET_AM33_2" |
67
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diff
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|
1450 "" |
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55
diff
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|
1451 ) |
0 | 1452 |
67
f6334be47118
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55
diff
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|
1453 (define_insn_and_split "*cbranchsf4_cmp" |
0 | 1454 [(set (pc) |
67
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diff
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|
1455 (if_then_else (match_operator 3 "ordered_comparison_operator" |
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diff
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|
1456 [(match_operand:SF 0 "register_operand" "f") |
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diff
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|
1457 (match_operand:SF 1 "nonmemory_operand" "fF")]) |
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55
diff
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|
1458 (match_operand 2 "label_ref_operand" "") |
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55
diff
changeset
|
1459 (pc))) |
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diff
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|
1460 ] |
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diff
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|
1461 "TARGET_AM33_2" |
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diff
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|
1462 "#" |
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|
1463 "&& reload_completed" |
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55
diff
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|
1464 [(const_int 0)] |
0 | 1465 { |
67
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diff
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|
1466 mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]); |
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|
1467 DONE; |
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diff
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|
1468 }) |
0 | 1469 |
67
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55
diff
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|
1470 (define_insn "*am33_cmpsf" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
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|
1471 [(set (reg:CC_FLOAT CC_REG) |
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diff
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|
1472 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f") |
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|
1473 (match_operand:SF 1 "nonmemory_operand" "fF")))] |
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diff
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|
1474 "TARGET_AM33_2 && reload_completed" |
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diff
changeset
|
1475 "fcmp %1, %0" |
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55
diff
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|
1476 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1477 (const_int 17) (const_int 25)))] |
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1478 ) |
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1479 |
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1480 (define_insn "*float_conditional_branch" |
0 | 1481 [(set (pc) |
67
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1482 (if_then_else (match_operator 0 "comparison_operator" |
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1483 [(reg:CC_FLOAT CC_REG) (const_int 0)]) |
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1484 (label_ref (match_operand 1 "" "")) |
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1485 (pc)))] |
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1486 "TARGET_AM33_2 && reload_completed" |
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1487 "fb%b0 %1" |
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1488 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1489 (const_int 44) (const_int 33)))] |
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1490 ) |
0 | 1491 |
1492 ;; Unconditional and other jump instructions. | |
1493 | |
1494 (define_insn "jump" | |
1495 [(set (pc) | |
1496 (label_ref (match_operand 0 "" "")))] | |
1497 "" | |
1498 "jmp %l0" | |
67
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1499 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1500 (const_int 11) (const_int 44)))] |
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1501 ) |
0 | 1502 |
1503 (define_insn "indirect_jump" | |
1504 [(set (pc) (match_operand:SI 0 "register_operand" "a"))] | |
1505 "" | |
1506 "jmp (%0)" | |
67
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1507 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1508 (const_int 11) (const_int 33)))] |
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1509 ) |
0 | 1510 |
1511 (define_expand "builtin_setjmp_receiver" | |
1512 [(match_operand 0 "" "")] | |
1513 "flag_pic" | |
1514 { | |
67
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1515 emit_insn (gen_load_pic ()); |
0 | 1516 DONE; |
67
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1517 }) |
0 | 1518 |
1519 (define_expand "casesi" | |
67
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1520 [(match_operand:SI 0 "register_operand") |
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1521 (match_operand:SI 1 "immediate_operand") |
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1522 (match_operand:SI 2 "immediate_operand") |
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1523 (match_operand 3 "" "") (match_operand 4 "")] |
0 | 1524 "" |
1525 { | |
1526 rtx table = gen_reg_rtx (SImode); | |
1527 rtx index = gen_reg_rtx (SImode); | |
1528 rtx addr = gen_reg_rtx (Pmode); | |
55
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1529 rtx test; |
0 | 1530 |
1531 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3])); | |
67
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1532 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1])))); |
55
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1533 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]); |
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1534 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4])); |
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1535 |
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1536 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
0 | 1537 emit_move_insn (addr, gen_rtx_MEM (SImode, |
1538 gen_rtx_PLUS (SImode, table, index))); | |
1539 if (flag_pic) | |
67
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1540 emit_insn (gen_addsi3 (addr, addr, table)); |
0 | 1541 |
1542 emit_jump_insn (gen_tablejump (addr, operands[3])); | |
1543 DONE; | |
67
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1544 }) |
0 | 1545 |
1546 (define_insn "tablejump" | |
1547 [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1548 (use (label_ref (match_operand 1 "" "")))] | |
1549 "" | |
1550 "jmp (%0)" | |
67
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1551 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1552 (const_int 11) (const_int 33)))] |
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1553 ) |
0 | 1554 |
1555 ;; Call subroutine with no return value. | |
1556 | |
1557 (define_expand "call" | |
67
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1558 [(call (match_operand:QI 0 "general_operand") |
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1559 (match_operand:SI 1 "general_operand"))] |
0 | 1560 "" |
1561 { | |
67
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1562 rtx fn = XEXP (operands[0], 0); |
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1563 |
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1564 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) |
0 | 1565 { |
67
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1566 if (MN10300_GLOBAL_P (fn)) |
0 | 1567 { |
1568 /* The PLT code won't run on AM30, but then, there's no | |
1569 shared library support for AM30 either, so we just assume | |
1570 the linker is going to adjust all @PLT relocs to the | |
1571 actual symbols. */ | |
1572 emit_use (pic_offset_table_rtx); | |
67
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1573 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); |
0 | 1574 } |
1575 else | |
67
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1576 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); |
0 | 1577 } |
67
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1578 if (! call_address_operand (fn, VOIDmode)) |
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1579 fn = force_reg (SImode, fn); |
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1580 |
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1581 XEXP (operands[0], 0) = fn; |
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1582 }) |
0 | 1583 |
67
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1584 (define_insn "*call_internal" |
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1585 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S")) |
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1586 (match_operand:SI 1 "" ""))] |
0 | 1587 "" |
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1588 "@ |
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1589 calls %C0 |
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1590 call %C0,[],0" |
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1591 [(set_attr_alternative "timings" |
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1592 [(if_then_else (eq_attr "cpu" "am34") |
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1593 (const_int 33) (const_int 44)) |
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1594 (if_then_else (eq_attr "cpu" "am34") |
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1595 (const_int 55) (const_int 33)) |
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1596 ]) |
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1597 ] |
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1598 ) |
0 | 1599 |
1600 ;; Call subroutine, returning value in operand 0 | |
1601 ;; (which must be a hard register). | |
1602 | |
1603 (define_expand "call_value" | |
67
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1604 [(set (match_operand 0 "") |
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1605 (call (match_operand:QI 1 "general_operand") |
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1606 (match_operand:SI 2 "general_operand")))] |
0 | 1607 "" |
1608 { | |
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1609 rtx fn = XEXP (operands[1], 0); |
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1610 |
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1611 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) |
0 | 1612 { |
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1613 if (MN10300_GLOBAL_P (fn)) |
0 | 1614 { |
1615 /* The PLT code won't run on AM30, but then, there's no | |
1616 shared library support for AM30 either, so we just assume | |
1617 the linker is going to adjust all @PLT relocs to the | |
1618 actual symbols. */ | |
1619 emit_use (pic_offset_table_rtx); | |
67
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1620 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); |
0 | 1621 } |
1622 else | |
67
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1623 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); |
0 | 1624 } |
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1625 if (! call_address_operand (fn, VOIDmode)) |
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1626 fn = force_reg (SImode, fn); |
0 | 1627 |
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|
1628 XEXP (operands[1], 0) = fn; |
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1629 }) |
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1630 |
0 | 1631 (define_insn "call_value_internal" |
67
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|
1632 [(set (match_operand 0 "" "") |
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1633 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S")) |
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1634 (match_operand:SI 2 "" "")))] |
0 | 1635 "" |
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1636 "@ |
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|
1637 calls %C1 |
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|
1638 call %C1,[],0" |
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1639 [(set_attr_alternative "timings" |
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1640 [(if_then_else (eq_attr "cpu" "am34") |
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1641 (const_int 33) (const_int 44)) |
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1642 (if_then_else (eq_attr "cpu" "am34") |
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1643 (const_int 55) (const_int 33)) |
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|
1644 ]) |
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|
1645 ] |
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1646 ) |
0 | 1647 |
1648 (define_expand "untyped_call" | |
67
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1649 [(parallel [(call (match_operand 0 "") |
0 | 1650 (const_int 0)) |
67
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1651 (match_operand 1 "") |
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1652 (match_operand 2 "")])] |
0 | 1653 "" |
1654 { | |
1655 int i; | |
1656 | |
1657 emit_call_insn (gen_call (operands[0], const0_rtx)); | |
1658 | |
1659 for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
1660 { | |
1661 rtx set = XVECEXP (operands[2], 0, i); | |
1662 emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
1663 } | |
1664 DONE; | |
67
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1665 }) |
0 | 1666 |
1667 (define_insn "nop" | |
1668 [(const_int 0)] | |
1669 "" | |
1670 "nop" | |
67
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1671 ) |
0 | 1672 |
1673 ;; ---------------------------------------------------------------------- | |
1674 ;; EXTEND INSTRUCTIONS | |
1675 ;; ---------------------------------------------------------------------- | |
1676 | |
67
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1677 (define_insn "zero_extendqisi2" |
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1678 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
0 | 1679 (zero_extend:SI |
67
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1680 (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))] |
0 | 1681 "" |
1682 "@ | |
67
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1683 extbu %0 |
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1684 movbu %1,%0 |
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1685 extbu %1,%0" |
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1686 [(set_attr "isa" "*,*,am33") |
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1687 (set_attr_alternative "timings" |
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1688 [(const_int 11) |
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1689 (if_then_else (eq_attr "cpu" "am34") |
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1690 (const_int 13) (const_int 24)) |
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1691 (const_int 11) |
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|
1692 ])] |
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1693 ) |
0 | 1694 |
67
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1695 (define_insn "zero_extendhisi2" |
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1696 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
0 | 1697 (zero_extend:SI |
67
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1698 (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))] |
0 | 1699 "" |
1700 "@ | |
67
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|
1701 exthu %0 |
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1702 movhu %1,%0 |
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1703 exthu %1,%0" |
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1704 [(set_attr "isa" "*,*,am33") |
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|
1705 (set_attr_alternative "timings" |
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1706 [(const_int 11) |
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|
1707 (if_then_else (eq_attr "cpu" "am34") |
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|
1708 (const_int 13) (const_int 24)) |
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|
1709 (const_int 11)])] |
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|
1710 ) |
0 | 1711 |
67
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|
1712 (define_insn "extendqisi2" |
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1713 [(set (match_operand:SI 0 "register_operand" "=D,r") |
0 | 1714 (sign_extend:SI |
67
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|
1715 (match_operand:QI 1 "register_operand" "0,r")))] |
0 | 1716 "" |
1717 "@ | |
67
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changeset
|
1718 extb %0 |
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|
1719 extb %1,%0" |
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1720 [(set_attr "isa" "*,am33")] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1721 ) |
0 | 1722 |
67
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diff
changeset
|
1723 (define_insn "extendhisi2" |
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1724 [(set (match_operand:SI 0 "register_operand" "=D,r") |
0 | 1725 (sign_extend:SI |
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1726 (match_operand:HI 1 "register_operand" "0,r")))] |
0 | 1727 "" |
1728 "@ | |
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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changeset
|
1729 exth %0 |
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|
1730 exth %1,%0" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1731 [(set_attr "isa" "*,am33")] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1732 ) |
0 | 1733 |
1734 ;; ---------------------------------------------------------------------- | |
1735 ;; SHIFTS | |
1736 ;; ---------------------------------------------------------------------- | |
1737 | |
67
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diff
changeset
|
1738 (define_insn "ashlsi3" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1739 [(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r") |
0 | 1740 (ashift:SI |
67
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diff
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|
1741 (match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r") |
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diff
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|
1742 (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r"))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1743 (clobber (reg:CC CC_REG))] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1744 "" |
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|
1745 "@ |
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diff
changeset
|
1746 add %0,%0 |
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diff
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|
1747 asl2 %0 |
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diff
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|
1748 asl2 %0\;add %0,%0 |
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diff
changeset
|
1749 asl2 %0\;asl2 %0 |
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|
1750 asl %S2,%0 |
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|
1751 asl %S2,%0 |
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|
1752 asl %S2,%0 |
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diff
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|
1753 asl %2,%1,%0" |
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|
1754 [(set_attr "isa" "*,*,*,*,*,*,*,am33") |
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|
1755 (set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*") |
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diff
changeset
|
1756 (set_attr "liw_op" "asl") |
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diff
changeset
|
1757 (set_attr "timings" "11,11,22,22,11,11,11,11")] |
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|
1758 ) |
0 | 1759 |
67
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diff
changeset
|
1760 (define_insn "lshrsi3" |
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changeset
|
1761 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") |
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diff
changeset
|
1762 (lshiftrt:SI |
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diff
changeset
|
1763 (match_operand:SI 1 "register_operand" "0,0,0,r") |
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changeset
|
1764 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) |
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1765 (clobber (reg:CC CC_REG))] |
0 | 1766 "" |
1767 "@ | |
67
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1768 lsr %S2,%0 |
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1769 lsr %S2,%0 |
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1770 lsr %S2,%0 |
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1771 lsr %2,%1,%0" |
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1772 [(set_attr "isa" "*,*,*,am33") |
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1773 (set_attr "liw" "op2,op2,*,*") |
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1774 (set_attr "liw_op" "lsr")] |
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1775 ) |
0 | 1776 |
67
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1777 (define_insn "ashrsi3" |
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1778 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") |
0 | 1779 (ashiftrt:SI |
67
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1780 (match_operand:SI 1 "register_operand" "0,0,0,r") |
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1781 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) |
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1782 (clobber (reg:CC CC_REG))] |
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1783 "" |
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1784 "@ |
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1785 asr %S2,%0 |
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1786 asr %S2,%0 |
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1787 asr %S2,%0 |
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1788 asr %2,%1,%0" |
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1789 [(set_attr "isa" "*,*,*,am33") |
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1790 (set_attr "liw" "op2,op2,*,*") |
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1791 (set_attr "liw_op" "asr")] |
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1792 ) |
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1793 |
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1794 ;; ---------------------------------------------------------------------- |
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1795 ;; MISCELANEOUS |
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1796 ;; ---------------------------------------------------------------------- |
0 | 1797 |
67
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1798 (define_expand "clzsi2" |
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1799 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1800 (unspec:SI [(match_operand:SI 1 "register_operand" "") |
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1801 (const_int 0)] UNSPEC_BSCH)) |
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1802 (clobber (reg:CC CC_REG))])] |
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1803 "TARGET_AM33" |
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1804 ) |
0 | 1805 |
67
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1806 (define_insn "*bsch" |
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1807 [(set (match_operand:SI 0 "register_operand" "=r") |
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1808 (unspec:SI [(match_operand:SI 1 "register_operand" "r") |
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1809 (match_operand:SI 2 "nonmemory_operand" "0")] |
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1810 UNSPEC_BSCH)) |
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1811 (clobber (reg:CC CC_REG))] |
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1812 "TARGET_AM33" |
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1813 "bsch %1,%0" |
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1814 ) |
0 | 1815 |
1816 ;; ---------------------------------------------------------------------- | |
1817 ;; FP INSTRUCTIONS | |
1818 ;; ---------------------------------------------------------------------- | |
1819 | |
67
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1820 (define_insn "abssf2" |
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1821 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1822 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))] |
1823 "TARGET_AM33_2" | |
1824 "@ | |
1825 fabs %0 | |
1826 fabs %1, %0" | |
67
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1827 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1828 (const_int 17) (const_int 14)))] |
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1829 ) |
0 | 1830 |
67
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1831 (define_insn "negsf2" |
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1832 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1833 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))] |
1834 "TARGET_AM33_2" | |
1835 "@ | |
1836 fneg %0 | |
1837 fneg %1, %0" | |
67
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1838 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1839 (const_int 17) (const_int 14)))] |
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1840 ) |
0 | 1841 |
1842 (define_expand "sqrtsf2" | |
1843 [(set (match_operand:SF 0 "register_operand" "") | |
1844 (sqrt:SF (match_operand:SF 1 "register_operand" "")))] | |
1845 "TARGET_AM33_2 && flag_unsafe_math_optimizations" | |
1846 { | |
1847 rtx scratch = gen_reg_rtx (SFmode); | |
1848 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); | |
1849 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), | |
1850 scratch)); | |
1851 DONE; | |
67
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1852 }) |
0 | 1853 |
1854 (define_insn "rsqrtsf2" | |
67
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1855 [(set (match_operand:SF 0 "register_operand" "=f,f") |
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1856 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F") |
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1857 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f")))) |
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1858 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1859 "TARGET_AM33_2" |
1860 "@ | |
1861 frsqrt %0 | |
1862 frsqrt %1, %0" | |
67
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1863 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1864 (const_int 4753) (const_int 2327)))] |
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1865 ) |
0 | 1866 |
1867 (define_insn "addsf3" | |
67
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1868 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1869 (plus:SF (match_operand:SF 1 "register_operand" "%0,f") |
67
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1870 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1871 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1872 "TARGET_AM33_2" |
1873 "@ | |
1874 fadd %2, %0 | |
1875 fadd %2, %1, %0" | |
67
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1876 [(set_attr_alternative "timings" |
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1877 [(if_then_else (eq_attr "cpu" "am34") |
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1878 (const_int 17) (const_int 14)) |
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1879 (if_then_else (eq_attr "cpu" "am34") |
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1880 (const_int 17) (const_int 25)) |
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|
1881 ])] |
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1882 ) |
0 | 1883 |
1884 (define_insn "subsf3" | |
67
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1885 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1886 (minus:SF (match_operand:SF 1 "register_operand" "0,f") |
67
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1887 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1888 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1889 "TARGET_AM33_2" |
1890 "@ | |
1891 fsub %2, %0 | |
1892 fsub %2, %1, %0" | |
67
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1893 [(set_attr_alternative "timings" |
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1894 [(if_then_else (eq_attr "cpu" "am34") |
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1895 (const_int 17) (const_int 14)) |
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1896 (if_then_else (eq_attr "cpu" "am34") |
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1897 (const_int 17) (const_int 25)) |
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1898 ])] |
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1899 ) |
0 | 1900 |
1901 (define_insn "mulsf3" | |
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1902 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1903 (mult:SF (match_operand:SF 1 "register_operand" "%0,f") |
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1904 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1905 (clobber (reg:CC_FLOAT CC_REG)) |
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1906 ] |
0 | 1907 "TARGET_AM33_2" |
1908 "@ | |
1909 fmul %2, %0 | |
1910 fmul %2, %1, %0" | |
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1911 [(set_attr_alternative "timings" |
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1912 [(if_then_else (eq_attr "cpu" "am34") |
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1913 (const_int 17) (const_int 14)) |
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1914 (if_then_else (eq_attr "cpu" "am34") |
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1915 (const_int 17) (const_int 25)) |
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1916 ])] |
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1917 ) |
0 | 1918 |
1919 (define_insn "divsf3" | |
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1920 [(set (match_operand:SF 0 "register_operand" "=f,f") |
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1921 (div:SF (match_operand:SF 1 "register_operand" "0,f") |
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1922 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1923 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1924 "TARGET_AM33_2" |
1925 "@ | |
1926 fdiv %2, %0 | |
1927 fdiv %2, %1, %0" | |
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1928 [(set_attr_alternative "timings" |
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1929 [(if_then_else (eq_attr "cpu" "am34") |
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1930 (const_int 2531) (const_int 1216)) |
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1931 (if_then_else (eq_attr "cpu" "am34") |
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1932 (const_int 2531) (const_int 1317)) |
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1933 ])] |
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1934 ) |
0 | 1935 |
67
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1936 (define_insn "fmasf4" |
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1937 [(set (match_operand:SF 0 "register_operand" "=c") |
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1938 (fma:SF (match_operand:SF 1 "register_operand" "f") |
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1939 (match_operand:SF 2 "register_operand" "f") |
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1940 (match_operand:SF 3 "register_operand" "f"))) |
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1941 (clobber (reg:CC_FLOAT CC_REG)) |
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1942 ] |
0 | 1943 "TARGET_AM33_2" |
1944 "fmadd %1, %2, %3, %0" | |
67
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1945 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1946 (const_int 17) (const_int 24)))] |
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1947 ) |
0 | 1948 |
67
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1949 (define_insn "fmssf4" |
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1950 [(set (match_operand:SF 0 "register_operand" "=c") |
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1951 (fma:SF (match_operand:SF 1 "register_operand" "f") |
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1952 (match_operand:SF 2 "register_operand" "f") |
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1953 (neg:SF (match_operand:SF 3 "register_operand" "f")))) |
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1954 (clobber (reg:CC_FLOAT CC_REG)) |
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1955 ] |
0 | 1956 "TARGET_AM33_2" |
1957 "fmsub %1, %2, %3, %0" | |
67
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1958 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1959 (const_int 17) (const_int 24)))] |
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1960 ) |
0 | 1961 |
67
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1962 (define_insn "fnmasf4" |
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1963 [(set (match_operand:SF 0 "register_operand" "=c") |
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1964 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) |
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1965 (match_operand:SF 2 "register_operand" "f") |
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1966 (match_operand:SF 3 "register_operand" "f"))) |
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1967 (clobber (reg:CC_FLOAT CC_REG)) |
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1968 ] |
0 | 1969 "TARGET_AM33_2" |
1970 "fnmadd %1, %2, %3, %0" | |
67
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1971 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1972 (const_int 17) (const_int 24)))] |
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1973 ) |
0 | 1974 |
67
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1975 (define_insn "fnmssf4" |
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1976 [(set (match_operand:SF 0 "register_operand" "=c") |
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1977 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) |
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1978 (match_operand:SF 2 "register_operand" "f") |
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1979 (neg:SF (match_operand:SF 3 "register_operand" "f")))) |
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1980 (clobber (reg:CC_FLOAT CC_REG)) |
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1981 ] |
0 | 1982 "TARGET_AM33_2" |
1983 "fnmsub %1, %2, %3, %0" | |
67
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1984 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1985 (const_int 17) (const_int 24)))] |
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1986 ) |
0 | 1987 |
1988 ;; ---------------------------------------------------------------------- | |
1989 ;; PROLOGUE/EPILOGUE | |
1990 ;; ---------------------------------------------------------------------- | |
1991 (define_expand "prologue" | |
1992 [(const_int 0)] | |
1993 "" | |
67
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1994 { mn10300_expand_prologue (); DONE; } |
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1995 ) |
0 | 1996 |
1997 (define_expand "epilogue" | |
1998 [(return)] | |
1999 "" | |
67
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2000 { mn10300_expand_epilogue (); DONE; } |
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2001 ) |
0 | 2002 |
2003 (define_insn "return" | |
2004 [(return)] | |
67
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2005 "mn10300_can_use_rets_insn ()" |
0 | 2006 { |
67
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2007 /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger. */ |
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2008 if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ()) |
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2009 return "retf [],0"; |
0 | 2010 else |
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2011 return "rets"; |
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2012 }) |
0 | 2013 |
67
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2014 (define_insn "return_ret" |
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2015 [(return) |
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2016 (use (match_operand:SI 0 "const_int_operand" ""))] |
0 | 2017 "" |
2018 { | |
67
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2019 /* The RETF insn is up to 3 cycles faster than RET. */ |
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2020 fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file); |
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2021 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ()); |
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2022 fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0])); |
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2023 return ""; |
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|
2024 }) |
0 | 2025 |
67
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|
2026 ;; This instruction matches one generated by mn10300_gen_multiple_store() |
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parents:
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diff
changeset
|
2027 (define_insn "store_movm" |
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parents:
55
diff
changeset
|
2028 [(match_parallel 0 "mn10300_store_multiple_operation" |
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parents:
55
diff
changeset
|
2029 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])] |
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parents:
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diff
changeset
|
2030 "" |
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diff
changeset
|
2031 { |
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parents:
55
diff
changeset
|
2032 fputs ("\tmovm ", asm_out_file); |
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parents:
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diff
changeset
|
2033 mn10300_print_reg_list (asm_out_file, |
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parents:
55
diff
changeset
|
2034 mn10300_store_multiple_operation (operands[0], |
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changeset
|
2035 VOIDmode)); |
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55
diff
changeset
|
2036 fprintf (asm_out_file, ",(sp)\n"); |
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diff
changeset
|
2037 return ""; |
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diff
changeset
|
2038 } |
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changeset
|
2039 ;; Assume that no more than 8 registers will be pushed. |
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diff
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|
2040 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
2041 (const_int 99) (const_int 88)))] |
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diff
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|
2042 ) |
0 | 2043 |
67
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diff
changeset
|
2044 (define_expand "load_pic" |
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changeset
|
2045 [(const_int 0)] |
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changeset
|
2046 "flag_pic" |
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changeset
|
2047 { |
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diff
changeset
|
2048 if (TARGET_AM33) |
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|
2049 emit_insn (gen_am33_load_pic (pic_offset_table_rtx)); |
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parents:
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|
2050 else if (mn10300_frame_size () == 0) |
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2051 emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx)); |
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changeset
|
2052 else |
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|
2053 emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx)); |
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changeset
|
2054 DONE; |
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|
2055 }) |
0 | 2056 |
67
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diff
changeset
|
2057 (define_insn "am33_load_pic" |
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diff
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|
2058 [(set (match_operand:SI 0 "register_operand" "=a") |
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parents:
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diff
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|
2059 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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|
2060 (clobber (reg:CC CC_REG))] |
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diff
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|
2061 "TARGET_AM33" |
0 | 2062 { |
67
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diff
changeset
|
2063 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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|
2064 return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0"; |
0 | 2065 } |
67
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|
2066 [(set_attr "timings" "33")] |
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diff
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|
2067 ) |
0 | 2068 |
67
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diff
changeset
|
2069 ;; Load pic register with push/pop of stack. |
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|
2070 (define_insn "mn10300_load_pic0" |
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2071 [(set (match_operand:SI 0 "register_operand" "=a") |
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|
2072 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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|
2073 (clobber (reg:SI MDR_REG)) |
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|
2074 (clobber (reg:CC CC_REG))] |
0 | 2075 "" |
2076 { | |
67
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|
2077 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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|
2078 return ("add -4,sp\;" |
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diff
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|
2079 "calls .LPIC%=\n" |
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diff
changeset
|
2080 ".LPIC%=:\;" |
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parents:
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diff
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|
2081 "movm (sp),[%0]\;" |
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diff
changeset
|
2082 "add %1-(.LPIC%=-.),%0"); |
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diff
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|
2083 } |
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diff
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|
2084 [(set_attr "timings" "88")] |
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diff
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|
2085 ) |
0 | 2086 |
67
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diff
changeset
|
2087 ;; Load pic register re-using existing stack space. |
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55
diff
changeset
|
2088 (define_insn "mn10300_load_pic1" |
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diff
changeset
|
2089 [(set (match_operand:SI 0 "register_operand" "=a") |
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diff
changeset
|
2090 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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diff
changeset
|
2091 (clobber (mem:SI (reg:SI SP_REG))) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
2092 (clobber (reg:SI MDR_REG)) |
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parents:
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diff
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|
2093 (clobber (reg:CC CC_REG))] |
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55
diff
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|
2094 "" |
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parents:
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diff
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|
2095 { |
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diff
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|
2096 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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diff
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|
2097 return ("calls .LPIC%=\n" |
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diff
changeset
|
2098 ".LPIC%=:\;" |
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diff
changeset
|
2099 "mov (sp),%0\;" |
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|
2100 "add %1-(.LPIC%=-.),%0"); |
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diff
changeset
|
2101 } |
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|
2102 [(set_attr "timings" "66")] |
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|
2103 ) |
0 | 2104 |
67
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|
2105 ;; The mode on operand 3 has been deliberately omitted because it |
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|
2106 ;; can be either SI (for arithmetic operations) or QI (for shifts). |
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diff
changeset
|
2107 (define_insn "liw" |
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changeset
|
2108 [(set (match_operand:SI 0 "register_operand" "=r") |
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diff
changeset
|
2109 (unspec:SI [(match_dup 0) |
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changeset
|
2110 (match_operand 2 "liw_operand" "rO") |
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diff
changeset
|
2111 (match_operand:SI 4 "const_int_operand" "")] |
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diff
changeset
|
2112 UNSPEC_LIW)) |
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diff
changeset
|
2113 (set (match_operand:SI 1 "register_operand" "=r") |
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diff
changeset
|
2114 (unspec:SI [(match_dup 1) |
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diff
changeset
|
2115 (match_operand 3 "liw_operand" "rO") |
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diff
changeset
|
2116 (match_operand:SI 5 "const_int_operand" "")] |
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changeset
|
2117 UNSPEC_LIW))] |
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diff
changeset
|
2118 "TARGET_ALLOW_LIW" |
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diff
changeset
|
2119 "%W4_%W5 %2, %0, %3, %1" |
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diff
changeset
|
2120 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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diff
changeset
|
2121 (const_int 13) (const_int 12)))] |
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diff
changeset
|
2122 ) |
0 | 2123 |
67
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2124 ;; The mode on operand 1 has been deliberately omitted because it |
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2125 ;; can be either SI (for arithmetic operations) or QI (for shifts). |
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2126 (define_insn "cmp_liw" |
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2127 [(set (reg:CC CC_REG) |
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2128 (compare:CC (match_operand:SI 2 "register_operand" "r") |
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2129 (match_operand 3 "liw_operand" "rO"))) |
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2130 (set (match_operand:SI 0 "register_operand" "=r") |
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2131 (unspec:SI [(match_dup 0) |
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2132 (match_operand 1 "liw_operand" "rO") |
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2133 (match_operand:SI 4 "const_int_operand" "")] |
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2134 UNSPEC_LIW))] |
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2135 "TARGET_ALLOW_LIW" |
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2136 "cmp_%W4 %3, %2, %1, %0" |
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2137 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2138 (const_int 13) (const_int 12)))] |
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2139 ) |
0 | 2140 |
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2141 (define_insn "liw_cmp" |
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2142 [(set (match_operand:SI 0 "register_operand" "=r") |
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2143 (unspec:SI [(match_dup 0) |
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2144 (match_operand 1 "liw_operand" "rO") |
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2145 (match_operand:SI 4 "const_int_operand" "")] |
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2146 UNSPEC_LIW)) |
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2147 (set (reg:CC CC_REG) |
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2148 (compare:CC (match_operand:SI 2 "register_operand" "r") |
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2149 (match_operand 3 "liw_operand" "rO")))] |
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2150 "TARGET_ALLOW_LIW" |
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2151 "%W4_cmp %1, %0, %3, %2" |
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2152 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2153 (const_int 13) (const_int 12)))] |
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2154 ) |