Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/rs6000.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
---|---|
date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | 77e2b8dfacca |
children | 04ced10e8804 |
rev | line source |
---|---|
0 | 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
4 2010, 2011 |
0 | 5 Free Software Foundation, Inc. |
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) | |
7 | |
8 This file is part of GCC. | |
9 | |
10 GCC is free software; you can redistribute it and/or modify it | |
11 under the terms of the GNU General Public License as published | |
12 by the Free Software Foundation; either version 3, or (at your | |
13 option) any later version. | |
14 | |
15 GCC is distributed in the hope that it will be useful, but WITHOUT | |
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 License for more details. | |
19 | |
20 Under Section 7 of GPL version 3, you are granted additional | |
21 permissions described in the GCC Runtime Library Exception, version | |
22 3.1, as published by the Free Software Foundation. | |
23 | |
24 You should have received a copy of the GNU General Public License and | |
25 a copy of the GCC Runtime Library Exception along with this program; | |
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
27 <http://www.gnu.org/licenses/>. */ | |
28 | |
29 /* Note that some other tm.h files include this one and then override | |
30 many of the definitions. */ | |
31 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
32 #ifndef RS6000_OPTS_H |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
33 #include "config/rs6000/rs6000-opts.h" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
34 #endif |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
35 |
0 | 36 /* Definitions for the object file format. These are set at |
37 compile-time. */ | |
38 | |
39 #define OBJECT_XCOFF 1 | |
40 #define OBJECT_ELF 2 | |
41 #define OBJECT_PEF 3 | |
42 #define OBJECT_MACHO 4 | |
43 | |
44 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) | |
45 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) | |
46 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) | |
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) | |
48 | |
49 #ifndef TARGET_AIX | |
50 #define TARGET_AIX 0 | |
51 #endif | |
52 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
53 #ifndef TARGET_AIX_OS |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
54 #define TARGET_AIX_OS 0 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
55 #endif |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
56 |
0 | 57 /* Control whether function entry points use a "dot" symbol when |
58 ABI_AIX. */ | |
59 #define DOT_SYMBOLS 1 | |
60 | |
61 /* Default string to use for cpu if not specified. */ | |
62 #ifndef TARGET_CPU_DEFAULT | |
63 #define TARGET_CPU_DEFAULT ((char *)0) | |
64 #endif | |
65 | |
66 /* If configured for PPC405, support PPC405CR Erratum77. */ | |
67 #ifdef CONFIG_PPC405CR | |
68 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) | |
69 #else | |
70 #define PPC405_ERRATUM77 0 | |
71 #endif | |
72 | |
73 #ifndef TARGET_PAIRED_FLOAT | |
74 #define TARGET_PAIRED_FLOAT 0 | |
75 #endif | |
76 | |
77 #ifdef HAVE_AS_POPCNTB | |
78 #define ASM_CPU_POWER5_SPEC "-mpower5" | |
79 #else | |
80 #define ASM_CPU_POWER5_SPEC "-mpower4" | |
81 #endif | |
82 | |
83 #ifdef HAVE_AS_DFP | |
84 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
85 #else | |
86 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
87 #endif | |
88 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
89 #ifdef HAVE_AS_POPCNTD |
0 | 90 #define ASM_CPU_POWER7_SPEC "-mpower7" |
91 #else | |
92 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
93 #endif | |
94 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
95 #ifdef HAVE_AS_DCI |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
96 #define ASM_CPU_476_SPEC "-m476" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
97 #else |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
98 #define ASM_CPU_476_SPEC "-mpower4" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
99 #endif |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
100 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
101 /* Common ASM definitions used by ASM_SPEC among the various targets for |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
102 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
103 provide the default assembler options if the user uses -mcpu=native, so if |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
104 you make changes here, make them also there. */ |
0 | 105 #define ASM_CPU_SPEC \ |
106 "%{!mcpu*: \ | |
107 %{mpower: %{!mpower2: -mpwr}} \ | |
108 %{mpower2: -mpwrx} \ | |
109 %{mpowerpc64*: -mppc64} \ | |
110 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ | |
111 %{mno-power: %{!mpowerpc*: -mcom}} \ | |
112 %{!mno-power: %{!mpower*: %(asm_default)}}} \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
113 %{mcpu=native: %(asm_cpu_native)} \ |
0 | 114 %{mcpu=common: -mcom} \ |
115 %{mcpu=cell: -mcell} \ | |
116 %{mcpu=power: -mpwr} \ | |
117 %{mcpu=power2: -mpwrx} \ | |
118 %{mcpu=power3: -mppc64} \ | |
119 %{mcpu=power4: -mpower4} \ | |
120 %{mcpu=power5: %(asm_cpu_power5)} \ | |
121 %{mcpu=power5+: %(asm_cpu_power5)} \ | |
122 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
123 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
124 %{mcpu=power7: %(asm_cpu_power7)} \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
125 %{mcpu=a2: -ma2} \ |
0 | 126 %{mcpu=powerpc: -mppc} \ |
127 %{mcpu=rios: -mpwr} \ | |
128 %{mcpu=rios1: -mpwr} \ | |
129 %{mcpu=rios2: -mpwrx} \ | |
130 %{mcpu=rsc: -mpwr} \ | |
131 %{mcpu=rsc1: -mpwr} \ | |
132 %{mcpu=rs64a: -mppc64} \ | |
133 %{mcpu=401: -mppc} \ | |
134 %{mcpu=403: -m403} \ | |
135 %{mcpu=405: -m405} \ | |
136 %{mcpu=405fp: -m405} \ | |
137 %{mcpu=440: -m440} \ | |
138 %{mcpu=440fp: -m440} \ | |
139 %{mcpu=464: -m440} \ | |
140 %{mcpu=464fp: -m440} \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
141 %{mcpu=476: %(asm_cpu_476)} \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
142 %{mcpu=476fp: %(asm_cpu_476)} \ |
0 | 143 %{mcpu=505: -mppc} \ |
144 %{mcpu=601: -m601} \ | |
145 %{mcpu=602: -mppc} \ | |
146 %{mcpu=603: -mppc} \ | |
147 %{mcpu=603e: -mppc} \ | |
148 %{mcpu=ec603e: -mppc} \ | |
149 %{mcpu=604: -mppc} \ | |
150 %{mcpu=604e: -mppc} \ | |
151 %{mcpu=620: -mppc64} \ | |
152 %{mcpu=630: -mppc64} \ | |
153 %{mcpu=740: -mppc} \ | |
154 %{mcpu=750: -mppc} \ | |
155 %{mcpu=G3: -mppc} \ | |
156 %{mcpu=7400: -mppc -maltivec} \ | |
157 %{mcpu=7450: -mppc -maltivec} \ | |
158 %{mcpu=G4: -mppc -maltivec} \ | |
159 %{mcpu=801: -mppc} \ | |
160 %{mcpu=821: -mppc} \ | |
161 %{mcpu=823: -mppc} \ | |
162 %{mcpu=860: -mppc} \ | |
163 %{mcpu=970: -mpower4 -maltivec} \ | |
164 %{mcpu=G5: -mpower4 -maltivec} \ | |
165 %{mcpu=8540: -me500} \ | |
166 %{mcpu=8548: -me500} \ | |
167 %{mcpu=e300c2: -me300} \ | |
168 %{mcpu=e300c3: -me300} \ | |
169 %{mcpu=e500mc: -me500mc} \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
170 %{mcpu=e500mc64: -me500mc64} \ |
0 | 171 %{maltivec: -maltivec} \ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
172 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
0 | 173 -many" |
174 | |
175 #define CPP_DEFAULT_SPEC "" | |
176 | |
177 #define ASM_DEFAULT_SPEC "" | |
178 | |
179 /* This macro defines names of additional specifications to put in the specs | |
180 that can be used in various specifications like CC1_SPEC. Its definition | |
181 is an initializer with a subgrouping for each command option. | |
182 | |
183 Each subgrouping contains a string constant, that defines the | |
184 specification name, and a string constant that used by the GCC driver | |
185 program. | |
186 | |
187 Do not define this macro if it does not need to do anything. */ | |
188 | |
189 #define SUBTARGET_EXTRA_SPECS | |
190 | |
191 #define EXTRA_SPECS \ | |
192 { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
193 { "asm_cpu", ASM_CPU_SPEC }, \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
194 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
0 | 195 { "asm_default", ASM_DEFAULT_SPEC }, \ |
196 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
197 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ | |
198 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
199 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
200 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
0 | 201 SUBTARGET_EXTRA_SPECS |
202 | |
203 /* -mcpu=native handling only makes sense with compiler running on | |
204 an PowerPC chip. If changing this condition, also change | |
205 the condition in driver-rs6000.c. */ | |
206 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
207 /* In driver-rs6000.c. */ | |
208 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
209 #define EXTRA_SPEC_FUNCTIONS \ | |
210 { "local_cpu_detect", host_detect_local_cpu }, | |
211 #define HAVE_LOCAL_CPU_DETECT | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
212 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
213 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
214 #else |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
215 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" |
0 | 216 #endif |
217 | |
218 #ifndef CC1_CPU_SPEC | |
219 #ifdef HAVE_LOCAL_CPU_DETECT | |
220 #define CC1_CPU_SPEC \ | |
221 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
222 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
223 #else | |
224 #define CC1_CPU_SPEC "" | |
225 #endif | |
226 #endif | |
227 | |
228 /* Architecture type. */ | |
229 | |
230 /* Define TARGET_MFCRF if the target assembler does not support the | |
231 optional field operand for mfcr. */ | |
232 | |
233 #ifndef HAVE_AS_MFCRF | |
234 #undef TARGET_MFCRF | |
235 #define TARGET_MFCRF 0 | |
236 #endif | |
237 | |
238 /* Define TARGET_POPCNTB if the target assembler does not support the | |
239 popcount byte instruction. */ | |
240 | |
241 #ifndef HAVE_AS_POPCNTB | |
242 #undef TARGET_POPCNTB | |
243 #define TARGET_POPCNTB 0 | |
244 #endif | |
245 | |
246 /* Define TARGET_FPRND if the target assembler does not support the | |
247 fp rounding instructions. */ | |
248 | |
249 #ifndef HAVE_AS_FPRND | |
250 #undef TARGET_FPRND | |
251 #define TARGET_FPRND 0 | |
252 #endif | |
253 | |
254 /* Define TARGET_CMPB if the target assembler does not support the | |
255 cmpb instruction. */ | |
256 | |
257 #ifndef HAVE_AS_CMPB | |
258 #undef TARGET_CMPB | |
259 #define TARGET_CMPB 0 | |
260 #endif | |
261 | |
262 /* Define TARGET_MFPGPR if the target assembler does not support the | |
263 mffpr and mftgpr instructions. */ | |
264 | |
265 #ifndef HAVE_AS_MFPGPR | |
266 #undef TARGET_MFPGPR | |
267 #define TARGET_MFPGPR 0 | |
268 #endif | |
269 | |
270 /* Define TARGET_DFP if the target assembler does not support decimal | |
271 floating point instructions. */ | |
272 #ifndef HAVE_AS_DFP | |
273 #undef TARGET_DFP | |
274 #define TARGET_DFP 0 | |
275 #endif | |
276 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
277 /* Define TARGET_POPCNTD if the target assembler does not support the |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
278 popcount word and double word instructions. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
279 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
280 #ifndef HAVE_AS_POPCNTD |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
281 #undef TARGET_POPCNTD |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
282 #define TARGET_POPCNTD 0 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
283 #endif |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
284 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
285 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
286 not, generate the lwsync code as an integer constant. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
287 #ifdef HAVE_AS_LWSYNC |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
288 #define TARGET_LWSYNC_INSTRUCTION 1 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
289 #else |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
290 #define TARGET_LWSYNC_INSTRUCTION 0 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
291 #endif |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
292 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
293 /* Define TARGET_TLS_MARKERS if the target assembler does not support |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
294 arg markers for __tls_get_addr calls. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
295 #ifndef HAVE_AS_TLS_MARKERS |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
296 #undef TARGET_TLS_MARKERS |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
297 #define TARGET_TLS_MARKERS 0 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
298 #else |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
299 #define TARGET_TLS_MARKERS tls_markers |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
300 #endif |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
301 |
0 | 302 #ifndef TARGET_SECURE_PLT |
303 #define TARGET_SECURE_PLT 0 | |
304 #endif | |
305 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
306 #ifndef TARGET_CMODEL |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
307 #define TARGET_CMODEL CMODEL_SMALL |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
308 #endif |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
309 |
0 | 310 #define TARGET_32BIT (! TARGET_64BIT) |
311 | |
312 #ifndef HAVE_AS_TLS | |
313 #define HAVE_AS_TLS 0 | |
314 #endif | |
315 | |
316 /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
317 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
318 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
319 | |
320 #ifdef IN_LIBGCC2 | |
321 /* For libgcc2 we make sure this is a compile time constant */ | |
322 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) | |
323 #undef TARGET_POWERPC64 | |
324 #define TARGET_POWERPC64 1 | |
325 #else | |
326 #undef TARGET_POWERPC64 | |
327 #define TARGET_POWERPC64 0 | |
328 #endif | |
329 #else | |
330 /* The option machinery will define this. */ | |
331 #endif | |
332 | |
333 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) | |
334 | |
335 /* FPU operations supported. | |
336 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
337 also test TARGET_HARD_FLOAT. */ | |
338 #define TARGET_SINGLE_FLOAT 1 | |
339 #define TARGET_DOUBLE_FLOAT 1 | |
340 #define TARGET_SINGLE_FPU 0 | |
341 #define TARGET_SIMPLE_FPU 0 | |
342 #define TARGET_XILINX_FPU 0 | |
343 | |
344 /* Recast the processor type to the cpu attribute. */ | |
345 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
346 | |
347 /* Define generic processor types based upon current deployment. */ | |
348 #define PROCESSOR_COMMON PROCESSOR_PPC601 | |
349 #define PROCESSOR_POWER PROCESSOR_RIOS1 | |
350 #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
351 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
352 | |
353 /* Define the default processor. This is overridden by other tm.h files. */ | |
354 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 | |
355 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A | |
356 | |
357 extern enum fpu_type_t fpu_type; | |
358 | |
359 /* Specify the dialect of assembler to use. New mnemonics is dialect one | |
360 and the old mnemonics are dialect zero. */ | |
361 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) | |
362 | |
363 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ | |
364 struct rs6000_cpu_select | |
365 { | |
366 const char *string; | |
367 const char *name; | |
368 int set_tune_p; | |
369 int set_arch_p; | |
370 }; | |
371 | |
372 extern struct rs6000_cpu_select rs6000_select[]; | |
373 | |
374 /* Debug support */ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
375 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
376 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
377 #define MASK_DEBUG_REG 0x04 /* debug register handling */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
378 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
379 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
380 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
381 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
382 | MASK_DEBUG_ARG \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
383 | MASK_DEBUG_REG \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
384 | MASK_DEBUG_ADDR \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
385 | MASK_DEBUG_COST \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
386 | MASK_DEBUG_TARGET) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
387 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
388 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
389 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
390 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
391 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
392 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
393 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
394 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
395 extern enum rs6000_vector rs6000_vector_unit[]; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
396 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
397 #define VECTOR_UNIT_NONE_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
398 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
399 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
400 #define VECTOR_UNIT_VSX_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
401 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
402 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
403 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
404 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
405 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
406 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
407 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
408 || rs6000_vector_unit[(MODE)] == VECTOR_VSX) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
409 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
410 /* Describe whether to use VSX loads or Altivec loads. For now, just use the |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
411 same unit as the vector unit we are using, but we may want to migrate to |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
412 using VSX style loads even for types handled by altivec. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
413 extern enum rs6000_vector rs6000_vector_mem[]; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
414 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
415 #define VECTOR_MEM_NONE_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
416 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
417 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
418 #define VECTOR_MEM_VSX_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
419 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
420 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
421 #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
422 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
423 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
424 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
425 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
426 || rs6000_vector_mem[(MODE)] == VECTOR_VSX) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
427 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
428 /* Return the alignment of a given vector type, which is set based on the |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
429 vector unit use. VSX for instance can load 32 or 64 bit aligned words |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
430 without problems, while Altivec requires 128-bit aligned vectors. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
431 extern int rs6000_vector_align[]; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
432 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
433 #define VECTOR_ALIGN(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
434 ((rs6000_vector_align[(MODE)] != 0) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
435 ? rs6000_vector_align[(MODE)] \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
436 : (int)GET_MODE_BITSIZE ((MODE))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
437 |
0 | 438 /* Alignment options for fields in structures for sub-targets following |
439 AIX-like ABI. | |
440 ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
441 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
442 | |
443 Override the macro definitions when compiling libobjc to avoid undefined | |
444 reference to rs6000_alignment_flags due to library's use of GCC alignment | |
445 macros which use the macros below. */ | |
446 | |
447 #ifndef IN_TARGET_LIBS | |
448 #define MASK_ALIGN_POWER 0x00000000 | |
449 #define MASK_ALIGN_NATURAL 0x00000001 | |
450 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
451 #else | |
452 #define TARGET_ALIGN_NATURAL 0 | |
453 #endif | |
454 | |
455 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
456 #define TARGET_IEEEQUAD rs6000_ieeequad | |
457 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
458 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
0 | 459 |
460 #define TARGET_SPE_ABI 0 | |
461 #define TARGET_SPE 0 | |
462 #define TARGET_E500 0 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
463 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
0 | 464 #define TARGET_FPRS 1 |
465 #define TARGET_E500_SINGLE 0 | |
466 #define TARGET_E500_DOUBLE 0 | |
467 #define CHECK_E500_OPTIONS do { } while (0) | |
468 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
469 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
470 Enable 32-bit fcfid's on any of the switches for newer ISA machines or |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
471 XILINX. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
472 #define TARGET_FCFID (TARGET_POWERPC64 \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
473 || TARGET_POPCNTB /* ISA 2.02 */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
474 || TARGET_CMPB /* ISA 2.05 */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
475 || TARGET_POPCNTD /* ISA 2.06 */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
476 || TARGET_XILINX_FPU) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
477 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
478 #define TARGET_FCTIDZ TARGET_FCFID |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
479 #define TARGET_STFIWX TARGET_PPC_GFXOPT |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
480 #define TARGET_LFIWAX TARGET_CMPB |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
481 #define TARGET_LFIWZX TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
482 #define TARGET_FCFIDS TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
483 #define TARGET_FCFIDU TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
484 #define TARGET_FCFIDUS TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
485 #define TARGET_FCTIDUZ TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
486 #define TARGET_FCTIWUZ TARGET_POPCNTD |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
487 |
0 | 488 /* E500 processors only support plain "sync", not lwsync. */ |
489 #define TARGET_NO_LWSYNC TARGET_E500 | |
490 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
491 /* Which machine supports the various reciprocal estimate instructions. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
492 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
493 && TARGET_FPRS && TARGET_SINGLE_FLOAT) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
494 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
495 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
496 && TARGET_DOUBLE_FLOAT \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
497 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
498 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
499 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
500 && TARGET_FPRS && TARGET_SINGLE_FLOAT) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
501 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
502 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
503 && TARGET_DOUBLE_FLOAT \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
504 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
505 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
506 /* Whether the various reciprocal divide/square root estimate instructions |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
507 exist, and whether we should automatically generate code for the instruction |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
508 by default. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
509 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
510 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
511 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
512 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
513 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
514 extern unsigned char rs6000_recip_bits[]; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
515 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
516 #define RS6000_RECIP_HAVE_RE_P(MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
517 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
518 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
519 #define RS6000_RECIP_AUTO_RE_P(MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
520 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
521 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
522 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
523 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
524 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
525 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
526 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
527 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
528 #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
529 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
530 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
531 /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
532 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT |
0 | 533 |
534 /* Target pragma. */ | |
535 #define REGISTER_TARGET_PRAGMAS() do { \ | |
536 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
537 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
0 | 538 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
539 } while (0) | |
540 | |
541 /* Target #defines. */ | |
542 #define TARGET_CPU_CPP_BUILTINS() \ | |
543 rs6000_cpu_cpp_builtins (pfile) | |
544 | |
545 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
546 we're compiling for. Some configurations may need to override it. */ | |
547 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
548 do \ | |
549 { \ | |
550 if (BYTES_BIG_ENDIAN) \ | |
551 { \ | |
552 builtin_define ("__BIG_ENDIAN__"); \ | |
553 builtin_define ("_BIG_ENDIAN"); \ | |
554 builtin_assert ("machine=bigendian"); \ | |
555 } \ | |
556 else \ | |
557 { \ | |
558 builtin_define ("__LITTLE_ENDIAN__"); \ | |
559 builtin_define ("_LITTLE_ENDIAN"); \ | |
560 builtin_assert ("machine=littleendian"); \ | |
561 } \ | |
562 } \ | |
563 while (0) | |
564 | |
565 /* Target machine storage layout. */ | |
566 | |
567 /* Define this macro if it is advisable to hold scalars in registers | |
568 in a wider mode than that declared by the program. In such cases, | |
569 the value is constrained to be within the bounds of the declared | |
570 type, but kept valid in the wider mode. The signedness of the | |
571 extension may differ from that of the type. */ | |
572 | |
573 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
574 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
575 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
576 (MODE) = TARGET_32BIT ? SImode : DImode; | |
577 | |
578 /* Define this if most significant bit is lowest numbered | |
579 in instructions that operate on numbered bit-fields. */ | |
580 /* That is true on RS/6000. */ | |
581 #define BITS_BIG_ENDIAN 1 | |
582 | |
583 /* Define this if most significant byte of a word is the lowest numbered. */ | |
584 /* That is true on RS/6000. */ | |
585 #define BYTES_BIG_ENDIAN 1 | |
586 | |
587 /* Define this if most significant word of a multiword number is lowest | |
588 numbered. | |
589 | |
590 For RS/6000 we can decide arbitrarily since there are no machine | |
591 instructions for them. Might as well be consistent with bits and bytes. */ | |
592 #define WORDS_BIG_ENDIAN 1 | |
593 | |
594 #define MAX_BITS_PER_WORD 64 | |
595 | |
596 /* Width of a word, in units (bytes). */ | |
597 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) | |
598 #ifdef IN_LIBGCC2 | |
599 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
600 #else | |
601 #define MIN_UNITS_PER_WORD 4 | |
602 #endif | |
603 #define UNITS_PER_FP_WORD 8 | |
604 #define UNITS_PER_ALTIVEC_WORD 16 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
605 #define UNITS_PER_VSX_WORD 16 |
0 | 606 #define UNITS_PER_SPE_WORD 8 |
607 #define UNITS_PER_PAIRED_WORD 8 | |
608 | |
609 /* Type used for ptrdiff_t, as a string used in a declaration. */ | |
610 #define PTRDIFF_TYPE "int" | |
611 | |
612 /* Type used for size_t, as a string used in a declaration. */ | |
613 #define SIZE_TYPE "long unsigned int" | |
614 | |
615 /* Type used for wchar_t, as a string used in a declaration. */ | |
616 #define WCHAR_TYPE "short unsigned int" | |
617 | |
618 /* Width of wchar_t in bits. */ | |
619 #define WCHAR_TYPE_SIZE 16 | |
620 | |
621 /* A C expression for the size in bits of the type `short' on the | |
622 target machine. If you don't define this, the default is half a | |
623 word. (If this would be less than one storage unit, it is | |
624 rounded up to one unit.) */ | |
625 #define SHORT_TYPE_SIZE 16 | |
626 | |
627 /* A C expression for the size in bits of the type `int' on the | |
628 target machine. If you don't define this, the default is one | |
629 word. */ | |
630 #define INT_TYPE_SIZE 32 | |
631 | |
632 /* A C expression for the size in bits of the type `long' on the | |
633 target machine. If you don't define this, the default is one | |
634 word. */ | |
635 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) | |
636 | |
637 /* A C expression for the size in bits of the type `long long' on the | |
638 target machine. If you don't define this, the default is two | |
639 words. */ | |
640 #define LONG_LONG_TYPE_SIZE 64 | |
641 | |
642 /* A C expression for the size in bits of the type `float' on the | |
643 target machine. If you don't define this, the default is one | |
644 word. */ | |
645 #define FLOAT_TYPE_SIZE 32 | |
646 | |
647 /* A C expression for the size in bits of the type `double' on the | |
648 target machine. If you don't define this, the default is two | |
649 words. */ | |
650 #define DOUBLE_TYPE_SIZE 64 | |
651 | |
652 /* A C expression for the size in bits of the type `long double' on | |
653 the target machine. If you don't define this, the default is two | |
654 words. */ | |
655 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size | |
656 | |
657 /* Define this to set long double type size to use in libgcc2.c, which can | |
658 not depend on target_flags. */ | |
659 #ifdef __LONG_DOUBLE_128__ | |
660 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
661 #else | |
662 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
663 #endif | |
664 | |
665 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ | |
666 #define WIDEST_HARDWARE_FP_SIZE 64 | |
667 | |
668 /* Width in bits of a pointer. | |
669 See also the macro `Pmode' defined below. */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
670 extern unsigned rs6000_pointer_size; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
671 #define POINTER_SIZE rs6000_pointer_size |
0 | 672 |
673 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
674 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) | |
675 | |
676 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
677 #define STACK_BOUNDARY \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
678 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
679 ? 64 : 128) |
0 | 680 |
681 /* Allocation boundary (in *bits*) for the code of a function. */ | |
682 #define FUNCTION_BOUNDARY 32 | |
683 | |
684 /* No data type wants to be aligned rounder than this. */ | |
685 #define BIGGEST_ALIGNMENT 128 | |
686 | |
687 /* A C expression to compute the alignment for a variables in the | |
688 local store. TYPE is the data type, and ALIGN is the alignment | |
689 that the object would ordinarily have. */ | |
690 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
691 DATA_ALIGNMENT (TYPE, ALIGN) |
0 | 692 |
693 /* Alignment of field after `int : 0' in a structure. */ | |
694 #define EMPTY_FIELD_BOUNDARY 32 | |
695 | |
696 /* Every structure's size must be a multiple of this. */ | |
697 #define STRUCTURE_SIZE_BOUNDARY 8 | |
698 | |
699 /* Return 1 if a structure or array containing FIELD should be | |
700 accessed using `BLKMODE'. | |
701 | |
702 For the SPE, simd types are V2SI, and gcc can be tempted to put the | |
703 entire thing in a DI and use subregs to access the internals. | |
704 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the | |
705 back-end. Because a single GPR can hold a V2SI, but not a DI, the | |
706 best thing to do is set structs to BLKmode and avoid Severe Tire | |
707 Damage. | |
708 | |
709 On e500 v2, DF and DI modes suffer from the same anomaly. DF can | |
710 fit into 1, whereas DI still needs two. */ | |
711 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ | |
712 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ | |
713 || (TARGET_E500_DOUBLE && (MODE) == DFmode)) | |
714 | |
715 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
716 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
717 | |
718 /* Make strings word-aligned so strcpy from constants will be faster. | |
719 Make vector constants quadword aligned. */ | |
720 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
721 (TREE_CODE (EXP) == STRING_CST \ | |
722 && (STRICT_ALIGNMENT || !optimize_size) \ | |
723 && (ALIGN) < BITS_PER_WORD \ | |
724 ? BITS_PER_WORD \ | |
725 : (ALIGN)) | |
726 | |
727 /* Make arrays of chars word-aligned for the same reasons. | |
728 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to | |
729 64 bits. */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
730 #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
731 (TREE_CODE (TYPE) == VECTOR_TYPE \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
732 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
733 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
734 ? 64 : 128) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
735 : ((TARGET_E500_DOUBLE \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
736 && TREE_CODE (TYPE) == REAL_TYPE \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
737 && TYPE_MODE (TYPE) == DFmode) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
738 ? 64 \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
739 : (TREE_CODE (TYPE) == ARRAY_TYPE \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
740 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
741 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) |
0 | 742 |
743 /* Nonzero if move instructions will actually fail to work | |
744 when given unaligned data. */ | |
745 #define STRICT_ALIGNMENT 0 | |
746 | |
747 /* Define this macro to be the value 1 if unaligned accesses have a cost | |
748 many times greater than aligned accesses, for example if they are | |
749 emulated in a trap handler. */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
750 /* Altivec vector memory instructions simply ignore the low bits; SPE vector |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
751 memory instructions trap on unaligned accesses; VSX memory instructions are |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
752 aligned to 4 or 8 bytes. */ |
0 | 753 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
754 (STRICT_ALIGNMENT \ | |
755 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ | |
756 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \ | |
757 || (MODE) == DImode) \ | |
758 && (ALIGN) < 32) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
759 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
760 |
0 | 761 |
762 /* Standard register usage. */ | |
763 | |
764 /* Number of actual hardware registers. | |
765 The hardware registers are assigned numbers for the compiler | |
766 from 0 to just below FIRST_PSEUDO_REGISTER. | |
767 All registers that the compiler knows about must be given numbers, | |
768 even those that are not normally considered general registers. | |
769 | |
770 RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
771 an MQ register, a count register, a link register, and 8 condition | |
772 register fields, which we view here as separate registers. AltiVec | |
773 adds 32 vector registers and a VRsave register. | |
774 | |
775 In addition, the difference between the frame and argument pointers is | |
776 a function of the number of registers saved, so we need to have a | |
777 register for AP that will later be eliminated in favor of SP or FP. | |
778 This is a normal register, but it is fixed. | |
779 | |
780 We also create a pseudo register for float/int conversions, that will | |
781 really represent the memory location used. It is represented here as | |
782 a register, in order to work around problems in allocating stack storage | |
783 in inline functions. | |
784 | |
785 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame | |
786 pointer, which is eventually eliminated in favor of SP or FP. */ | |
787 | |
788 #define FIRST_PSEUDO_REGISTER 114 | |
789 | |
790 /* This must be included for pre gcc 3.0 glibc compatibility. */ | |
791 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 | |
792 | |
793 /* Add 32 dwarf columns for synthetic SPE registers. */ | |
794 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) | |
795 | |
796 /* The SPE has an additional 32 synthetic registers, with DWARF debug | |
797 info numbering for these registers starting at 1200. While eh_frame | |
798 register numbering need not be the same as the debug info numbering, | |
799 we choose to number these regs for eh_frame at 1200 too. This allows | |
800 future versions of the rs6000 backend to add hard registers and | |
801 continue to use the gcc hard register numbering for eh_frame. If the | |
802 extra SPE registers in eh_frame were numbered starting from the | |
803 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER | |
804 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to | |
805 avoid invalidating older SPE eh_frame info. | |
806 | |
807 We must map them here to avoid huge unwinder tables mostly consisting | |
808 of unused space. */ | |
809 #define DWARF_REG_TO_UNWIND_COLUMN(r) \ | |
810 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) | |
811 | |
812 /* Use standard DWARF numbering for DWARF debugging information. */ | |
813 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | |
814 | |
815 /* Use gcc hard register numbering for eh_frame. */ | |
816 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
817 | |
818 /* Map register numbers held in the call frame info that gcc has | |
819 collected using DWARF_FRAME_REGNUM to those that should be output in | |
820 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers | |
821 for .eh_frame, but use the numbers mandated by the various ABIs for | |
822 .debug_frame. rs6000_emit_prologue has translated any combination of | |
823 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves | |
824 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ | |
825 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
826 ((FOR_EH) ? (REGNO) \ | |
827 : (REGNO) == CR2_REGNO ? 64 \ | |
828 : DBX_REGISTER_NUMBER (REGNO)) | |
829 | |
830 /* 1 for registers that have pervasive standard uses | |
831 and are not available for the register allocator. | |
832 | |
833 On RS/6000, r1 is used for the stack. On Darwin, r2 is available | |
834 as a local register; for all other OS's r2 is the TOC pointer. | |
835 | |
836 cr5 is not supposed to be used. | |
837 | |
838 On System V implementations, r13 is fixed and not available for use. */ | |
839 | |
840 #define FIXED_REGISTERS \ | |
841 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ | |
842 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
843 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
844 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
845 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ | |
846 /* AltiVec registers. */ \ | |
847 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
848 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
849 1, 1 \ | |
850 , 1, 1, 1 \ | |
851 } | |
852 | |
853 /* 1 for registers not available across function calls. | |
854 These must include the FIXED_REGISTERS and also any | |
855 registers that can be used without being saved. | |
856 The latter must include the registers where values are returned | |
857 and the register where structure-value addresses are passed. | |
858 Aside from that, you can include as many other registers as you like. */ | |
859 | |
860 #define CALL_USED_REGISTERS \ | |
861 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
863 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
865 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
866 /* AltiVec registers. */ \ | |
867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
868 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
869 1, 1 \ | |
870 , 1, 1, 1 \ | |
871 } | |
872 | |
873 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that | |
874 the entire set of `FIXED_REGISTERS' be included. | |
875 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
876 This macro is optional. If not specified, it defaults to the value | |
877 of `CALL_USED_REGISTERS'. */ | |
878 | |
879 #define CALL_REALLY_USED_REGISTERS \ | |
880 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
882 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
884 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
885 /* AltiVec registers. */ \ | |
886 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
888 0, 0 \ | |
889 , 0, 0, 0 \ | |
890 } | |
891 | |
892 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) | |
893 | |
894 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) | |
895 #define FIRST_SAVED_FP_REGNO (14+32) | |
896 #define FIRST_SAVED_GP_REGNO 13 | |
897 | |
898 /* List the order in which to allocate registers. Each register must be | |
899 listed once, even those in FIXED_REGISTERS. | |
900 | |
901 We allocate in the following order: | |
902 fp0 (not saved or used for anything) | |
903 fp13 - fp2 (not saved; incoming fp arg registers) | |
904 fp1 (not saved; return value) | |
905 fp31 - fp14 (saved; order given to save least number) | |
906 cr7, cr6 (not saved or special) | |
907 cr1 (not saved, but used for FP operations) | |
908 cr0 (not saved, but used for arithmetic operations) | |
909 cr4, cr3, cr2 (saved) | |
910 r0 (not saved; cannot be base reg) | |
911 r9 (not saved; best for TImode) | |
912 r11, r10, r8-r4 (not saved; highest used first to make less conflict) | |
913 r3 (not saved; return value register) | |
914 r31 - r13 (saved; order given to save least number) | |
915 r12 (not saved; if used for DImode or DFmode would use r13) | |
916 mq (not saved; best to use it if we can) | |
917 ctr (not saved; when we have the choice ctr is better) | |
918 lr (saved) | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
919 cr5, r1, r2, ap, ca (fixed) |
0 | 920 v0 - v1 (not saved or used for anything) |
921 v13 - v3 (not saved; incoming vector arg registers) | |
922 v2 (not saved; incoming vector arg reg; return value) | |
923 v19 - v14 (not saved or used for anything) | |
924 v31 - v20 (saved; order given to save least number) | |
925 vrsave, vscr (fixed) | |
926 spe_acc, spefscr (fixed) | |
927 sfp (fixed) | |
928 */ | |
929 | |
930 #if FIXED_R2 == 1 | |
931 #define MAYBE_R2_AVAILABLE | |
932 #define MAYBE_R2_FIXED 2, | |
933 #else | |
934 #define MAYBE_R2_AVAILABLE 2, | |
935 #define MAYBE_R2_FIXED | |
936 #endif | |
937 | |
938 #define REG_ALLOC_ORDER \ | |
939 {32, \ | |
940 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ | |
941 33, \ | |
942 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
943 50, 49, 48, 47, 46, \ | |
944 75, 74, 69, 68, 72, 71, 70, \ | |
945 0, MAYBE_R2_AVAILABLE \ | |
946 9, 11, 10, 8, 7, 6, 5, 4, \ | |
947 3, \ | |
948 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ | |
949 18, 17, 16, 15, 14, 13, 12, \ | |
950 64, 66, 65, \ | |
951 73, 1, MAYBE_R2_FIXED 67, 76, \ | |
952 /* AltiVec registers. */ \ | |
953 77, 78, \ | |
954 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
955 79, \ | |
956 96, 95, 94, 93, 92, 91, \ | |
957 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
958 109, 110, \ | |
959 111, 112, 113 \ | |
960 } | |
961 | |
962 /* True if register is floating-point. */ | |
963 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
964 | |
965 /* True if register is a condition register. */ | |
966 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) | |
967 | |
968 /* True if register is a condition register, but not cr0. */ | |
969 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) | |
970 | |
971 /* True if register is an integer register. */ | |
972 #define INT_REGNO_P(N) \ | |
973 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
974 | |
975 /* SPE SIMD registers are just the GPRs. */ | |
976 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
977 | |
978 /* PAIRED SIMD registers are just the FPRs. */ | |
979 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
980 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
981 /* True if register is the CA register. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
982 #define CA_REGNO_P(N) ((N) == CA_REGNO) |
0 | 983 |
984 /* True if register is an AltiVec register. */ | |
985 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
986 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
987 /* True if register is a VSX register. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
988 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
989 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
990 /* Alternate name for any vector register supporting floating point, no matter |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
991 which instruction set(s) are available. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
992 #define VFLOAT_REGNO_P(N) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
993 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
994 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
995 /* Alternate name for any vector register supporting integer, no matter which |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
996 instruction set(s) are available. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
997 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
998 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
999 /* Alternate name for any vector register supporting logical operations, no |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1000 matter which instruction set(s) are available. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1001 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1002 |
0 | 1003 /* Return number of consecutive hard regs needed starting at reg REGNO |
1004 to hold something of mode MODE. */ | |
1005 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1006 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1007 |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1008 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1009 enough space to account for vectors in FP regs. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1010 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1011 (TARGET_VSX \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1012 && ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1013 || ALTIVEC_VECTOR_MODE (MODE)) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1014 && FP_REGNO_P (REGNO) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1015 ? V2DFmode \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1016 : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1017 |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1018 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1019 (((TARGET_32BIT && TARGET_POWERPC64 \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1020 && (GET_MODE_SIZE (MODE) > 4) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1021 && INT_REGNO_P (REGNO)) ? 1 : 0) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1022 || (TARGET_VSX && FP_REGNO_P (REGNO) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1023 && GET_MODE_SIZE (MODE) > 8)) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1024 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1025 #define VSX_VECTOR_MODE(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1026 ((MODE) == V4SFmode \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1027 || (MODE) == V2DFmode) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1028 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1029 #define VSX_SCALAR_MODE(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1030 ((MODE) == DFmode) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1031 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1032 #define VSX_MODE(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1033 (VSX_VECTOR_MODE (MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1034 || VSX_SCALAR_MODE (MODE)) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1035 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1036 #define VSX_MOVE_MODE(MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1037 (VSX_VECTOR_MODE (MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1038 || VSX_SCALAR_MODE (MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1039 || ALTIVEC_VECTOR_MODE (MODE) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1040 || (MODE) == TImode) |
0 | 1041 |
1042 #define ALTIVEC_VECTOR_MODE(MODE) \ | |
1043 ((MODE) == V16QImode \ | |
1044 || (MODE) == V8HImode \ | |
1045 || (MODE) == V4SFmode \ | |
1046 || (MODE) == V4SImode) | |
1047 | |
1048 #define SPE_VECTOR_MODE(MODE) \ | |
1049 ((MODE) == V4HImode \ | |
1050 || (MODE) == V2SFmode \ | |
1051 || (MODE) == V1DImode \ | |
1052 || (MODE) == V2SImode) | |
1053 | |
1054 #define PAIRED_VECTOR_MODE(MODE) \ | |
1055 ((MODE) == V2SFmode) | |
1056 | |
1057 /* Value is TRUE if hard register REGNO can hold a value of | |
1058 machine-mode MODE. */ | |
1059 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1060 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
1061 | |
1062 /* Value is 1 if it is a good idea to tie two pseudo registers | |
1063 when one has mode MODE1 and one has mode MODE2. | |
1064 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1065 for any hard reg, then this must be 0 for correct output. */ | |
1066 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1067 (SCALAR_FLOAT_MODE_P (MODE1) \ | |
1068 ? SCALAR_FLOAT_MODE_P (MODE2) \ | |
1069 : SCALAR_FLOAT_MODE_P (MODE2) \ | |
1070 ? SCALAR_FLOAT_MODE_P (MODE1) \ | |
1071 : GET_MODE_CLASS (MODE1) == MODE_CC \ | |
1072 ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1073 : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1074 ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
1075 : SPE_VECTOR_MODE (MODE1) \ | |
1076 ? SPE_VECTOR_MODE (MODE2) \ | |
1077 : SPE_VECTOR_MODE (MODE2) \ | |
1078 ? SPE_VECTOR_MODE (MODE1) \ | |
1079 : ALTIVEC_VECTOR_MODE (MODE1) \ | |
1080 ? ALTIVEC_VECTOR_MODE (MODE2) \ | |
1081 : ALTIVEC_VECTOR_MODE (MODE2) \ | |
1082 ? ALTIVEC_VECTOR_MODE (MODE1) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1083 : VSX_VECTOR_MODE (MODE1) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1084 ? VSX_VECTOR_MODE (MODE2) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1085 : VSX_VECTOR_MODE (MODE2) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1086 ? VSX_VECTOR_MODE (MODE1) \ |
0 | 1087 : 1) |
1088 | |
1089 /* Post-reload, we can't use any new AltiVec registers, as we already | |
1090 emitted the vrsave mask. */ | |
1091 | |
1092 #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1093 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) | |
1094 | |
1095 /* Specify the cost of a branch insn; roughly the number of extra insns that | |
1096 should be added to avoid a branch. | |
1097 | |
1098 Set this to 3 on the RS/6000 since that is roughly the average cost of an | |
1099 unscheduled conditional branch. */ | |
1100 | |
1101 #define BRANCH_COST(speed_p, predictable_p) 3 | |
1102 | |
1103 /* Override BRANCH_COST heuristic which empirically produces worse | |
1104 performance for removing short circuiting from the logical ops. */ | |
1105 | |
1106 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
1107 | |
1108 /* A fixed register used at epilogue generation to address SPE registers | |
1109 with negative offsets. The 64-bit load/store instructions on the SPE | |
1110 only take positive offsets (and small ones at that), so we need to | |
1111 reserve a register for consing up negative offsets. */ | |
1112 | |
1113 #define FIXED_SCRATCH 0 | |
1114 | |
1115 /* Specify the registers used for certain standard purposes. | |
1116 The values of these macros are register numbers. */ | |
1117 | |
1118 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1119 /* #define PC_REGNUM */ | |
1120 | |
1121 /* Register to use for pushing function arguments. */ | |
1122 #define STACK_POINTER_REGNUM 1 | |
1123 | |
1124 /* Base register for access to local variables of the function. */ | |
1125 #define HARD_FRAME_POINTER_REGNUM 31 | |
1126 | |
1127 /* Base register for access to local variables of the function. */ | |
1128 #define FRAME_POINTER_REGNUM 113 | |
1129 | |
1130 /* Base register for access to arguments of the function. */ | |
1131 #define ARG_POINTER_REGNUM 67 | |
1132 | |
1133 /* Place to put static chain when calling a function that requires it. */ | |
1134 #define STATIC_CHAIN_REGNUM 11 | |
1135 | |
1136 | |
1137 /* Define the classes of registers for register constraints in the | |
1138 machine description. Also define ranges of constants. | |
1139 | |
1140 One of the classes must always be named ALL_REGS and include all hard regs. | |
1141 If there is more than one class, another class must be named NO_REGS | |
1142 and contain no registers. | |
1143 | |
1144 The name GENERAL_REGS must be the name of a class (or an alias for | |
1145 another name such as ALL_REGS). This is the class of registers | |
1146 that is allowed by "g" or "r" in a register constraint. | |
1147 Also, registers outside this class are allocated only when | |
1148 instructions express preferences for them. | |
1149 | |
1150 The classes must be numbered in nondecreasing order; that is, | |
1151 a larger-numbered class must never be contained completely | |
1152 in a smaller-numbered class. | |
1153 | |
1154 For any two classes, it is very desirable that there be another | |
1155 class that represents their union. */ | |
1156 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1157 /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1158 condition registers, plus three special registers, MQ, CTR, and the link |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1159 register. AltiVec adds a vector register class. VSX registers overlap the |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1160 FPR registers and the Altivec registers. |
0 | 1161 |
1162 However, r0 is special in that it cannot be used as a base register. | |
1163 So make a class for registers valid as base registers. | |
1164 | |
1165 Also, cr0 is the only condition code register that can be used in | |
1166 arithmetic insns, so make a separate class for it. */ | |
1167 | |
1168 enum reg_class | |
1169 { | |
1170 NO_REGS, | |
1171 BASE_REGS, | |
1172 GENERAL_REGS, | |
1173 FLOAT_REGS, | |
1174 ALTIVEC_REGS, | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1175 VSX_REGS, |
0 | 1176 VRSAVE_REGS, |
1177 VSCR_REGS, | |
1178 SPE_ACC_REGS, | |
1179 SPEFSCR_REGS, | |
1180 NON_SPECIAL_REGS, | |
1181 MQ_REGS, | |
1182 LINK_REGS, | |
1183 CTR_REGS, | |
1184 LINK_OR_CTR_REGS, | |
1185 SPECIAL_REGS, | |
1186 SPEC_OR_GEN_REGS, | |
1187 CR0_REGS, | |
1188 CR_REGS, | |
1189 NON_FLOAT_REGS, | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1190 CA_REGS, |
0 | 1191 ALL_REGS, |
1192 LIM_REG_CLASSES | |
1193 }; | |
1194 | |
1195 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1196 | |
1197 /* Give names of register classes as strings for dump file. */ | |
1198 | |
1199 #define REG_CLASS_NAMES \ | |
1200 { \ | |
1201 "NO_REGS", \ | |
1202 "BASE_REGS", \ | |
1203 "GENERAL_REGS", \ | |
1204 "FLOAT_REGS", \ | |
1205 "ALTIVEC_REGS", \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1206 "VSX_REGS", \ |
0 | 1207 "VRSAVE_REGS", \ |
1208 "VSCR_REGS", \ | |
1209 "SPE_ACC_REGS", \ | |
1210 "SPEFSCR_REGS", \ | |
1211 "NON_SPECIAL_REGS", \ | |
1212 "MQ_REGS", \ | |
1213 "LINK_REGS", \ | |
1214 "CTR_REGS", \ | |
1215 "LINK_OR_CTR_REGS", \ | |
1216 "SPECIAL_REGS", \ | |
1217 "SPEC_OR_GEN_REGS", \ | |
1218 "CR0_REGS", \ | |
1219 "CR_REGS", \ | |
1220 "NON_FLOAT_REGS", \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1221 "CA_REGS", \ |
0 | 1222 "ALL_REGS" \ |
1223 } | |
1224 | |
1225 /* Define which registers fit in which classes. | |
1226 This is an initializer for a vector of HARD_REG_SET | |
1227 of length N_REG_CLASSES. */ | |
1228 | |
1229 #define REG_CLASS_CONTENTS \ | |
1230 { \ | |
1231 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
1232 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ | |
1233 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ | |
1234 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ | |
1235 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1236 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ |
0 | 1237 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ |
1238 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ | |
1239 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ | |
1240 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ | |
1241 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ | |
1242 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ | |
1243 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ | |
1244 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ | |
1245 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ | |
1246 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ | |
1247 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ | |
1248 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ | |
1249 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ | |
1250 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1251 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ |
0 | 1252 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ |
1253 } | |
1254 | |
1255 /* The following macro defines cover classes for Integrated Register | |
1256 Allocator. Cover classes is a set of non-intersected register | |
1257 classes covering all hard registers used for register allocation | |
1258 purpose. Any move between two registers of a cover class should be | |
1259 cheaper than load or store of the registers. The macro value is | |
1260 array of register classes with LIM_REG_CLASSES used as the end | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1261 marker. |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1262 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1263 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1264 account for the Altivec and Floating registers being subsets of the VSX |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1265 register set. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1266 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1267 #define IRA_COVER_CLASSES_PRE_VSX \ |
0 | 1268 { \ |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1269 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1270 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1271 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1272 CR_REGS, CA_REGS, LIM_REG_CLASSES \ |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1273 } |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1274 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1275 #define IRA_COVER_CLASSES_VSX \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1276 { \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1277 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1278 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ |
0 | 1279 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1280 CR_REGS, CA_REGS, LIM_REG_CLASSES \ |
0 | 1281 } |
1282 | |
1283 /* The same information, inverted: | |
1284 Return the class number of the smallest class containing | |
1285 reg number REGNO. This could be a conditional expression | |
1286 or could index an array. */ | |
1287 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1288 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1289 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1290 #if ENABLE_CHECKING |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1291 #define REGNO_REG_CLASS(REGNO) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1292 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1293 rs6000_regno_regclass[(REGNO)]) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1294 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1295 #else |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1296 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1297 #endif |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1298 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1299 /* Register classes for various constraints that are based on the target |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1300 switches. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1301 enum r6000_reg_class_enum { |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1302 RS6000_CONSTRAINT_d, /* fpr registers for double values */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1303 RS6000_CONSTRAINT_f, /* fpr registers for single values */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1304 RS6000_CONSTRAINT_v, /* Altivec registers */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1305 RS6000_CONSTRAINT_wa, /* Any VSX register */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1306 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1307 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1308 RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1309 RS6000_CONSTRAINT_MAX |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1310 }; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1311 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1312 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; |
0 | 1313 |
1314 /* The class value for index registers, and the one for base regs. */ | |
1315 #define INDEX_REG_CLASS GENERAL_REGS | |
1316 #define BASE_REG_CLASS BASE_REGS | |
1317 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1318 /* Return whether a given register class can hold VSX objects. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1319 #define VSX_REG_CLASS_P(CLASS) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1320 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1321 |
0 | 1322 /* Given an rtx X being reloaded into a reg required to be |
1323 in class CLASS, return the class of reg to actually use. | |
1324 In general this is just CLASS; but on some machines | |
1325 in some cases it is preferable to use a more restrictive class. | |
1326 | |
1327 On the RS/6000, we have to return NO_REGS when we want to reload a | |
1328 floating-point CONST_DOUBLE to force it to be copied to memory. | |
1329 | |
1330 We also don't want to reload integer values into floating-point | |
1331 registers if we can at all help it. In fact, this can | |
1332 cause reload to die, if it tries to generate a reload of CTR | |
1333 into a FP register and discovers it doesn't have the memory location | |
1334 required. | |
1335 | |
1336 ??? Would it be a good idea to have reload do the converse, that is | |
1337 try to reload floating modes into FP registers if possible? | |
1338 */ | |
1339 | |
1340 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1341 rs6000_preferred_reload_class_ptr (X, CLASS) |
0 | 1342 |
1343 /* Return the register class of a scratch register needed to copy IN into | |
1344 or out of a register in CLASS in MODE. If it can be done directly, | |
1345 NO_REGS is returned. */ | |
1346 | |
1347 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1348 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
0 | 1349 |
1350 /* If we are copying between FP or AltiVec registers and anything | |
1351 else, we need a memory location. The exception is when we are | |
1352 targeting ppc64 and the move to/from fpr to gpr instructions | |
1353 are available.*/ | |
1354 | |
1355 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1356 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
0 | 1357 |
1358 /* For cpus that cannot load/store SDmode values from the 64-bit | |
1359 FP registers without using a full 64-bit load/store, we need | |
1360 to allocate a full 64-bit stack slot for them. */ | |
1361 | |
1362 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ | |
1363 rs6000_secondary_memory_needed_rtx (MODE) | |
1364 | |
1365 /* Return the maximum number of consecutive registers | |
1366 needed to represent mode MODE in a register of class CLASS. | |
1367 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1368 On RS/6000, this is the size of MODE in words, except in the FP regs, where |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1369 a single reg is enough for two words, unless we have VSX, where the FP |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1370 registers can hold 128 bits. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1371 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] |
0 | 1372 |
1373 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ | |
1374 | |
1375 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1376 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
0 | 1377 |
1378 /* Stack layout; function entry, exit and calling. */ | |
1379 | |
1380 /* Define this if pushing a word on the stack | |
1381 makes the stack pointer a smaller address. */ | |
1382 #define STACK_GROWS_DOWNWARD | |
1383 | |
1384 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
1385 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1386 | |
1387 /* Define this to nonzero if the nominal address of the stack frame | |
1388 is at the high-address end of the local variables; | |
1389 that is, each additional local variable allocated | |
1390 goes at a more negative offset in the frame. | |
1391 | |
1392 On the RS/6000, we grow upwards, from the area after the outgoing | |
1393 arguments. */ | |
1394 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0) | |
1395 | |
1396 /* Size of the outgoing register save area */ | |
1397 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ | |
1398 || DEFAULT_ABI == ABI_DARWIN) \ | |
1399 ? (TARGET_64BIT ? 64 : 32) \ | |
1400 : 0) | |
1401 | |
1402 /* Size of the fixed area on the stack */ | |
1403 #define RS6000_SAVE_AREA \ | |
1404 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ | |
1405 << (TARGET_64BIT ? 1 : 0)) | |
1406 | |
1407 /* MEM representing address to save the TOC register */ | |
1408 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
1409 plus_constant (stack_pointer_rtx, \ | |
1410 (TARGET_32BIT ? 20 : 40))) | |
1411 | |
1412 /* Align an address */ | |
1413 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) | |
1414 | |
1415 /* Offset within stack frame to start allocating local variables at. | |
1416 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1417 first local allocated. Otherwise, it is the offset to the BEGINNING | |
1418 of the first local allocated. | |
1419 | |
1420 On the RS/6000, the frame pointer is the same as the stack pointer, | |
1421 except for dynamic allocations. So we start after the fixed area and | |
1422 outgoing parameter area. */ | |
1423 | |
1424 #define STARTING_FRAME_OFFSET \ | |
1425 (FRAME_GROWS_DOWNWARD \ | |
1426 ? 0 \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1427 : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1428 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ |
0 | 1429 + RS6000_SAVE_AREA)) |
1430 | |
1431 /* Offset from the stack pointer register to an item dynamically | |
1432 allocated on the stack, e.g., by `alloca'. | |
1433 | |
1434 The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1435 length of the outgoing arguments. The default is correct for most | |
1436 machines. See `function.c' for details. */ | |
1437 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1438 (RS6000_ALIGN (crtl->outgoing_args_size, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1439 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ |
0 | 1440 + (STACK_POINTER_OFFSET)) |
1441 | |
1442 /* If we generate an insn to push BYTES bytes, | |
1443 this says how many the stack pointer really advances by. | |
1444 On RS/6000, don't define this because there are no push insns. */ | |
1445 /* #define PUSH_ROUNDING(BYTES) */ | |
1446 | |
1447 /* Offset of first parameter from the argument pointer register value. | |
1448 On the RS/6000, we define the argument pointer to the start of the fixed | |
1449 area. */ | |
1450 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA | |
1451 | |
1452 /* Offset from the argument pointer register value to the top of | |
1453 stack. This is different from FIRST_PARM_OFFSET because of the | |
1454 register save area. */ | |
1455 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1456 | |
1457 /* Define this if stack space is still allocated for a parameter passed | |
1458 in a register. The value is the number of bytes allocated to this | |
1459 area. */ | |
1460 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE | |
1461 | |
1462 /* Define this if the above stack space is to be considered part of the | |
1463 space allocated by the caller. */ | |
1464 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
1465 | |
1466 /* This is the difference between the logical top of stack and the actual sp. | |
1467 | |
1468 For the RS/6000, sp points past the fixed area. */ | |
1469 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA | |
1470 | |
1471 /* Define this if the maximum size of all the outgoing args is to be | |
1472 accumulated and pushed during the prologue. The amount can be | |
1473 found in the variable crtl->outgoing_args_size. */ | |
1474 #define ACCUMULATE_OUTGOING_ARGS 1 | |
1475 | |
1476 /* Define how to find the value returned by a library function | |
1477 assuming the value has mode MODE. */ | |
1478 | |
1479 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) | |
1480 | |
1481 /* DRAFT_V4_STRUCT_RET defaults off. */ | |
1482 #define DRAFT_V4_STRUCT_RET 0 | |
1483 | |
1484 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ | |
1485 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1486 | |
1487 /* Mode of stack savearea. | |
1488 FUNCTION is VOIDmode because calling convention maintains SP. | |
1489 BLOCK needs Pmode for SP. | |
1490 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
1491 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
1492 (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
1493 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) | |
1494 | |
1495 /* Minimum and maximum general purpose registers used to hold arguments. */ | |
1496 #define GP_ARG_MIN_REG 3 | |
1497 #define GP_ARG_MAX_REG 10 | |
1498 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1499 | |
1500 /* Minimum and maximum floating point registers used to hold arguments. */ | |
1501 #define FP_ARG_MIN_REG 33 | |
1502 #define FP_ARG_AIX_MAX_REG 45 | |
1503 #define FP_ARG_V4_MAX_REG 40 | |
1504 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ | |
1505 || DEFAULT_ABI == ABI_DARWIN) \ | |
1506 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) | |
1507 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) | |
1508 | |
1509 /* Minimum and maximum AltiVec registers used to hold arguments. */ | |
1510 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1511 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1512 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1513 | |
1514 /* Return registers */ | |
1515 #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1516 #define FP_ARG_RETURN FP_ARG_MIN_REG | |
1517 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) | |
1518 | |
1519 /* Flags for the call/call_value rtl operations set up by function_arg */ | |
1520 #define CALL_NORMAL 0x00000000 /* no special processing */ | |
1521 /* Bits in 0x00000001 are unused. */ | |
1522 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ | |
1523 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1524 #define CALL_LONG 0x00000008 /* always call indirect */ | |
1525 #define CALL_LIBCALL 0x00000010 /* libcall */ | |
1526 | |
1527 /* We don't have prologue and epilogue functions to save/restore | |
1528 everything for most ABIs. */ | |
1529 #define WORLD_SAVE_P(INFO) 0 | |
1530 | |
1531 /* 1 if N is a possible register number for a function value | |
1532 as seen by the caller. | |
1533 | |
1534 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ | |
1535 #define FUNCTION_VALUE_REGNO_P(N) \ | |
1536 ((N) == GP_ARG_RETURN \ | |
1537 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ | |
1538 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) | |
1539 | |
1540 /* 1 if N is a possible register number for function argument passing. | |
1541 On RS/6000, these are r3-r10 and fp1-fp13. | |
1542 On AltiVec, v2 - v13 are used for passing vectors. */ | |
1543 #define FUNCTION_ARG_REGNO_P(N) \ | |
1544 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ | |
1545 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ | |
1546 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ | |
1547 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ | |
1548 && TARGET_HARD_FLOAT && TARGET_FPRS)) | |
1549 | |
1550 /* Define a data type for recording info about an argument list | |
1551 during the scan of that argument list. This data type should | |
1552 hold all necessary information about the function itself | |
1553 and about the args processed so far, enough to enable macros | |
1554 such as FUNCTION_ARG to determine where the next arg should go. | |
1555 | |
1556 On the RS/6000, this is a structure. The first element is the number of | |
1557 total argument words, the second is used to store the next | |
1558 floating-point register number, and the third says how many more args we | |
1559 have prototype types for. | |
1560 | |
1561 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is | |
1562 the next available GP register, `fregno' is the next available FP | |
1563 register, and `words' is the number of words used on the stack. | |
1564 | |
1565 The varargs/stdarg support requires that this structure's size | |
1566 be a multiple of sizeof(int). */ | |
1567 | |
1568 typedef struct rs6000_args | |
1569 { | |
1570 int words; /* # words used for passing GP registers */ | |
1571 int fregno; /* next available FP register */ | |
1572 int vregno; /* next available AltiVec register */ | |
1573 int nargs_prototype; /* # args left in the current prototype */ | |
1574 int prototype; /* Whether a prototype was defined */ | |
1575 int stdarg; /* Whether function is a stdarg function. */ | |
1576 int call_cookie; /* Do special things for this call */ | |
1577 int sysv_gregno; /* next available GP register */ | |
1578 int intoffset; /* running offset in struct (darwin64) */ | |
1579 int use_stack; /* any part of struct on stack (darwin64) */ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1580 int floats_in_gpr; /* count of SFmode floats taking up |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1581 GPR space (darwin64) */ |
0 | 1582 int named; /* false for varargs params */ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1583 int escapes; /* if function visible outside tu */ |
0 | 1584 } CUMULATIVE_ARGS; |
1585 | |
1586 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1587 for a call to a function whose data type is FNTYPE. | |
1588 For a library call, FNTYPE is 0. */ | |
1589 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1590 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1591 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1592 N_NAMED_ARGS, FNDECL, VOIDmode) |
0 | 1593 |
1594 /* Similar, but when scanning the definition of a procedure. We always | |
1595 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1596 | |
1597 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1598 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1599 1000, current_function_decl, VOIDmode) |
0 | 1600 |
1601 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1602 | |
1603 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1604 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1605 0, NULL_TREE, MODE) |
0 | 1606 |
1607 /* If defined, a C expression which determines whether, and in which | |
1608 direction, to pad out an argument with extra space. The value | |
1609 should be of type `enum direction': either `upward' to pad above | |
1610 the argument, `downward' to pad below, or `none' to inhibit | |
1611 padding. */ | |
1612 | |
1613 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) | |
1614 | |
1615 #define PAD_VARARGS_DOWN \ | |
1616 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
1617 | |
1618 /* Output assembler code to FILE to increment profiler label # LABELNO | |
1619 for profiling a function entry. */ | |
1620 | |
1621 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1622 output_function_profiler ((FILE), (LABELNO)); | |
1623 | |
1624 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1625 the stack pointer does not matter. No definition is equivalent to | |
1626 always zero. | |
1627 | |
1628 On the RS/6000, this is nonzero because we can restore the stack from | |
1629 its backpointer, which we maintain. */ | |
1630 #define EXIT_IGNORE_STACK 1 | |
1631 | |
1632 /* Define this macro as a C expression that is nonzero for registers | |
1633 that are used by the epilogue or the return' pattern. The stack | |
1634 and frame pointer registers are already be assumed to be used as | |
1635 needed. */ | |
1636 | |
1637 #define EPILOGUE_USES(REGNO) \ | |
1638 ((reload_completed && (REGNO) == LR_REGNO) \ | |
1639 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1640 || (crtl->calls_eh_return \ |
0 | 1641 && TARGET_AIX \ |
1642 && (REGNO) == 2)) | |
1643 | |
1644 | |
1645 /* Length in units of the trampoline for entering a nested function. */ | |
1646 | |
1647 #define TRAMPOLINE_SIZE rs6000_trampoline_size () | |
1648 | |
1649 /* Definitions for __builtin_return_address and __builtin_frame_address. | |
1650 __builtin_return_address (0) should give link register (65), enable | |
1651 this. */ | |
1652 /* This should be uncommented, so that the link register is used, but | |
1653 currently this would result in unmatched insns and spilling fixed | |
1654 registers so we'll leave it for another day. When these problems are | |
1655 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1656 (mrs) */ | |
1657 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
1658 | |
1659 /* Number of bytes into the frame return addresses can be found. See | |
1660 rs6000_stack_info in rs6000.c for more information on how the different | |
1661 abi's store the return address. */ | |
1662 #define RETURN_ADDRESS_OFFSET \ | |
1663 ((DEFAULT_ABI == ABI_AIX \ | |
1664 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ | |
1665 (DEFAULT_ABI == ABI_V4) ? 4 : \ | |
1666 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) | |
1667 | |
1668 /* The current return address is in link register (65). The return address | |
1669 of anything farther back is accessed normally at an offset of 8 from the | |
1670 frame pointer. */ | |
1671 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
1672 (rs6000_return_addr (COUNT, FRAME)) | |
1673 | |
1674 | |
1675 /* Definitions for register eliminations. | |
1676 | |
1677 We have two registers that can be eliminated on the RS/6000. First, the | |
1678 frame pointer register can often be eliminated in favor of the stack | |
1679 pointer register. Secondly, the argument pointer register can always be | |
1680 eliminated; it is replaced with either the stack or frame pointer. | |
1681 | |
1682 In addition, we use the elimination mechanism to see if r30 is needed | |
1683 Initially we assume that it isn't. If it is, we spill it. This is done | |
1684 by making it an eliminable register. We replace it with itself so that | |
1685 if it isn't needed, then existing uses won't be modified. */ | |
1686 | |
1687 /* This is an array of structures. Each structure initializes one pair | |
1688 of eliminable registers. The "from" register number is given first, | |
1689 followed by "to". Eliminations of the same "from" register are listed | |
1690 in order of preference. */ | |
1691 #define ELIMINABLE_REGS \ | |
1692 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1693 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1694 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1695 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1696 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1697 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } | |
1698 | |
1699 /* Define the offset between two registers, one to be eliminated, and the other | |
1700 its replacement, at the start of a routine. */ | |
1701 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1702 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
1703 | |
1704 /* Addressing modes, and classification of registers for them. */ | |
1705 | |
1706 #define HAVE_PRE_DECREMENT 1 | |
1707 #define HAVE_PRE_INCREMENT 1 | |
1708 #define HAVE_PRE_MODIFY_DISP 1 | |
1709 #define HAVE_PRE_MODIFY_REG 1 | |
1710 | |
1711 /* Macros to check register numbers against specific register classes. */ | |
1712 | |
1713 /* These assume that REGNO is a hard or pseudo reg number. | |
1714 They give nonzero only if REGNO is a hard reg of the suitable class | |
1715 or a pseudo reg currently allocated to a suitable hard reg. | |
1716 Since they use reg_renumber, they are safe only once reg_renumber | |
1717 has been allocated, which happens in local-alloc.c. */ | |
1718 | |
1719 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1720 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1721 ? (REGNO) <= 31 || (REGNO) == 67 \ | |
1722 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1723 : (reg_renumber[REGNO] >= 0 \ | |
1724 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
1725 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
1726 | |
1727 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1728 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1729 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
1730 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1731 : (reg_renumber[REGNO] > 0 \ | |
1732 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
1733 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1734 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1735 /* Nonzero if X is a hard reg that can be used as an index |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1736 or if it is a pseudo reg in the non-strict case. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1737 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1738 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1739 || REGNO_OK_FOR_INDEX_P (REGNO (X))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1740 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1741 /* Nonzero if X is a hard reg that can be used as a base reg |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1742 or if it is a pseudo reg in the non-strict case. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1743 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1744 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1745 || REGNO_OK_FOR_BASE_P (REGNO (X))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1746 |
0 | 1747 |
1748 /* Maximum number of registers that can appear in a valid memory address. */ | |
1749 | |
1750 #define MAX_REGS_PER_ADDRESS 2 | |
1751 | |
1752 /* Recognize any constant value that is a valid address. */ | |
1753 | |
1754 #define CONSTANT_ADDRESS_P(X) \ | |
1755 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1756 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1757 || GET_CODE (X) == HIGH) | |
1758 | |
1759 /* Nonzero if the constant value X is a legitimate general operand. | |
1760 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1761 | |
1762 On the RS/6000, all integer constants are acceptable, most won't be valid | |
1763 for particular insns, though. Only easy FP constants are | |
1764 acceptable. */ | |
1765 | |
1766 #define LEGITIMATE_CONSTANT_P(X) \ | |
1767 (((GET_CODE (X) != CONST_DOUBLE \ | |
1768 && GET_CODE (X) != CONST_VECTOR) \ | |
1769 || GET_MODE (X) == VOIDmode \ | |
1770 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ | |
1771 || easy_fp_constant (X, GET_MODE (X)) \ | |
1772 || easy_vector_constant (X, GET_MODE (X))) \ | |
1773 && !rs6000_tls_referenced_p (X)) | |
1774 | |
1775 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) | |
1776 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ | |
1777 && EASY_VECTOR_15((n) >> 1) \ | |
1778 && ((n) & 1) == 0) | |
1779 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1780 #define EASY_VECTOR_MSB(n,mode) \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1781 (((unsigned HOST_WIDE_INT)n) == \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1782 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1783 |
0 | 1784 |
1785 /* Try a machine-dependent way of reloading an illegitimate address | |
1786 operand. If we find one, push the reload and jump to WIN. This | |
1787 macro is used in only one place: `find_reloads_address' in reload.c. | |
1788 | |
1789 Implemented on rs6000 by rs6000_legitimize_reload_address. | |
1790 Note that (X) is evaluated twice; this is safe in current usage. */ | |
1791 | |
1792 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1793 do { \ | |
1794 int win; \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1795 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
0 | 1796 (int)(TYPE), (IND_LEVELS), &win); \ |
1797 if ( win ) \ | |
1798 goto WIN; \ | |
1799 } while (0) | |
1800 | |
1801 #define FIND_BASE_TERM rs6000_find_base_term | |
1802 | |
1803 /* The register number of the register used to address a table of | |
1804 static data addresses in memory. In some cases this register is | |
1805 defined by a processor's "application binary interface" (ABI). | |
1806 When this macro is defined, RTL is generated for this register | |
1807 once, as with the stack pointer and frame pointer registers. If | |
1808 this macro is not defined, it is up to the machine-dependent files | |
1809 to allocate such a register (if necessary). */ | |
1810 | |
1811 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 | |
1812 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
1813 | |
1814 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) | |
1815 | |
1816 /* Define this macro if the register defined by | |
1817 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
1818 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ | |
1819 | |
1820 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1821 | |
1822 /* A C expression that is nonzero if X is a legitimate immediate | |
1823 operand on the target machine when generating position independent | |
1824 code. You can assume that X satisfies `CONSTANT_P', so you need | |
1825 not check this. You can also assume FLAG_PIC is true, so you need | |
1826 not check it either. You need not define this macro if all | |
1827 constants (including `SYMBOL_REF') can be immediate operands when | |
1828 generating position independent code. */ | |
1829 | |
1830 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
1831 | |
1832 /* Define this if some processing needs to be done immediately before | |
1833 emitting code for an insn. */ | |
1834 | |
1835 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ | |
1836 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) | |
1837 | |
1838 /* Specify the machine mode that this machine uses | |
1839 for the index in the tablejump instruction. */ | |
1840 #define CASE_VECTOR_MODE SImode | |
1841 | |
1842 /* Define as C expression which evaluates to nonzero if the tablejump | |
1843 instruction expects the table to contain offsets from the address of the | |
1844 table. | |
1845 Do not define this if the table should contain absolute addresses. */ | |
1846 #define CASE_VECTOR_PC_RELATIVE 1 | |
1847 | |
1848 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1849 #define DEFAULT_SIGNED_CHAR 0 | |
1850 | |
1851 /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1852 also convert validly to an unsigned one. */ | |
1853 | |
1854 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ | |
1855 | |
1856 /* An integer expression for the size in bits of the largest integer machine | |
1857 mode that should actually be used. */ | |
1858 | |
1859 /* Allow pairs of registers to be used, which is the intent of the default. */ | |
1860 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
1861 | |
1862 /* Max number of bytes we can move from memory to memory | |
1863 in one reasonably fast instruction. */ | |
1864 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) | |
1865 #define MAX_MOVE_MAX 8 | |
1866 | |
1867 /* Nonzero if access to memory by bytes is no faster than for words. | |
1868 Also nonzero if doing byte operations (specifically shifts) in registers | |
1869 is undesirable. */ | |
1870 #define SLOW_BYTE_ACCESS 1 | |
1871 | |
1872 /* Define if operations between registers always perform the operation | |
1873 on the full register even if a narrower mode is specified. */ | |
1874 #define WORD_REGISTER_OPERATIONS | |
1875 | |
1876 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1877 will either zero-extend or sign-extend. The value of this macro should | |
1878 be the code that says which one of the two operations is implicitly | |
1879 done, UNKNOWN if none. */ | |
1880 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1881 | |
1882 /* Define if loading short immediate values into registers sign extends. */ | |
1883 #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1884 | |
1885 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1886 is done just by pretending it is already truncated. */ | |
1887 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1888 | |
1889 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ | |
1890 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1891 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) | |
1892 | |
1893 /* The CTZ patterns return -1 for input of zero. */ | |
1894 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) | |
1895 | |
1896 /* Specify the machine mode that pointers have. | |
1897 After generation of rtl, the compiler makes no further distinction | |
1898 between pointers and any other objects of this machine mode. */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1899 extern unsigned rs6000_pmode; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1900 #define Pmode ((enum machine_mode)rs6000_pmode) |
0 | 1901 |
1902 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ | |
1903 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) | |
1904 | |
1905 /* Mode of a function address in a call instruction (for indexing purposes). | |
1906 Doesn't matter on RS/6000. */ | |
1907 #define FUNCTION_MODE SImode | |
1908 | |
1909 /* Define this if addresses of constant functions | |
1910 shouldn't be put through pseudo regs where they can be cse'd. | |
1911 Desirable on machines where ordinary constants are expensive | |
1912 but a CALL with constant address is cheap. */ | |
1913 #define NO_FUNCTION_CSE | |
1914 | |
1915 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
1916 few bits. | |
1917 | |
1918 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
1919 have been dropped from the PowerPC architecture. */ | |
1920 | |
1921 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) | |
1922 | |
1923 /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
1924 should be adjusted to reflect any required changes. This macro is used when | |
1925 there is some systematic length adjustment required that would be difficult | |
1926 to express in the length attribute. */ | |
1927 | |
1928 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
1929 | |
1930 /* Given a comparison code (EQ, NE, etc.) and the first operand of a | |
1931 COMPARE, return the mode to be used for the comparison. For | |
1932 floating-point, CCFPmode should be used. CCUNSmode should be used | |
1933 for unsigned comparisons. CCEQmode should be used when we are | |
1934 doing an inequality comparison on the result of a | |
1935 comparison. CCmode should be used in all other cases. */ | |
1936 | |
1937 #define SELECT_CC_MODE(OP,X,Y) \ | |
1938 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ | |
1939 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ | |
1940 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ | |
1941 ? CCEQmode : CCmode)) | |
1942 | |
1943 /* Can the condition code MODE be safely reversed? This is safe in | |
1944 all cases on this port, because at present it doesn't use the | |
1945 trapping FP comparisons (fcmpo). */ | |
1946 #define REVERSIBLE_CC_MODE(MODE) 1 | |
1947 | |
1948 /* Given a condition code and a mode, return the inverse condition. */ | |
1949 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
1950 | |
1951 | |
1952 /* Control the assembler format that we output. */ | |
1953 | |
1954 /* A C string constant describing how to begin a comment in the target | |
1955 assembler language. The compiler assumes that the comment will end at | |
1956 the end of the line. */ | |
1957 #define ASM_COMMENT_START " #" | |
1958 | |
1959 /* Flag to say the TOC is initialized */ | |
1960 extern int toc_initialized; | |
1961 | |
1962 /* Macro to output a special constant pool entry. Go to WIN if we output | |
1963 it. Otherwise, it is written the usual way. | |
1964 | |
1965 On the RS/6000, toc entries are handled this way. */ | |
1966 | |
1967 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ | |
1968 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
1969 { \ | |
1970 output_toc (FILE, X, LABELNO, MODE); \ | |
1971 goto WIN; \ | |
1972 } \ | |
1973 } | |
1974 | |
1975 #ifdef HAVE_GAS_WEAK | |
1976 #define RS6000_WEAK 1 | |
1977 #else | |
1978 #define RS6000_WEAK 0 | |
1979 #endif | |
1980 | |
1981 #if RS6000_WEAK | |
1982 /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
1983 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
1984 do \ | |
1985 { \ | |
1986 fputs ("\t.weak\t", (FILE)); \ | |
1987 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1988 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
1989 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
1990 { \ | |
1991 if (TARGET_XCOFF) \ | |
1992 fputs ("[DS]", (FILE)); \ | |
1993 fputs ("\n\t.weak\t.", (FILE)); \ | |
1994 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1995 } \ | |
1996 fputc ('\n', (FILE)); \ | |
1997 if (VAL) \ | |
1998 { \ | |
1999 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
2000 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2001 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2002 { \ | |
2003 fputs ("\t.set\t.", (FILE)); \ | |
2004 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2005 fputs (",.", (FILE)); \ | |
2006 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ | |
2007 fputc ('\n', (FILE)); \ | |
2008 } \ | |
2009 } \ | |
2010 } \ | |
2011 while (0) | |
2012 #endif | |
2013 | |
2014 #if HAVE_GAS_WEAKREF | |
2015 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2016 do \ | |
2017 { \ | |
2018 fputs ("\t.weakref\t", (FILE)); \ | |
2019 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2020 fputs (", ", (FILE)); \ | |
2021 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2022 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2023 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2024 { \ | |
2025 fputs ("\n\t.weakref\t.", (FILE)); \ | |
2026 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2027 fputs (", .", (FILE)); \ | |
2028 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2029 } \ | |
2030 fputc ('\n', (FILE)); \ | |
2031 } while (0) | |
2032 #endif | |
2033 | |
2034 /* This implements the `alias' attribute. */ | |
2035 #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2036 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2037 do \ | |
2038 { \ | |
2039 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2040 const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2041 if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
2042 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2043 { \ | |
2044 if (TREE_PUBLIC (DECL)) \ | |
2045 { \ | |
2046 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2047 { \ | |
2048 fputs ("\t.globl\t.", FILE); \ | |
2049 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2050 putc ('\n', FILE); \ | |
2051 } \ | |
2052 } \ | |
2053 else if (TARGET_XCOFF) \ | |
2054 { \ | |
2055 fputs ("\t.lglobl\t.", FILE); \ | |
2056 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2057 putc ('\n', FILE); \ | |
2058 } \ | |
2059 fputs ("\t.set\t.", FILE); \ | |
2060 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2061 fputs (",.", FILE); \ | |
2062 RS6000_OUTPUT_BASENAME (FILE, name); \ | |
2063 fputc ('\n', FILE); \ | |
2064 } \ | |
2065 ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2066 } \ | |
2067 while (0) | |
2068 | |
2069 #define TARGET_ASM_FILE_START rs6000_file_start | |
2070 | |
2071 /* Output to assembler file text saying following lines | |
2072 may contain character constants, extra white space, comments, etc. */ | |
2073 | |
2074 #define ASM_APP_ON "" | |
2075 | |
2076 /* Output to assembler file text saying following lines | |
2077 no longer contain unusual constructs. */ | |
2078 | |
2079 #define ASM_APP_OFF "" | |
2080 | |
2081 /* How to refer to registers in assembler output. | |
2082 This sequence is indexed by compiler's hard-register-number (see above). */ | |
2083 | |
2084 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ | |
2085 | |
2086 #define REGISTER_NAMES \ | |
2087 { \ | |
2088 &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2089 &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2090 &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2091 &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2092 &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2093 &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2094 &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2095 &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2096 &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2097 &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2098 &rs6000_reg_names[10][0], /* r10 */ \ | |
2099 &rs6000_reg_names[11][0], /* r11 */ \ | |
2100 &rs6000_reg_names[12][0], /* r12 */ \ | |
2101 &rs6000_reg_names[13][0], /* r13 */ \ | |
2102 &rs6000_reg_names[14][0], /* r14 */ \ | |
2103 &rs6000_reg_names[15][0], /* r15 */ \ | |
2104 &rs6000_reg_names[16][0], /* r16 */ \ | |
2105 &rs6000_reg_names[17][0], /* r17 */ \ | |
2106 &rs6000_reg_names[18][0], /* r18 */ \ | |
2107 &rs6000_reg_names[19][0], /* r19 */ \ | |
2108 &rs6000_reg_names[20][0], /* r20 */ \ | |
2109 &rs6000_reg_names[21][0], /* r21 */ \ | |
2110 &rs6000_reg_names[22][0], /* r22 */ \ | |
2111 &rs6000_reg_names[23][0], /* r23 */ \ | |
2112 &rs6000_reg_names[24][0], /* r24 */ \ | |
2113 &rs6000_reg_names[25][0], /* r25 */ \ | |
2114 &rs6000_reg_names[26][0], /* r26 */ \ | |
2115 &rs6000_reg_names[27][0], /* r27 */ \ | |
2116 &rs6000_reg_names[28][0], /* r28 */ \ | |
2117 &rs6000_reg_names[29][0], /* r29 */ \ | |
2118 &rs6000_reg_names[30][0], /* r30 */ \ | |
2119 &rs6000_reg_names[31][0], /* r31 */ \ | |
2120 \ | |
2121 &rs6000_reg_names[32][0], /* fr0 */ \ | |
2122 &rs6000_reg_names[33][0], /* fr1 */ \ | |
2123 &rs6000_reg_names[34][0], /* fr2 */ \ | |
2124 &rs6000_reg_names[35][0], /* fr3 */ \ | |
2125 &rs6000_reg_names[36][0], /* fr4 */ \ | |
2126 &rs6000_reg_names[37][0], /* fr5 */ \ | |
2127 &rs6000_reg_names[38][0], /* fr6 */ \ | |
2128 &rs6000_reg_names[39][0], /* fr7 */ \ | |
2129 &rs6000_reg_names[40][0], /* fr8 */ \ | |
2130 &rs6000_reg_names[41][0], /* fr9 */ \ | |
2131 &rs6000_reg_names[42][0], /* fr10 */ \ | |
2132 &rs6000_reg_names[43][0], /* fr11 */ \ | |
2133 &rs6000_reg_names[44][0], /* fr12 */ \ | |
2134 &rs6000_reg_names[45][0], /* fr13 */ \ | |
2135 &rs6000_reg_names[46][0], /* fr14 */ \ | |
2136 &rs6000_reg_names[47][0], /* fr15 */ \ | |
2137 &rs6000_reg_names[48][0], /* fr16 */ \ | |
2138 &rs6000_reg_names[49][0], /* fr17 */ \ | |
2139 &rs6000_reg_names[50][0], /* fr18 */ \ | |
2140 &rs6000_reg_names[51][0], /* fr19 */ \ | |
2141 &rs6000_reg_names[52][0], /* fr20 */ \ | |
2142 &rs6000_reg_names[53][0], /* fr21 */ \ | |
2143 &rs6000_reg_names[54][0], /* fr22 */ \ | |
2144 &rs6000_reg_names[55][0], /* fr23 */ \ | |
2145 &rs6000_reg_names[56][0], /* fr24 */ \ | |
2146 &rs6000_reg_names[57][0], /* fr25 */ \ | |
2147 &rs6000_reg_names[58][0], /* fr26 */ \ | |
2148 &rs6000_reg_names[59][0], /* fr27 */ \ | |
2149 &rs6000_reg_names[60][0], /* fr28 */ \ | |
2150 &rs6000_reg_names[61][0], /* fr29 */ \ | |
2151 &rs6000_reg_names[62][0], /* fr30 */ \ | |
2152 &rs6000_reg_names[63][0], /* fr31 */ \ | |
2153 \ | |
2154 &rs6000_reg_names[64][0], /* mq */ \ | |
2155 &rs6000_reg_names[65][0], /* lr */ \ | |
2156 &rs6000_reg_names[66][0], /* ctr */ \ | |
2157 &rs6000_reg_names[67][0], /* ap */ \ | |
2158 \ | |
2159 &rs6000_reg_names[68][0], /* cr0 */ \ | |
2160 &rs6000_reg_names[69][0], /* cr1 */ \ | |
2161 &rs6000_reg_names[70][0], /* cr2 */ \ | |
2162 &rs6000_reg_names[71][0], /* cr3 */ \ | |
2163 &rs6000_reg_names[72][0], /* cr4 */ \ | |
2164 &rs6000_reg_names[73][0], /* cr5 */ \ | |
2165 &rs6000_reg_names[74][0], /* cr6 */ \ | |
2166 &rs6000_reg_names[75][0], /* cr7 */ \ | |
2167 \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2168 &rs6000_reg_names[76][0], /* ca */ \ |
0 | 2169 \ |
2170 &rs6000_reg_names[77][0], /* v0 */ \ | |
2171 &rs6000_reg_names[78][0], /* v1 */ \ | |
2172 &rs6000_reg_names[79][0], /* v2 */ \ | |
2173 &rs6000_reg_names[80][0], /* v3 */ \ | |
2174 &rs6000_reg_names[81][0], /* v4 */ \ | |
2175 &rs6000_reg_names[82][0], /* v5 */ \ | |
2176 &rs6000_reg_names[83][0], /* v6 */ \ | |
2177 &rs6000_reg_names[84][0], /* v7 */ \ | |
2178 &rs6000_reg_names[85][0], /* v8 */ \ | |
2179 &rs6000_reg_names[86][0], /* v9 */ \ | |
2180 &rs6000_reg_names[87][0], /* v10 */ \ | |
2181 &rs6000_reg_names[88][0], /* v11 */ \ | |
2182 &rs6000_reg_names[89][0], /* v12 */ \ | |
2183 &rs6000_reg_names[90][0], /* v13 */ \ | |
2184 &rs6000_reg_names[91][0], /* v14 */ \ | |
2185 &rs6000_reg_names[92][0], /* v15 */ \ | |
2186 &rs6000_reg_names[93][0], /* v16 */ \ | |
2187 &rs6000_reg_names[94][0], /* v17 */ \ | |
2188 &rs6000_reg_names[95][0], /* v18 */ \ | |
2189 &rs6000_reg_names[96][0], /* v19 */ \ | |
2190 &rs6000_reg_names[97][0], /* v20 */ \ | |
2191 &rs6000_reg_names[98][0], /* v21 */ \ | |
2192 &rs6000_reg_names[99][0], /* v22 */ \ | |
2193 &rs6000_reg_names[100][0], /* v23 */ \ | |
2194 &rs6000_reg_names[101][0], /* v24 */ \ | |
2195 &rs6000_reg_names[102][0], /* v25 */ \ | |
2196 &rs6000_reg_names[103][0], /* v26 */ \ | |
2197 &rs6000_reg_names[104][0], /* v27 */ \ | |
2198 &rs6000_reg_names[105][0], /* v28 */ \ | |
2199 &rs6000_reg_names[106][0], /* v29 */ \ | |
2200 &rs6000_reg_names[107][0], /* v30 */ \ | |
2201 &rs6000_reg_names[108][0], /* v31 */ \ | |
2202 &rs6000_reg_names[109][0], /* vrsave */ \ | |
2203 &rs6000_reg_names[110][0], /* vscr */ \ | |
2204 &rs6000_reg_names[111][0], /* spe_acc */ \ | |
2205 &rs6000_reg_names[112][0], /* spefscr */ \ | |
2206 &rs6000_reg_names[113][0], /* sfp */ \ | |
2207 } | |
2208 | |
2209 /* Table of additional register names to use in user input. */ | |
2210 | |
2211 #define ADDITIONAL_REGISTER_NAMES \ | |
2212 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ | |
2213 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2214 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2215 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2216 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2217 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2218 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2219 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2220 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2221 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2222 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2223 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2224 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2225 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2226 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2227 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
2228 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ | |
2229 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2230 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2231 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2232 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2233 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2234 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2235 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
2236 {"vrsave", 109}, {"vscr", 110}, \ | |
2237 {"spe_acc", 111}, {"spefscr", 112}, \ | |
2238 /* no additional names for: mq, lr, ctr, ap */ \ | |
2239 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ | |
2240 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2241 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2242 /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2243 {"xer", 76}, \ |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2244 /* VSX registers overlaid on top of FR, Altivec registers */ \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2245 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2246 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2247 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2248 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2249 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2250 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2251 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2252 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2253 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2254 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2255 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2256 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2257 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2258 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2259 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2260 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } |
0 | 2261 |
2262 /* Text to write out after a CALL that may be replaced by glue code by | |
2263 the loader. This depends on the AIX version. */ | |
2264 #define RS6000_CALL_GLUE "cror 31,31,31" | |
2265 | |
2266 /* This is how to output an element of a case-vector that is relative. */ | |
2267 | |
2268 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
2269 do { char buf[100]; \ | |
2270 fputs ("\t.long ", FILE); \ | |
2271 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ | |
2272 assemble_name (FILE, buf); \ | |
2273 putc ('-', FILE); \ | |
2274 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ | |
2275 assemble_name (FILE, buf); \ | |
2276 putc ('\n', FILE); \ | |
2277 } while (0) | |
2278 | |
2279 /* This is how to output an assembler line | |
2280 that says to advance the location counter | |
2281 to a multiple of 2**LOG bytes. */ | |
2282 | |
2283 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2284 if ((LOG) != 0) \ | |
2285 fprintf (FILE, "\t.align %d\n", (LOG)) | |
2286 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2287 /* How to align the given loop. */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2288 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2289 |
0 | 2290 /* Pick up the return address upon entry to a procedure. Used for |
2291 dwarf2 unwind information. This also enables the table driven | |
2292 mechanism. */ | |
2293 | |
2294 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) | |
2295 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
2296 | |
2297 /* Describe how we implement __builtin_eh_return. */ | |
2298 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2299 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2300 | |
2301 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2302 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2303 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2304 | |
2305 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2306 | |
2307 /* Define which CODE values are valid. */ | |
2308 | |
2309 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
2310 ((CODE) == '.' || (CODE) == '&') | |
2311 | |
2312 /* Print a memory address as an operand to reference that memory location. */ | |
2313 | |
2314 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2315 | |
2316 /* uncomment for disabling the corresponding default options */ | |
2317 /* #define MACHINE_no_sched_interblock */ | |
2318 /* #define MACHINE_no_sched_speculative */ | |
2319 /* #define MACHINE_no_sched_speculative_load */ | |
2320 | |
2321 /* General flags. */ | |
2322 extern int frame_pointer_needed; | |
2323 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2324 /* Classification of the builtin functions to properly set the declaration tree |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2325 flags. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2326 enum rs6000_btc |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2327 { |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2328 RS6000_BTC_MISC, /* assume builtin can do anything */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2329 RS6000_BTC_CONST, /* builtin is a 'const' function. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2330 RS6000_BTC_PURE, /* builtin is a 'pure' function. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2331 RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2332 }; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2333 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2334 /* Convenience macros to document the instruction type. */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2335 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2336 #define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2337 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2338 #undef RS6000_BUILTIN |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2339 #undef RS6000_BUILTIN_EQUATE |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2340 #define RS6000_BUILTIN(NAME, TYPE) NAME, |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2341 #define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE, |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2342 |
0 | 2343 enum rs6000_builtins |
2344 { | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2345 #include "rs6000-builtin.def" |
0 | 2346 |
2347 RS6000_BUILTIN_COUNT | |
2348 }; | |
2349 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2350 #undef RS6000_BUILTIN |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2351 #undef RS6000_BUILTIN_EQUATE |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2352 |
0 | 2353 enum rs6000_builtin_type_index |
2354 { | |
2355 RS6000_BTI_NOT_OPAQUE, | |
2356 RS6000_BTI_opaque_V2SI, | |
2357 RS6000_BTI_opaque_V2SF, | |
2358 RS6000_BTI_opaque_p_V2SI, | |
2359 RS6000_BTI_opaque_V4SI, | |
2360 RS6000_BTI_V16QI, | |
2361 RS6000_BTI_V2SI, | |
2362 RS6000_BTI_V2SF, | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2363 RS6000_BTI_V2DI, |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2364 RS6000_BTI_V2DF, |
0 | 2365 RS6000_BTI_V4HI, |
2366 RS6000_BTI_V4SI, | |
2367 RS6000_BTI_V4SF, | |
2368 RS6000_BTI_V8HI, | |
2369 RS6000_BTI_unsigned_V16QI, | |
2370 RS6000_BTI_unsigned_V8HI, | |
2371 RS6000_BTI_unsigned_V4SI, | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2372 RS6000_BTI_unsigned_V2DI, |
0 | 2373 RS6000_BTI_bool_char, /* __bool char */ |
2374 RS6000_BTI_bool_short, /* __bool short */ | |
2375 RS6000_BTI_bool_int, /* __bool int */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2376 RS6000_BTI_bool_long, /* __bool long */ |
0 | 2377 RS6000_BTI_pixel, /* __pixel */ |
2378 RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2379 RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2380 RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2381 RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
0 | 2382 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2383 RS6000_BTI_long, /* long_integer_type_node */ | |
2384 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2385 RS6000_BTI_long_long, /* long_long_integer_type_node */ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2386 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ |
0 | 2387 RS6000_BTI_INTQI, /* intQI_type_node */ |
2388 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2389 RS6000_BTI_INTHI, /* intHI_type_node */ | |
2390 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2391 RS6000_BTI_INTSI, /* intSI_type_node */ | |
2392 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2393 RS6000_BTI_INTDI, /* intDI_type_node */ |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2394 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ |
0 | 2395 RS6000_BTI_float, /* float_type_node */ |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2396 RS6000_BTI_double, /* double_type_node */ |
0 | 2397 RS6000_BTI_void, /* void_type_node */ |
2398 RS6000_BTI_MAX | |
2399 }; | |
2400 | |
2401 | |
2402 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2403 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2404 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2405 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2406 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2407 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2408 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) |
0 | 2409 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2410 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2411 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2412 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2413 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2414 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2415 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
2416 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) | |
2417 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2418 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
0 | 2419 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2420 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2421 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2422 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
0 | 2423 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2424 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2425 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2426 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2427 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
0 | 2428 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2429 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2430 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2431 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) |
0 | 2432 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2433 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2434 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2435 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2436 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2437 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2438 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2439 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2440 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2441 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) |
0 | 2442 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2443 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
0 | 2444 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
2445 | |
2446 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2447 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2448 |