Mercurial > hg > CbC > CbC_gcc
annotate gcc/lower-subreg.c @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Decompose multiword subregs. |
|
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parents:
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changeset
|
2 Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
| 0 | 3 Contributed by Richard Henderson <rth@redhat.com> |
| 4 Ian Lance Taylor <iant@google.com> | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "machmode.h" | |
| 26 #include "tm.h" | |
| 27 #include "rtl.h" | |
| 28 #include "tm_p.h" | |
| 29 #include "timevar.h" | |
| 30 #include "flags.h" | |
| 31 #include "insn-config.h" | |
| 32 #include "obstack.h" | |
| 33 #include "basic-block.h" | |
| 34 #include "recog.h" | |
| 35 #include "bitmap.h" | |
|
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36 #include "dce.h" |
| 0 | 37 #include "expr.h" |
| 38 #include "except.h" | |
| 39 #include "regs.h" | |
| 40 #include "tree-pass.h" | |
| 41 #include "df.h" | |
| 42 | |
| 43 #ifdef STACK_GROWS_DOWNWARD | |
| 44 # undef STACK_GROWS_DOWNWARD | |
| 45 # define STACK_GROWS_DOWNWARD 1 | |
| 46 #else | |
| 47 # define STACK_GROWS_DOWNWARD 0 | |
| 48 #endif | |
| 49 | |
| 50 DEF_VEC_P (bitmap); | |
| 51 DEF_VEC_ALLOC_P (bitmap,heap); | |
| 52 | |
| 53 /* Decompose multi-word pseudo-registers into individual | |
| 54 pseudo-registers when possible. This is possible when all the uses | |
| 55 of a multi-word register are via SUBREG, or are copies of the | |
| 56 register to another location. Breaking apart the register permits | |
| 57 more CSE and permits better register allocation. */ | |
| 58 | |
| 59 /* Bit N in this bitmap is set if regno N is used in a context in | |
| 60 which we can decompose it. */ | |
| 61 static bitmap decomposable_context; | |
| 62 | |
| 63 /* Bit N in this bitmap is set if regno N is used in a context in | |
| 64 which it can not be decomposed. */ | |
| 65 static bitmap non_decomposable_context; | |
| 66 | |
|
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67 /* Bit N in this bitmap is set if regno N is used in a subreg |
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68 which changes the mode but not the size. This typically happens |
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69 when the register accessed as a floating-point value; we want to |
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70 avoid generating accesses to its subwords in integer modes. */ |
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71 static bitmap subreg_context; |
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72 |
| 0 | 73 /* Bit N in the bitmap in element M of this array is set if there is a |
| 74 copy from reg M to reg N. */ | |
| 75 static VEC(bitmap,heap) *reg_copy_graph; | |
| 76 | |
| 77 /* Return whether X is a simple object which we can take a word_mode | |
| 78 subreg of. */ | |
| 79 | |
| 80 static bool | |
| 81 simple_move_operand (rtx x) | |
| 82 { | |
| 83 if (GET_CODE (x) == SUBREG) | |
| 84 x = SUBREG_REG (x); | |
| 85 | |
| 86 if (!OBJECT_P (x)) | |
| 87 return false; | |
| 88 | |
| 89 if (GET_CODE (x) == LABEL_REF | |
| 90 || GET_CODE (x) == SYMBOL_REF | |
| 91 || GET_CODE (x) == HIGH | |
| 92 || GET_CODE (x) == CONST) | |
| 93 return false; | |
| 94 | |
| 95 if (MEM_P (x) | |
| 96 && (MEM_VOLATILE_P (x) | |
| 97 || mode_dependent_address_p (XEXP (x, 0)))) | |
| 98 return false; | |
| 99 | |
| 100 return true; | |
| 101 } | |
| 102 | |
| 103 /* If INSN is a single set between two objects, return the single set. | |
| 104 Such an insn can always be decomposed. INSN should have been | |
| 105 passed to recog and extract_insn before this is called. */ | |
| 106 | |
| 107 static rtx | |
| 108 simple_move (rtx insn) | |
| 109 { | |
| 110 rtx x; | |
| 111 rtx set; | |
| 112 enum machine_mode mode; | |
| 113 | |
| 114 if (recog_data.n_operands != 2) | |
| 115 return NULL_RTX; | |
| 116 | |
| 117 set = single_set (insn); | |
| 118 if (!set) | |
| 119 return NULL_RTX; | |
| 120 | |
| 121 x = SET_DEST (set); | |
| 122 if (x != recog_data.operand[0] && x != recog_data.operand[1]) | |
| 123 return NULL_RTX; | |
| 124 if (!simple_move_operand (x)) | |
| 125 return NULL_RTX; | |
| 126 | |
| 127 x = SET_SRC (set); | |
| 128 if (x != recog_data.operand[0] && x != recog_data.operand[1]) | |
| 129 return NULL_RTX; | |
| 130 /* For the src we can handle ASM_OPERANDS, and it is beneficial for | |
| 131 things like x86 rdtsc which returns a DImode value. */ | |
| 132 if (GET_CODE (x) != ASM_OPERANDS | |
| 133 && !simple_move_operand (x)) | |
| 134 return NULL_RTX; | |
| 135 | |
| 136 /* We try to decompose in integer modes, to avoid generating | |
| 137 inefficient code copying between integer and floating point | |
| 138 registers. That means that we can't decompose if this is a | |
| 139 non-integer mode for which there is no integer mode of the same | |
| 140 size. */ | |
| 141 mode = GET_MODE (SET_SRC (set)); | |
| 142 if (!SCALAR_INT_MODE_P (mode) | |
| 143 && (mode_for_size (GET_MODE_SIZE (mode) * BITS_PER_UNIT, MODE_INT, 0) | |
| 144 == BLKmode)) | |
| 145 return NULL_RTX; | |
| 146 | |
| 147 /* Reject PARTIAL_INT modes. They are used for processor specific | |
| 148 purposes and it's probably best not to tamper with them. */ | |
| 149 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
| 150 return NULL_RTX; | |
| 151 | |
| 152 return set; | |
| 153 } | |
| 154 | |
| 155 /* If SET is a copy from one multi-word pseudo-register to another, | |
| 156 record that in reg_copy_graph. Return whether it is such a | |
| 157 copy. */ | |
| 158 | |
| 159 static bool | |
| 160 find_pseudo_copy (rtx set) | |
| 161 { | |
| 162 rtx dest = SET_DEST (set); | |
| 163 rtx src = SET_SRC (set); | |
| 164 unsigned int rd, rs; | |
| 165 bitmap b; | |
| 166 | |
| 167 if (!REG_P (dest) || !REG_P (src)) | |
| 168 return false; | |
| 169 | |
| 170 rd = REGNO (dest); | |
| 171 rs = REGNO (src); | |
| 172 if (HARD_REGISTER_NUM_P (rd) || HARD_REGISTER_NUM_P (rs)) | |
| 173 return false; | |
| 174 | |
| 175 if (GET_MODE_SIZE (GET_MODE (dest)) <= UNITS_PER_WORD) | |
| 176 return false; | |
| 177 | |
| 178 b = VEC_index (bitmap, reg_copy_graph, rs); | |
| 179 if (b == NULL) | |
| 180 { | |
| 181 b = BITMAP_ALLOC (NULL); | |
| 182 VEC_replace (bitmap, reg_copy_graph, rs, b); | |
| 183 } | |
| 184 | |
| 185 bitmap_set_bit (b, rd); | |
| 186 | |
| 187 return true; | |
| 188 } | |
| 189 | |
| 190 /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case | |
| 191 where they are copied to another register, add the register to | |
| 192 which they are copied to DECOMPOSABLE_CONTEXT. Use | |
| 193 NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track | |
| 194 copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */ | |
| 195 | |
| 196 static void | |
| 197 propagate_pseudo_copies (void) | |
| 198 { | |
| 199 bitmap queue, propagate; | |
| 200 | |
| 201 queue = BITMAP_ALLOC (NULL); | |
| 202 propagate = BITMAP_ALLOC (NULL); | |
| 203 | |
| 204 bitmap_copy (queue, decomposable_context); | |
| 205 do | |
| 206 { | |
| 207 bitmap_iterator iter; | |
| 208 unsigned int i; | |
| 209 | |
| 210 bitmap_clear (propagate); | |
| 211 | |
| 212 EXECUTE_IF_SET_IN_BITMAP (queue, 0, i, iter) | |
| 213 { | |
| 214 bitmap b = VEC_index (bitmap, reg_copy_graph, i); | |
| 215 if (b) | |
| 216 bitmap_ior_and_compl_into (propagate, b, non_decomposable_context); | |
| 217 } | |
| 218 | |
| 219 bitmap_and_compl (queue, propagate, decomposable_context); | |
| 220 bitmap_ior_into (decomposable_context, propagate); | |
| 221 } | |
| 222 while (!bitmap_empty_p (queue)); | |
| 223 | |
| 224 BITMAP_FREE (queue); | |
| 225 BITMAP_FREE (propagate); | |
| 226 } | |
| 227 | |
| 228 /* A pointer to one of these values is passed to | |
| 229 find_decomposable_subregs via for_each_rtx. */ | |
| 230 | |
| 231 enum classify_move_insn | |
| 232 { | |
| 233 /* Not a simple move from one location to another. */ | |
| 234 NOT_SIMPLE_MOVE, | |
| 235 /* A simple move from one pseudo-register to another. */ | |
| 236 SIMPLE_PSEUDO_REG_MOVE, | |
| 237 /* A simple move involving a non-pseudo-register. */ | |
| 238 SIMPLE_MOVE | |
| 239 }; | |
| 240 | |
| 241 /* This is called via for_each_rtx. If we find a SUBREG which we | |
| 242 could use to decompose a pseudo-register, set a bit in | |
| 243 DECOMPOSABLE_CONTEXT. If we find an unadorned register which is | |
| 244 not a simple pseudo-register copy, DATA will point at the type of | |
| 245 move, and we set a bit in DECOMPOSABLE_CONTEXT or | |
| 246 NON_DECOMPOSABLE_CONTEXT as appropriate. */ | |
| 247 | |
| 248 static int | |
| 249 find_decomposable_subregs (rtx *px, void *data) | |
| 250 { | |
| 251 enum classify_move_insn *pcmi = (enum classify_move_insn *) data; | |
| 252 rtx x = *px; | |
| 253 | |
| 254 if (x == NULL_RTX) | |
| 255 return 0; | |
| 256 | |
| 257 if (GET_CODE (x) == SUBREG) | |
| 258 { | |
| 259 rtx inner = SUBREG_REG (x); | |
| 260 unsigned int regno, outer_size, inner_size, outer_words, inner_words; | |
| 261 | |
| 262 if (!REG_P (inner)) | |
| 263 return 0; | |
| 264 | |
| 265 regno = REGNO (inner); | |
| 266 if (HARD_REGISTER_NUM_P (regno)) | |
| 267 return -1; | |
| 268 | |
| 269 outer_size = GET_MODE_SIZE (GET_MODE (x)); | |
| 270 inner_size = GET_MODE_SIZE (GET_MODE (inner)); | |
| 271 outer_words = (outer_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 272 inner_words = (inner_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 273 | |
| 274 /* We only try to decompose single word subregs of multi-word | |
| 275 registers. When we find one, we return -1 to avoid iterating | |
| 276 over the inner register. | |
| 277 | |
| 278 ??? This doesn't allow, e.g., DImode subregs of TImode values | |
| 279 on 32-bit targets. We would need to record the way the | |
| 280 pseudo-register was used, and only decompose if all the uses | |
| 281 were the same number and size of pieces. Hopefully this | |
| 282 doesn't happen much. */ | |
| 283 | |
| 284 if (outer_words == 1 && inner_words > 1) | |
| 285 { | |
| 286 bitmap_set_bit (decomposable_context, regno); | |
| 287 return -1; | |
| 288 } | |
| 289 | |
| 290 /* If this is a cast from one mode to another, where the modes | |
| 291 have the same size, and they are not tieable, then mark this | |
| 292 register as non-decomposable. If we decompose it we are | |
| 293 likely to mess up whatever the backend is trying to do. */ | |
| 294 if (outer_words > 1 | |
| 295 && outer_size == inner_size | |
| 296 && !MODES_TIEABLE_P (GET_MODE (x), GET_MODE (inner))) | |
| 297 { | |
| 298 bitmap_set_bit (non_decomposable_context, regno); | |
|
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parents:
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299 bitmap_set_bit (subreg_context, regno); |
| 0 | 300 return -1; |
| 301 } | |
| 302 } | |
| 303 else if (REG_P (x)) | |
| 304 { | |
| 305 unsigned int regno; | |
| 306 | |
| 307 /* We will see an outer SUBREG before we see the inner REG, so | |
| 308 when we see a plain REG here it means a direct reference to | |
| 309 the register. | |
| 310 | |
| 311 If this is not a simple copy from one location to another, | |
| 312 then we can not decompose this register. If this is a simple | |
| 313 copy from one pseudo-register to another, and the mode is right | |
| 314 then we mark the register as decomposable. | |
| 315 Otherwise we don't say anything about this register -- | |
| 316 it could be decomposed, but whether that would be | |
| 317 profitable depends upon how it is used elsewhere. | |
| 318 | |
| 319 We only set bits in the bitmap for multi-word | |
| 320 pseudo-registers, since those are the only ones we care about | |
| 321 and it keeps the size of the bitmaps down. */ | |
| 322 | |
| 323 regno = REGNO (x); | |
| 324 if (!HARD_REGISTER_NUM_P (regno) | |
| 325 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
| 326 { | |
| 327 switch (*pcmi) | |
| 328 { | |
| 329 case NOT_SIMPLE_MOVE: | |
| 330 bitmap_set_bit (non_decomposable_context, regno); | |
| 331 break; | |
| 332 case SIMPLE_PSEUDO_REG_MOVE: | |
| 333 if (MODES_TIEABLE_P (GET_MODE (x), word_mode)) | |
| 334 bitmap_set_bit (decomposable_context, regno); | |
| 335 break; | |
| 336 case SIMPLE_MOVE: | |
| 337 break; | |
| 338 default: | |
| 339 gcc_unreachable (); | |
| 340 } | |
| 341 } | |
| 342 } | |
| 343 else if (MEM_P (x)) | |
| 344 { | |
| 345 enum classify_move_insn cmi_mem = NOT_SIMPLE_MOVE; | |
| 346 | |
| 347 /* Any registers used in a MEM do not participate in a | |
| 348 SIMPLE_MOVE or SIMPLE_PSEUDO_REG_MOVE. Do our own recursion | |
| 349 here, and return -1 to block the parent's recursion. */ | |
| 350 for_each_rtx (&XEXP (x, 0), find_decomposable_subregs, &cmi_mem); | |
| 351 return -1; | |
| 352 } | |
| 353 | |
| 354 return 0; | |
| 355 } | |
| 356 | |
| 357 /* Decompose REGNO into word-sized components. We smash the REG node | |
| 358 in place. This ensures that (1) something goes wrong quickly if we | |
| 359 fail to make some replacement, and (2) the debug information inside | |
| 360 the symbol table is automatically kept up to date. */ | |
| 361 | |
| 362 static void | |
| 363 decompose_register (unsigned int regno) | |
| 364 { | |
| 365 rtx reg; | |
| 366 unsigned int words, i; | |
| 367 rtvec v; | |
| 368 | |
| 369 reg = regno_reg_rtx[regno]; | |
| 370 | |
| 371 regno_reg_rtx[regno] = NULL_RTX; | |
| 372 | |
| 373 words = GET_MODE_SIZE (GET_MODE (reg)); | |
| 374 words = (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 375 | |
| 376 v = rtvec_alloc (words); | |
| 377 for (i = 0; i < words; ++i) | |
| 378 RTVEC_ELT (v, i) = gen_reg_rtx_offset (reg, word_mode, i * UNITS_PER_WORD); | |
| 379 | |
| 380 PUT_CODE (reg, CONCATN); | |
| 381 XVEC (reg, 0) = v; | |
| 382 | |
| 383 if (dump_file) | |
| 384 { | |
| 385 fprintf (dump_file, "; Splitting reg %u ->", regno); | |
| 386 for (i = 0; i < words; ++i) | |
| 387 fprintf (dump_file, " %u", REGNO (XVECEXP (reg, 0, i))); | |
| 388 fputc ('\n', dump_file); | |
| 389 } | |
| 390 } | |
| 391 | |
| 392 /* Get a SUBREG of a CONCATN. */ | |
| 393 | |
| 394 static rtx | |
| 395 simplify_subreg_concatn (enum machine_mode outermode, rtx op, | |
| 396 unsigned int byte) | |
| 397 { | |
| 398 unsigned int inner_size; | |
|
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399 enum machine_mode innermode, partmode; |
| 0 | 400 rtx part; |
| 401 unsigned int final_offset; | |
| 402 | |
| 403 gcc_assert (GET_CODE (op) == CONCATN); | |
| 404 gcc_assert (byte % GET_MODE_SIZE (outermode) == 0); | |
| 405 | |
| 406 innermode = GET_MODE (op); | |
| 407 gcc_assert (byte < GET_MODE_SIZE (innermode)); | |
| 408 gcc_assert (GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (innermode)); | |
| 409 | |
| 410 inner_size = GET_MODE_SIZE (innermode) / XVECLEN (op, 0); | |
| 411 part = XVECEXP (op, 0, byte / inner_size); | |
|
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412 partmode = GET_MODE (part); |
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413 |
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414 /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of |
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415 regular CONST_VECTORs. They have vector or integer modes, depending |
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416 on the capabilities of the target. Cope with them. */ |
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417 if (partmode == VOIDmode && VECTOR_MODE_P (innermode)) |
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418 partmode = GET_MODE_INNER (innermode); |
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419 else if (partmode == VOIDmode) |
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420 { |
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421 enum mode_class mclass = GET_MODE_CLASS (innermode); |
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422 partmode = mode_for_size (inner_size * BITS_PER_UNIT, mclass, 0); |
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423 } |
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424 |
| 0 | 425 final_offset = byte % inner_size; |
| 426 if (final_offset + GET_MODE_SIZE (outermode) > inner_size) | |
| 427 return NULL_RTX; | |
| 428 | |
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429 return simplify_gen_subreg (outermode, part, partmode, final_offset); |
| 0 | 430 } |
| 431 | |
| 432 /* Wrapper around simplify_gen_subreg which handles CONCATN. */ | |
| 433 | |
| 434 static rtx | |
| 435 simplify_gen_subreg_concatn (enum machine_mode outermode, rtx op, | |
| 436 enum machine_mode innermode, unsigned int byte) | |
| 437 { | |
| 438 rtx ret; | |
| 439 | |
| 440 /* We have to handle generating a SUBREG of a SUBREG of a CONCATN. | |
| 441 If OP is a SUBREG of a CONCATN, then it must be a simple mode | |
| 442 change with the same size and offset 0, or it must extract a | |
| 443 part. We shouldn't see anything else here. */ | |
| 444 if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN) | |
| 445 { | |
| 446 rtx op2; | |
| 447 | |
| 448 if ((GET_MODE_SIZE (GET_MODE (op)) | |
| 449 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))) | |
| 450 && SUBREG_BYTE (op) == 0) | |
| 451 return simplify_gen_subreg_concatn (outermode, SUBREG_REG (op), | |
| 452 GET_MODE (SUBREG_REG (op)), byte); | |
| 453 | |
| 454 op2 = simplify_subreg_concatn (GET_MODE (op), SUBREG_REG (op), | |
| 455 SUBREG_BYTE (op)); | |
| 456 if (op2 == NULL_RTX) | |
| 457 { | |
| 458 /* We don't handle paradoxical subregs here. */ | |
| 459 gcc_assert (GET_MODE_SIZE (outermode) | |
| 460 <= GET_MODE_SIZE (GET_MODE (op))); | |
| 461 gcc_assert (GET_MODE_SIZE (GET_MODE (op)) | |
| 462 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))); | |
| 463 op2 = simplify_subreg_concatn (outermode, SUBREG_REG (op), | |
| 464 byte + SUBREG_BYTE (op)); | |
| 465 gcc_assert (op2 != NULL_RTX); | |
| 466 return op2; | |
| 467 } | |
| 468 | |
| 469 op = op2; | |
| 470 gcc_assert (op != NULL_RTX); | |
| 471 gcc_assert (innermode == GET_MODE (op)); | |
| 472 } | |
| 473 | |
| 474 if (GET_CODE (op) == CONCATN) | |
| 475 return simplify_subreg_concatn (outermode, op, byte); | |
| 476 | |
| 477 ret = simplify_gen_subreg (outermode, op, innermode, byte); | |
| 478 | |
| 479 /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then | |
| 480 resolve_simple_move will ask for the high part of the paradoxical | |
| 481 subreg, which does not have a value. Just return a zero. */ | |
| 482 if (ret == NULL_RTX | |
| 483 && GET_CODE (op) == SUBREG | |
| 484 && SUBREG_BYTE (op) == 0 | |
| 485 && (GET_MODE_SIZE (innermode) | |
| 486 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))) | |
| 487 return CONST0_RTX (outermode); | |
| 488 | |
| 489 gcc_assert (ret != NULL_RTX); | |
| 490 return ret; | |
| 491 } | |
| 492 | |
| 493 /* Return whether we should resolve X into the registers into which it | |
| 494 was decomposed. */ | |
| 495 | |
| 496 static bool | |
| 497 resolve_reg_p (rtx x) | |
| 498 { | |
| 499 return GET_CODE (x) == CONCATN; | |
| 500 } | |
| 501 | |
| 502 /* Return whether X is a SUBREG of a register which we need to | |
| 503 resolve. */ | |
| 504 | |
| 505 static bool | |
| 506 resolve_subreg_p (rtx x) | |
| 507 { | |
| 508 if (GET_CODE (x) != SUBREG) | |
| 509 return false; | |
| 510 return resolve_reg_p (SUBREG_REG (x)); | |
| 511 } | |
| 512 | |
| 513 /* This is called via for_each_rtx. Look for SUBREGs which need to be | |
| 514 decomposed. */ | |
| 515 | |
| 516 static int | |
| 517 resolve_subreg_use (rtx *px, void *data) | |
| 518 { | |
| 519 rtx insn = (rtx) data; | |
| 520 rtx x = *px; | |
| 521 | |
| 522 if (x == NULL_RTX) | |
| 523 return 0; | |
| 524 | |
| 525 if (resolve_subreg_p (x)) | |
| 526 { | |
| 527 x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x), | |
| 528 SUBREG_BYTE (x)); | |
| 529 | |
| 530 /* It is possible for a note to contain a reference which we can | |
| 531 decompose. In this case, return 1 to the caller to indicate | |
| 532 that the note must be removed. */ | |
| 533 if (!x) | |
| 534 { | |
| 535 gcc_assert (!insn); | |
| 536 return 1; | |
| 537 } | |
| 538 | |
| 539 validate_change (insn, px, x, 1); | |
| 540 return -1; | |
| 541 } | |
| 542 | |
| 543 if (resolve_reg_p (x)) | |
| 544 { | |
| 545 /* Return 1 to the caller to indicate that we found a direct | |
| 546 reference to a register which is being decomposed. This can | |
| 547 happen inside notes, multiword shift or zero-extend | |
| 548 instructions. */ | |
| 549 return 1; | |
| 550 } | |
| 551 | |
| 552 return 0; | |
| 553 } | |
| 554 | |
|
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555 /* This is called via for_each_rtx. Look for SUBREGs which can be |
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556 decomposed and decomposed REGs that need copying. */ |
| 0 | 557 |
|
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558 static int |
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559 adjust_decomposed_uses (rtx *px, void *data ATTRIBUTE_UNUSED) |
| 0 | 560 { |
|
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561 rtx x = *px; |
| 0 | 562 |
|
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563 if (x == NULL_RTX) |
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564 return 0; |
| 0 | 565 |
|
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566 if (resolve_subreg_p (x)) |
| 0 | 567 { |
|
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568 x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x), |
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569 SUBREG_BYTE (x)); |
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570 |
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571 if (x) |
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572 *px = x; |
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573 else |
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574 x = copy_rtx (*px); |
| 0 | 575 } |
|
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576 |
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577 if (resolve_reg_p (x)) |
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578 *px = copy_rtx (x); |
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579 |
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580 return 0; |
| 0 | 581 } |
| 582 | |
| 583 /* Resolve any decomposed registers which appear in register notes on | |
| 584 INSN. */ | |
| 585 | |
| 586 static void | |
| 587 resolve_reg_notes (rtx insn) | |
| 588 { | |
| 589 rtx *pnote, note; | |
| 590 | |
| 591 note = find_reg_equal_equiv_note (insn); | |
| 592 if (note) | |
| 593 { | |
| 594 int old_count = num_validated_changes (); | |
| 595 if (for_each_rtx (&XEXP (note, 0), resolve_subreg_use, NULL)) | |
| 596 remove_note (insn, note); | |
| 597 else | |
| 598 if (old_count != num_validated_changes ()) | |
| 599 df_notes_rescan (insn); | |
| 600 } | |
| 601 | |
| 602 pnote = ®_NOTES (insn); | |
| 603 while (*pnote != NULL_RTX) | |
| 604 { | |
| 605 bool del = false; | |
| 606 | |
| 607 note = *pnote; | |
| 608 switch (REG_NOTE_KIND (note)) | |
| 609 { | |
| 610 case REG_DEAD: | |
| 611 case REG_UNUSED: | |
| 612 if (resolve_reg_p (XEXP (note, 0))) | |
| 613 del = true; | |
| 614 break; | |
| 615 | |
| 616 default: | |
| 617 break; | |
| 618 } | |
| 619 | |
| 620 if (del) | |
| 621 *pnote = XEXP (note, 1); | |
| 622 else | |
| 623 pnote = &XEXP (note, 1); | |
| 624 } | |
| 625 } | |
| 626 | |
| 627 /* Return whether X can be decomposed into subwords. */ | |
| 628 | |
| 629 static bool | |
| 630 can_decompose_p (rtx x) | |
| 631 { | |
| 632 if (REG_P (x)) | |
| 633 { | |
| 634 unsigned int regno = REGNO (x); | |
| 635 | |
| 636 if (HARD_REGISTER_NUM_P (regno)) | |
| 637 return (validate_subreg (word_mode, GET_MODE (x), x, UNITS_PER_WORD) | |
| 638 && HARD_REGNO_MODE_OK (regno, word_mode)); | |
| 639 else | |
|
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640 return !bitmap_bit_p (subreg_context, regno); |
| 0 | 641 } |
| 642 | |
| 643 return true; | |
| 644 } | |
| 645 | |
| 646 /* Decompose the registers used in a simple move SET within INSN. If | |
| 647 we don't change anything, return INSN, otherwise return the start | |
| 648 of the sequence of moves. */ | |
| 649 | |
| 650 static rtx | |
| 651 resolve_simple_move (rtx set, rtx insn) | |
| 652 { | |
| 653 rtx src, dest, real_dest, insns; | |
| 654 enum machine_mode orig_mode, dest_mode; | |
| 655 unsigned int words; | |
| 656 bool pushing; | |
| 657 | |
| 658 src = SET_SRC (set); | |
| 659 dest = SET_DEST (set); | |
| 660 orig_mode = GET_MODE (dest); | |
| 661 | |
| 662 words = (GET_MODE_SIZE (orig_mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 663 if (words <= 1) | |
| 664 return insn; | |
| 665 | |
| 666 start_sequence (); | |
| 667 | |
| 668 /* We have to handle copying from a SUBREG of a decomposed reg where | |
| 669 the SUBREG is larger than word size. Rather than assume that we | |
| 670 can take a word_mode SUBREG of the destination, we copy to a new | |
| 671 register and then copy that to the destination. */ | |
| 672 | |
| 673 real_dest = NULL_RTX; | |
| 674 | |
| 675 if (GET_CODE (src) == SUBREG | |
| 676 && resolve_reg_p (SUBREG_REG (src)) | |
| 677 && (SUBREG_BYTE (src) != 0 | |
| 678 || (GET_MODE_SIZE (orig_mode) | |
| 679 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))) | |
| 680 { | |
| 681 real_dest = dest; | |
| 682 dest = gen_reg_rtx (orig_mode); | |
| 683 if (REG_P (real_dest)) | |
| 684 REG_ATTRS (dest) = REG_ATTRS (real_dest); | |
| 685 } | |
| 686 | |
| 687 /* Similarly if we are copying to a SUBREG of a decomposed reg where | |
| 688 the SUBREG is larger than word size. */ | |
| 689 | |
| 690 if (GET_CODE (dest) == SUBREG | |
| 691 && resolve_reg_p (SUBREG_REG (dest)) | |
| 692 && (SUBREG_BYTE (dest) != 0 | |
| 693 || (GET_MODE_SIZE (orig_mode) | |
| 694 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))) | |
| 695 { | |
| 696 rtx reg, minsn, smove; | |
| 697 | |
| 698 reg = gen_reg_rtx (orig_mode); | |
| 699 minsn = emit_move_insn (reg, src); | |
| 700 smove = single_set (minsn); | |
| 701 gcc_assert (smove != NULL_RTX); | |
| 702 resolve_simple_move (smove, minsn); | |
| 703 src = reg; | |
| 704 } | |
| 705 | |
| 706 /* If we didn't have any big SUBREGS of decomposed registers, and | |
| 707 neither side of the move is a register we are decomposing, then | |
| 708 we don't have to do anything here. */ | |
| 709 | |
| 710 if (src == SET_SRC (set) | |
| 711 && dest == SET_DEST (set) | |
| 712 && !resolve_reg_p (src) | |
| 713 && !resolve_subreg_p (src) | |
| 714 && !resolve_reg_p (dest) | |
| 715 && !resolve_subreg_p (dest)) | |
| 716 { | |
| 717 end_sequence (); | |
| 718 return insn; | |
| 719 } | |
| 720 | |
| 721 /* It's possible for the code to use a subreg of a decomposed | |
| 722 register while forming an address. We need to handle that before | |
| 723 passing the address to emit_move_insn. We pass NULL_RTX as the | |
| 724 insn parameter to resolve_subreg_use because we can not validate | |
| 725 the insn yet. */ | |
| 726 if (MEM_P (src) || MEM_P (dest)) | |
| 727 { | |
| 728 int acg; | |
| 729 | |
| 730 if (MEM_P (src)) | |
| 731 for_each_rtx (&XEXP (src, 0), resolve_subreg_use, NULL_RTX); | |
| 732 if (MEM_P (dest)) | |
| 733 for_each_rtx (&XEXP (dest, 0), resolve_subreg_use, NULL_RTX); | |
| 734 acg = apply_change_group (); | |
| 735 gcc_assert (acg); | |
| 736 } | |
| 737 | |
| 738 /* If SRC is a register which we can't decompose, or has side | |
| 739 effects, we need to move via a temporary register. */ | |
| 740 | |
| 741 if (!can_decompose_p (src) | |
| 742 || side_effects_p (src) | |
| 743 || GET_CODE (src) == ASM_OPERANDS) | |
| 744 { | |
| 745 rtx reg; | |
| 746 | |
| 747 reg = gen_reg_rtx (orig_mode); | |
| 748 emit_move_insn (reg, src); | |
| 749 src = reg; | |
| 750 } | |
| 751 | |
| 752 /* If DEST is a register which we can't decompose, or has side | |
| 753 effects, we need to first move to a temporary register. We | |
| 754 handle the common case of pushing an operand directly. We also | |
| 755 go through a temporary register if it holds a floating point | |
| 756 value. This gives us better code on systems which can't move | |
| 757 data easily between integer and floating point registers. */ | |
| 758 | |
| 759 dest_mode = orig_mode; | |
| 760 pushing = push_operand (dest, dest_mode); | |
| 761 if (!can_decompose_p (dest) | |
| 762 || (side_effects_p (dest) && !pushing) | |
| 763 || (!SCALAR_INT_MODE_P (dest_mode) | |
| 764 && !resolve_reg_p (dest) | |
| 765 && !resolve_subreg_p (dest))) | |
| 766 { | |
| 767 if (real_dest == NULL_RTX) | |
| 768 real_dest = dest; | |
| 769 if (!SCALAR_INT_MODE_P (dest_mode)) | |
| 770 { | |
| 771 dest_mode = mode_for_size (GET_MODE_SIZE (dest_mode) * BITS_PER_UNIT, | |
| 772 MODE_INT, 0); | |
| 773 gcc_assert (dest_mode != BLKmode); | |
| 774 } | |
| 775 dest = gen_reg_rtx (dest_mode); | |
| 776 if (REG_P (real_dest)) | |
| 777 REG_ATTRS (dest) = REG_ATTRS (real_dest); | |
| 778 } | |
| 779 | |
| 780 if (pushing) | |
| 781 { | |
| 782 unsigned int i, j, jinc; | |
| 783 | |
| 784 gcc_assert (GET_MODE_SIZE (orig_mode) % UNITS_PER_WORD == 0); | |
| 785 gcc_assert (GET_CODE (XEXP (dest, 0)) != PRE_MODIFY); | |
| 786 gcc_assert (GET_CODE (XEXP (dest, 0)) != POST_MODIFY); | |
| 787 | |
| 788 if (WORDS_BIG_ENDIAN == STACK_GROWS_DOWNWARD) | |
| 789 { | |
| 790 j = 0; | |
| 791 jinc = 1; | |
| 792 } | |
| 793 else | |
| 794 { | |
| 795 j = words - 1; | |
| 796 jinc = -1; | |
| 797 } | |
| 798 | |
| 799 for (i = 0; i < words; ++i, j += jinc) | |
| 800 { | |
| 801 rtx temp; | |
| 802 | |
| 803 temp = copy_rtx (XEXP (dest, 0)); | |
| 804 temp = adjust_automodify_address_nv (dest, word_mode, temp, | |
| 805 j * UNITS_PER_WORD); | |
| 806 emit_move_insn (temp, | |
| 807 simplify_gen_subreg_concatn (word_mode, src, | |
| 808 orig_mode, | |
| 809 j * UNITS_PER_WORD)); | |
| 810 } | |
| 811 } | |
| 812 else | |
| 813 { | |
| 814 unsigned int i; | |
| 815 | |
| 816 if (REG_P (dest) && !HARD_REGISTER_NUM_P (REGNO (dest))) | |
| 817 emit_clobber (dest); | |
| 818 | |
| 819 for (i = 0; i < words; ++i) | |
| 820 emit_move_insn (simplify_gen_subreg_concatn (word_mode, dest, | |
| 821 dest_mode, | |
| 822 i * UNITS_PER_WORD), | |
| 823 simplify_gen_subreg_concatn (word_mode, src, | |
| 824 orig_mode, | |
| 825 i * UNITS_PER_WORD)); | |
| 826 } | |
| 827 | |
| 828 if (real_dest != NULL_RTX) | |
| 829 { | |
| 830 rtx mdest, minsn, smove; | |
| 831 | |
| 832 if (dest_mode == orig_mode) | |
| 833 mdest = dest; | |
| 834 else | |
| 835 mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0); | |
| 836 minsn = emit_move_insn (real_dest, mdest); | |
| 837 | |
| 838 smove = single_set (minsn); | |
| 839 gcc_assert (smove != NULL_RTX); | |
| 840 | |
| 841 resolve_simple_move (smove, minsn); | |
| 842 } | |
| 843 | |
| 844 insns = get_insns (); | |
| 845 end_sequence (); | |
| 846 | |
|
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847 copy_reg_eh_region_note_forward (insn, insns, NULL_RTX); |
| 0 | 848 |
| 849 emit_insn_before (insns, insn); | |
| 850 | |
| 851 delete_insn (insn); | |
| 852 | |
| 853 return insns; | |
| 854 } | |
| 855 | |
| 856 /* Change a CLOBBER of a decomposed register into a CLOBBER of the | |
| 857 component registers. Return whether we changed something. */ | |
| 858 | |
| 859 static bool | |
| 860 resolve_clobber (rtx pat, rtx insn) | |
| 861 { | |
| 862 rtx reg; | |
| 863 enum machine_mode orig_mode; | |
| 864 unsigned int words, i; | |
| 865 int ret; | |
| 866 | |
| 867 reg = XEXP (pat, 0); | |
| 868 if (!resolve_reg_p (reg) && !resolve_subreg_p (reg)) | |
| 869 return false; | |
| 870 | |
| 871 orig_mode = GET_MODE (reg); | |
| 872 words = GET_MODE_SIZE (orig_mode); | |
| 873 words = (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
| 874 | |
| 875 ret = validate_change (NULL_RTX, &XEXP (pat, 0), | |
| 876 simplify_gen_subreg_concatn (word_mode, reg, | |
| 877 orig_mode, 0), | |
| 878 0); | |
| 879 df_insn_rescan (insn); | |
| 880 gcc_assert (ret != 0); | |
| 881 | |
| 882 for (i = words - 1; i > 0; --i) | |
| 883 { | |
| 884 rtx x; | |
| 885 | |
| 886 x = simplify_gen_subreg_concatn (word_mode, reg, orig_mode, | |
| 887 i * UNITS_PER_WORD); | |
| 888 x = gen_rtx_CLOBBER (VOIDmode, x); | |
| 889 emit_insn_after (x, insn); | |
| 890 } | |
| 891 | |
| 892 resolve_reg_notes (insn); | |
| 893 | |
| 894 return true; | |
| 895 } | |
| 896 | |
| 897 /* A USE of a decomposed register is no longer meaningful. Return | |
| 898 whether we changed something. */ | |
| 899 | |
| 900 static bool | |
| 901 resolve_use (rtx pat, rtx insn) | |
| 902 { | |
| 903 if (resolve_reg_p (XEXP (pat, 0)) || resolve_subreg_p (XEXP (pat, 0))) | |
| 904 { | |
| 905 delete_insn (insn); | |
| 906 return true; | |
| 907 } | |
| 908 | |
| 909 resolve_reg_notes (insn); | |
| 910 | |
| 911 return false; | |
| 912 } | |
| 913 | |
|
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914 /* A VAR_LOCATION can be simplified. */ |
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915 |
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916 static void |
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917 resolve_debug (rtx insn) |
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918 { |
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919 for_each_rtx (&PATTERN (insn), adjust_decomposed_uses, NULL_RTX); |
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920 |
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921 df_insn_rescan (insn); |
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922 |
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923 resolve_reg_notes (insn); |
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924 } |
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925 |
| 0 | 926 /* Checks if INSN is a decomposable multiword-shift or zero-extend and |
| 927 sets the decomposable_context bitmap accordingly. A non-zero value | |
| 928 is returned if a decomposable insn has been found. */ | |
| 929 | |
| 930 static int | |
| 931 find_decomposable_shift_zext (rtx insn) | |
| 932 { | |
| 933 rtx set; | |
| 934 rtx op; | |
| 935 rtx op_operand; | |
| 936 | |
| 937 set = single_set (insn); | |
| 938 if (!set) | |
| 939 return 0; | |
| 940 | |
| 941 op = SET_SRC (set); | |
| 942 if (GET_CODE (op) != ASHIFT | |
| 943 && GET_CODE (op) != LSHIFTRT | |
| 944 && GET_CODE (op) != ZERO_EXTEND) | |
| 945 return 0; | |
| 946 | |
| 947 op_operand = XEXP (op, 0); | |
| 948 if (!REG_P (SET_DEST (set)) || !REG_P (op_operand) | |
| 949 || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set))) | |
| 950 || HARD_REGISTER_NUM_P (REGNO (op_operand)) | |
| 951 || !SCALAR_INT_MODE_P (GET_MODE (op))) | |
| 952 return 0; | |
| 953 | |
| 954 if (GET_CODE (op) == ZERO_EXTEND) | |
| 955 { | |
| 956 if (GET_MODE (op_operand) != word_mode | |
| 957 || GET_MODE_BITSIZE (GET_MODE (op)) != 2 * BITS_PER_WORD) | |
| 958 return 0; | |
| 959 } | |
| 960 else /* left or right shift */ | |
| 961 { | |
|
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962 if (!CONST_INT_P (XEXP (op, 1)) |
| 0 | 963 || INTVAL (XEXP (op, 1)) < BITS_PER_WORD |
| 964 || GET_MODE_BITSIZE (GET_MODE (op_operand)) != 2 * BITS_PER_WORD) | |
| 965 return 0; | |
| 966 } | |
| 967 | |
| 968 bitmap_set_bit (decomposable_context, REGNO (SET_DEST (set))); | |
| 969 | |
| 970 if (GET_CODE (op) != ZERO_EXTEND) | |
| 971 bitmap_set_bit (decomposable_context, REGNO (op_operand)); | |
| 972 | |
| 973 return 1; | |
| 974 } | |
| 975 | |
| 976 /* Decompose a more than word wide shift (in INSN) of a multiword | |
| 977 pseudo or a multiword zero-extend of a wordmode pseudo into a move | |
| 978 and 'set to zero' insn. Return a pointer to the new insn when a | |
| 979 replacement was done. */ | |
| 980 | |
| 981 static rtx | |
| 982 resolve_shift_zext (rtx insn) | |
| 983 { | |
| 984 rtx set; | |
| 985 rtx op; | |
| 986 rtx op_operand; | |
| 987 rtx insns; | |
| 988 rtx src_reg, dest_reg, dest_zero; | |
| 989 int src_reg_num, dest_reg_num, offset1, offset2, src_offset; | |
| 990 | |
| 991 set = single_set (insn); | |
| 992 if (!set) | |
| 993 return NULL_RTX; | |
| 994 | |
| 995 op = SET_SRC (set); | |
| 996 if (GET_CODE (op) != ASHIFT | |
| 997 && GET_CODE (op) != LSHIFTRT | |
| 998 && GET_CODE (op) != ZERO_EXTEND) | |
| 999 return NULL_RTX; | |
| 1000 | |
| 1001 op_operand = XEXP (op, 0); | |
| 1002 | |
| 1003 if (!resolve_reg_p (SET_DEST (set)) && !resolve_reg_p (op_operand)) | |
| 1004 return NULL_RTX; | |
| 1005 | |
| 1006 /* src_reg_num is the number of the word mode register which we | |
| 1007 are operating on. For a left shift and a zero_extend on little | |
| 1008 endian machines this is register 0. */ | |
| 1009 src_reg_num = GET_CODE (op) == LSHIFTRT ? 1 : 0; | |
| 1010 | |
| 1011 if (WORDS_BIG_ENDIAN | |
| 1012 && GET_MODE_SIZE (GET_MODE (op_operand)) > UNITS_PER_WORD) | |
| 1013 src_reg_num = 1 - src_reg_num; | |
| 1014 | |
| 1015 if (GET_CODE (op) == ZERO_EXTEND) | |
| 1016 dest_reg_num = WORDS_BIG_ENDIAN ? 1 : 0; | |
| 1017 else | |
| 1018 dest_reg_num = 1 - src_reg_num; | |
| 1019 | |
| 1020 offset1 = UNITS_PER_WORD * dest_reg_num; | |
| 1021 offset2 = UNITS_PER_WORD * (1 - dest_reg_num); | |
| 1022 src_offset = UNITS_PER_WORD * src_reg_num; | |
| 1023 | |
| 1024 start_sequence (); | |
| 1025 | |
| 1026 dest_reg = simplify_gen_subreg_concatn (word_mode, SET_DEST (set), | |
| 1027 GET_MODE (SET_DEST (set)), | |
| 1028 offset1); | |
| 1029 dest_zero = simplify_gen_subreg_concatn (word_mode, SET_DEST (set), | |
| 1030 GET_MODE (SET_DEST (set)), | |
| 1031 offset2); | |
| 1032 src_reg = simplify_gen_subreg_concatn (word_mode, op_operand, | |
| 1033 GET_MODE (op_operand), | |
| 1034 src_offset); | |
| 1035 if (GET_CODE (op) != ZERO_EXTEND) | |
| 1036 { | |
| 1037 int shift_count = INTVAL (XEXP (op, 1)); | |
| 1038 if (shift_count > BITS_PER_WORD) | |
| 1039 src_reg = expand_shift (GET_CODE (op) == ASHIFT ? | |
| 1040 LSHIFT_EXPR : RSHIFT_EXPR, | |
| 1041 word_mode, src_reg, | |
| 1042 build_int_cst (NULL_TREE, | |
| 1043 shift_count - BITS_PER_WORD), | |
| 1044 dest_reg, 1); | |
| 1045 } | |
| 1046 | |
| 1047 if (dest_reg != src_reg) | |
| 1048 emit_move_insn (dest_reg, src_reg); | |
| 1049 emit_move_insn (dest_zero, CONST0_RTX (word_mode)); | |
| 1050 insns = get_insns (); | |
| 1051 | |
| 1052 end_sequence (); | |
| 1053 | |
| 1054 emit_insn_before (insns, insn); | |
| 1055 | |
| 1056 if (dump_file) | |
| 1057 { | |
| 1058 rtx in; | |
| 1059 fprintf (dump_file, "; Replacing insn: %d with insns: ", INSN_UID (insn)); | |
| 1060 for (in = insns; in != insn; in = NEXT_INSN (in)) | |
| 1061 fprintf (dump_file, "%d ", INSN_UID (in)); | |
| 1062 fprintf (dump_file, "\n"); | |
| 1063 } | |
| 1064 | |
| 1065 delete_insn (insn); | |
| 1066 return insns; | |
| 1067 } | |
| 1068 | |
| 1069 /* Look for registers which are always accessed via word-sized SUBREGs | |
| 1070 or via copies. Decompose these registers into several word-sized | |
| 1071 pseudo-registers. */ | |
| 1072 | |
| 1073 static void | |
| 1074 decompose_multiword_subregs (void) | |
| 1075 { | |
| 1076 unsigned int max; | |
| 1077 basic_block bb; | |
| 1078 | |
| 1079 if (df) | |
| 1080 df_set_flags (DF_DEFER_INSN_RESCAN); | |
| 1081 | |
| 1082 max = max_reg_num (); | |
| 1083 | |
| 1084 /* First see if there are any multi-word pseudo-registers. If there | |
| 1085 aren't, there is nothing we can do. This should speed up this | |
| 1086 pass in the normal case, since it should be faster than scanning | |
| 1087 all the insns. */ | |
| 1088 { | |
| 1089 unsigned int i; | |
| 1090 | |
| 1091 for (i = FIRST_PSEUDO_REGISTER; i < max; ++i) | |
| 1092 { | |
| 1093 if (regno_reg_rtx[i] != NULL | |
| 1094 && GET_MODE_SIZE (GET_MODE (regno_reg_rtx[i])) > UNITS_PER_WORD) | |
| 1095 break; | |
| 1096 } | |
| 1097 if (i == max) | |
| 1098 return; | |
| 1099 } | |
| 1100 | |
|
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1101 if (df) |
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1102 run_word_dce (); |
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1103 |
| 0 | 1104 /* FIXME: When the dataflow branch is merged, we can change this |
| 1105 code to look for each multi-word pseudo-register and to find each | |
| 1106 insn which sets or uses that register. That should be faster | |
| 1107 than scanning all the insns. */ | |
| 1108 | |
| 1109 decomposable_context = BITMAP_ALLOC (NULL); | |
| 1110 non_decomposable_context = BITMAP_ALLOC (NULL); | |
|
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1111 subreg_context = BITMAP_ALLOC (NULL); |
| 0 | 1112 |
| 1113 reg_copy_graph = VEC_alloc (bitmap, heap, max); | |
| 1114 VEC_safe_grow (bitmap, heap, reg_copy_graph, max); | |
| 1115 memset (VEC_address (bitmap, reg_copy_graph), 0, sizeof (bitmap) * max); | |
| 1116 | |
| 1117 FOR_EACH_BB (bb) | |
| 1118 { | |
| 1119 rtx insn; | |
| 1120 | |
| 1121 FOR_BB_INSNS (bb, insn) | |
| 1122 { | |
| 1123 rtx set; | |
| 1124 enum classify_move_insn cmi; | |
| 1125 int i, n; | |
| 1126 | |
| 1127 if (!INSN_P (insn) | |
| 1128 || GET_CODE (PATTERN (insn)) == CLOBBER | |
| 1129 || GET_CODE (PATTERN (insn)) == USE) | |
| 1130 continue; | |
| 1131 | |
| 1132 if (find_decomposable_shift_zext (insn)) | |
| 1133 continue; | |
| 1134 | |
| 1135 recog_memoized (insn); | |
| 1136 extract_insn (insn); | |
| 1137 | |
| 1138 set = simple_move (insn); | |
| 1139 | |
| 1140 if (!set) | |
| 1141 cmi = NOT_SIMPLE_MOVE; | |
| 1142 else | |
| 1143 { | |
| 1144 if (find_pseudo_copy (set)) | |
| 1145 cmi = SIMPLE_PSEUDO_REG_MOVE; | |
| 1146 else | |
| 1147 cmi = SIMPLE_MOVE; | |
| 1148 } | |
| 1149 | |
| 1150 n = recog_data.n_operands; | |
| 1151 for (i = 0; i < n; ++i) | |
| 1152 { | |
| 1153 for_each_rtx (&recog_data.operand[i], | |
| 1154 find_decomposable_subregs, | |
| 1155 &cmi); | |
| 1156 | |
| 1157 /* We handle ASM_OPERANDS as a special case to support | |
| 1158 things like x86 rdtsc which returns a DImode value. | |
| 1159 We can decompose the output, which will certainly be | |
| 1160 operand 0, but not the inputs. */ | |
| 1161 | |
| 1162 if (cmi == SIMPLE_MOVE | |
| 1163 && GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
| 1164 { | |
| 1165 gcc_assert (i == 0); | |
| 1166 cmi = NOT_SIMPLE_MOVE; | |
| 1167 } | |
| 1168 } | |
| 1169 } | |
| 1170 } | |
| 1171 | |
| 1172 bitmap_and_compl_into (decomposable_context, non_decomposable_context); | |
| 1173 if (!bitmap_empty_p (decomposable_context)) | |
| 1174 { | |
| 1175 sbitmap sub_blocks; | |
| 1176 unsigned int i; | |
| 1177 sbitmap_iterator sbi; | |
| 1178 bitmap_iterator iter; | |
| 1179 unsigned int regno; | |
| 1180 | |
| 1181 propagate_pseudo_copies (); | |
| 1182 | |
| 1183 sub_blocks = sbitmap_alloc (last_basic_block); | |
| 1184 sbitmap_zero (sub_blocks); | |
| 1185 | |
| 1186 EXECUTE_IF_SET_IN_BITMAP (decomposable_context, 0, regno, iter) | |
| 1187 decompose_register (regno); | |
| 1188 | |
| 1189 FOR_EACH_BB (bb) | |
| 1190 { | |
| 1191 rtx insn; | |
| 1192 | |
| 1193 FOR_BB_INSNS (bb, insn) | |
| 1194 { | |
|
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1195 rtx pat; |
| 0 | 1196 |
| 1197 if (!INSN_P (insn)) | |
| 1198 continue; | |
| 1199 | |
| 1200 pat = PATTERN (insn); | |
| 1201 if (GET_CODE (pat) == CLOBBER) | |
| 1202 resolve_clobber (pat, insn); | |
| 1203 else if (GET_CODE (pat) == USE) | |
| 1204 resolve_use (pat, insn); | |
|
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1205 else if (DEBUG_INSN_P (insn)) |
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1206 resolve_debug (insn); |
| 0 | 1207 else |
| 1208 { | |
| 1209 rtx set; | |
| 1210 int i; | |
| 1211 | |
| 1212 recog_memoized (insn); | |
| 1213 extract_insn (insn); | |
| 1214 | |
| 1215 set = simple_move (insn); | |
| 1216 if (set) | |
| 1217 { | |
| 1218 rtx orig_insn = insn; | |
| 1219 bool cfi = control_flow_insn_p (insn); | |
| 1220 | |
| 1221 /* We can end up splitting loads to multi-word pseudos | |
| 1222 into separate loads to machine word size pseudos. | |
| 1223 When this happens, we first had one load that can | |
| 1224 throw, and after resolve_simple_move we'll have a | |
| 1225 bunch of loads (at least two). All those loads may | |
| 1226 trap if we can have non-call exceptions, so they | |
| 1227 all will end the current basic block. We split the | |
| 1228 block after the outer loop over all insns, but we | |
| 1229 make sure here that we will be able to split the | |
| 1230 basic block and still produce the correct control | |
| 1231 flow graph for it. */ | |
| 1232 gcc_assert (!cfi | |
|
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1233 || (cfun->can_throw_non_call_exceptions |
| 0 | 1234 && can_throw_internal (insn))); |
| 1235 | |
| 1236 insn = resolve_simple_move (set, insn); | |
| 1237 if (insn != orig_insn) | |
| 1238 { | |
| 1239 recog_memoized (insn); | |
| 1240 extract_insn (insn); | |
| 1241 | |
| 1242 if (cfi) | |
| 1243 SET_BIT (sub_blocks, bb->index); | |
| 1244 } | |
| 1245 } | |
| 1246 else | |
| 1247 { | |
| 1248 rtx decomposed_shift; | |
| 1249 | |
| 1250 decomposed_shift = resolve_shift_zext (insn); | |
| 1251 if (decomposed_shift != NULL_RTX) | |
| 1252 { | |
| 1253 insn = decomposed_shift; | |
| 1254 recog_memoized (insn); | |
| 1255 extract_insn (insn); | |
| 1256 } | |
| 1257 } | |
| 1258 | |
| 1259 for (i = recog_data.n_operands - 1; i >= 0; --i) | |
| 1260 for_each_rtx (recog_data.operand_loc[i], | |
| 1261 resolve_subreg_use, | |
| 1262 insn); | |
| 1263 | |
| 1264 resolve_reg_notes (insn); | |
| 1265 | |
| 1266 if (num_validated_changes () > 0) | |
| 1267 { | |
| 1268 for (i = recog_data.n_dups - 1; i >= 0; --i) | |
| 1269 { | |
| 1270 rtx *pl = recog_data.dup_loc[i]; | |
| 1271 int dup_num = recog_data.dup_num[i]; | |
| 1272 rtx *px = recog_data.operand_loc[dup_num]; | |
| 1273 | |
| 1274 validate_unshare_change (insn, pl, *px, 1); | |
| 1275 } | |
| 1276 | |
| 1277 i = apply_change_group (); | |
| 1278 gcc_assert (i); | |
| 1279 } | |
| 1280 } | |
| 1281 } | |
| 1282 } | |
| 1283 | |
| 1284 /* If we had insns to split that caused control flow insns in the middle | |
| 1285 of a basic block, split those blocks now. Note that we only handle | |
| 1286 the case where splitting a load has caused multiple possibly trapping | |
| 1287 loads to appear. */ | |
| 1288 EXECUTE_IF_SET_IN_SBITMAP (sub_blocks, 0, i, sbi) | |
| 1289 { | |
| 1290 rtx insn, end; | |
| 1291 edge fallthru; | |
| 1292 | |
| 1293 bb = BASIC_BLOCK (i); | |
| 1294 insn = BB_HEAD (bb); | |
| 1295 end = BB_END (bb); | |
| 1296 | |
| 1297 while (insn != end) | |
| 1298 { | |
| 1299 if (control_flow_insn_p (insn)) | |
| 1300 { | |
| 1301 /* Split the block after insn. There will be a fallthru | |
| 1302 edge, which is OK so we keep it. We have to create the | |
| 1303 exception edges ourselves. */ | |
| 1304 fallthru = split_block (bb, insn); | |
| 1305 rtl_make_eh_edge (NULL, bb, BB_END (bb)); | |
| 1306 bb = fallthru->dest; | |
| 1307 insn = BB_HEAD (bb); | |
| 1308 } | |
| 1309 else | |
| 1310 insn = NEXT_INSN (insn); | |
| 1311 } | |
| 1312 } | |
| 1313 | |
| 1314 sbitmap_free (sub_blocks); | |
| 1315 } | |
| 1316 | |
| 1317 { | |
| 1318 unsigned int i; | |
| 1319 bitmap b; | |
| 1320 | |
|
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1321 FOR_EACH_VEC_ELT (bitmap, reg_copy_graph, i, b) |
| 0 | 1322 if (b) |
| 1323 BITMAP_FREE (b); | |
| 1324 } | |
| 1325 | |
|
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1326 VEC_free (bitmap, heap, reg_copy_graph); |
| 0 | 1327 |
| 1328 BITMAP_FREE (decomposable_context); | |
| 1329 BITMAP_FREE (non_decomposable_context); | |
|
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1330 BITMAP_FREE (subreg_context); |
| 0 | 1331 } |
| 1332 | |
| 1333 /* Gate function for lower subreg pass. */ | |
| 1334 | |
| 1335 static bool | |
| 1336 gate_handle_lower_subreg (void) | |
| 1337 { | |
| 1338 return flag_split_wide_types != 0; | |
| 1339 } | |
| 1340 | |
| 1341 /* Implement first lower subreg pass. */ | |
| 1342 | |
| 1343 static unsigned int | |
| 1344 rest_of_handle_lower_subreg (void) | |
| 1345 { | |
| 1346 decompose_multiword_subregs (); | |
| 1347 return 0; | |
| 1348 } | |
| 1349 | |
| 1350 /* Implement second lower subreg pass. */ | |
| 1351 | |
| 1352 static unsigned int | |
| 1353 rest_of_handle_lower_subreg2 (void) | |
| 1354 { | |
| 1355 decompose_multiword_subregs (); | |
| 1356 return 0; | |
| 1357 } | |
| 1358 | |
| 1359 struct rtl_opt_pass pass_lower_subreg = | |
| 1360 { | |
| 1361 { | |
| 1362 RTL_PASS, | |
| 1363 "subreg1", /* name */ | |
| 1364 gate_handle_lower_subreg, /* gate */ | |
| 1365 rest_of_handle_lower_subreg, /* execute */ | |
| 1366 NULL, /* sub */ | |
| 1367 NULL, /* next */ | |
| 1368 0, /* static_pass_number */ | |
| 1369 TV_LOWER_SUBREG, /* tv_id */ | |
| 1370 0, /* properties_required */ | |
| 1371 0, /* properties_provided */ | |
| 1372 0, /* properties_destroyed */ | |
| 1373 0, /* todo_flags_start */ | |
| 1374 TODO_dump_func | | |
| 1375 TODO_ggc_collect | | |
| 1376 TODO_verify_flow /* todo_flags_finish */ | |
| 1377 } | |
| 1378 }; | |
| 1379 | |
| 1380 struct rtl_opt_pass pass_lower_subreg2 = | |
| 1381 { | |
| 1382 { | |
| 1383 RTL_PASS, | |
| 1384 "subreg2", /* name */ | |
| 1385 gate_handle_lower_subreg, /* gate */ | |
| 1386 rest_of_handle_lower_subreg2, /* execute */ | |
| 1387 NULL, /* sub */ | |
| 1388 NULL, /* next */ | |
| 1389 0, /* static_pass_number */ | |
| 1390 TV_LOWER_SUBREG, /* tv_id */ | |
| 1391 0, /* properties_required */ | |
| 1392 0, /* properties_provided */ | |
| 1393 0, /* properties_destroyed */ | |
| 1394 0, /* todo_flags_start */ | |
| 1395 TODO_df_finish | TODO_verify_rtl_sharing | | |
| 1396 TODO_dump_func | | |
| 1397 TODO_ggc_collect | | |
| 1398 TODO_verify_flow /* todo_flags_finish */ | |
| 1399 } | |
| 1400 }; |