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111
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1 /* Machine description for AArch64 architecture.
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145
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2 Copyright (C) 2009-2020 Free Software Foundation, Inc.
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3 Contributed by ARM Ltd.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but
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13 WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 #ifndef GCC_AARCH64_PROTOS_H
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23 #define GCC_AARCH64_PROTOS_H
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24
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25 #include "input.h"
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26
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27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
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28 high and lo relocs that calculate the base address using a PC
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29 relative reloc.
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30 So to get the address of foo, we generate
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31 adrp x0, foo
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32 add x0, x0, :lo12:foo
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33
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34 To load or store something to foo, we could use the corresponding
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35 load store variants that generate an
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36 ldr x0, [x0,:lo12:foo]
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37 or
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38 str x1, [x0, :lo12:foo]
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39
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40 This corresponds to the small code model of the compiler.
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41
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42 SYMBOL_SMALL_GOT_4G: Similar to the one above but this
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43 gives us the GOT entry of the symbol being referred to :
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44 Thus calculating the GOT entry for foo is done using the
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45 following sequence of instructions. The ADRP instruction
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46 gets us to the page containing the GOT entry of the symbol
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47 and the got_lo12 gets us the actual offset in it, together
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48 the base and offset, we can address 4G size GOT table.
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49
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50 adrp x0, :got:foo
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51 ldr x0, [x0, :gotoff_lo12:foo]
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52
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53 This corresponds to the small PIC model of the compiler.
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54
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55 SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
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56 restricted within 28K GOT table size.
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57
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58 ldr reg, [gp, #:gotpage_lo15:sym]
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59
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60 This corresponds to -fpic model for small memory model of the compiler.
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61
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62 SYMBOL_SMALL_TLSGD
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63 SYMBOL_SMALL_TLSDESC
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64 SYMBOL_SMALL_TLSIE
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65 SYMBOL_TINY_TLSIE
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66 SYMBOL_TLSLE12
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67 SYMBOL_TLSLE24
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68 SYMBOL_TLSLE32
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69 SYMBOL_TLSLE48
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70 Each of these represents a thread-local symbol, and corresponds to the
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71 thread local storage relocation operator for the symbol being referred to.
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72
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73 SYMBOL_TINY_ABSOLUTE
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74
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75 Generate symbol accesses as a PC relative address using a single
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76 instruction. To compute the address of symbol foo, we generate:
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77
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78 ADR x0, foo
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79
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80 SYMBOL_TINY_GOT
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81
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82 Generate symbol accesses via the GOT using a single PC relative
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83 instruction. To compute the address of symbol foo, we generate:
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84
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85 ldr t0, :got:foo
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86
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87 The value of foo can subsequently read using:
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88
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89 ldrb t0, [t0]
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90
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91 SYMBOL_FORCE_TO_MEM : Global variables are addressed using
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92 constant pool. All variable addresses are spilled into constant
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93 pools. The constant pools themselves are addressed using PC
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94 relative accesses. This only works for the large code model.
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95 */
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96 enum aarch64_symbol_type
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97 {
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98 SYMBOL_SMALL_ABSOLUTE,
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99 SYMBOL_SMALL_GOT_28K,
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100 SYMBOL_SMALL_GOT_4G,
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101 SYMBOL_SMALL_TLSGD,
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102 SYMBOL_SMALL_TLSDESC,
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103 SYMBOL_SMALL_TLSIE,
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104 SYMBOL_TINY_ABSOLUTE,
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105 SYMBOL_TINY_GOT,
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106 SYMBOL_TINY_TLSIE,
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107 SYMBOL_TLSLE12,
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108 SYMBOL_TLSLE24,
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109 SYMBOL_TLSLE32,
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110 SYMBOL_TLSLE48,
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111 SYMBOL_FORCE_TO_MEM
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112 };
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113
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131
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114 /* Classifies the type of an address query.
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115
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116 ADDR_QUERY_M
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117 Query what is valid for an "m" constraint and a memory_operand
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118 (the rules are the same for both).
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119
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120 ADDR_QUERY_LDP_STP
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121 Query what is valid for a load/store pair.
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122
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123 ADDR_QUERY_LDP_STP_N
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124 Query what is valid for a load/store pair, but narrow the incoming mode
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125 for address checking. This is used for the store_pair_lanes patterns.
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126
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127 ADDR_QUERY_ANY
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128 Query what is valid for at least one memory constraint, which may
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129 allow things that "m" doesn't. For example, the SVE LDR and STR
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130 addressing modes allow a wider range of immediate offsets than "m"
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131 does. */
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132 enum aarch64_addr_query_type {
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133 ADDR_QUERY_M,
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134 ADDR_QUERY_LDP_STP,
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135 ADDR_QUERY_LDP_STP_N,
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136 ADDR_QUERY_ANY
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137 };
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138
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111
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139 /* A set of tuning parameters contains references to size and time
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140 cost models and vectors for address cost calculations, register
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141 move costs and memory move costs. */
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142
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143 /* Scaled addressing modes can vary cost depending on the mode of the
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144 value to be loaded/stored. QImode values cannot use scaled
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145 addressing modes. */
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146
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147 struct scale_addr_mode_cost
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148 {
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149 const int hi;
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150 const int si;
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151 const int di;
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152 const int ti;
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153 };
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154
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155 /* Additional cost for addresses. */
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156 struct cpu_addrcost_table
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157 {
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158 const struct scale_addr_mode_cost addr_scale_costs;
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159 const int pre_modify;
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160 const int post_modify;
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161 const int register_offset;
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162 const int register_sextend;
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163 const int register_zextend;
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164 const int imm_offset;
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165 };
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166
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167 /* Additional costs for register copies. Cost is for one register. */
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168 struct cpu_regmove_cost
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169 {
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170 const int GP2GP;
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171 const int GP2FP;
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172 const int FP2GP;
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173 const int FP2FP;
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174 };
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175
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176 /* Cost for vector insn classes. */
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177 struct cpu_vector_cost
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178 {
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179 const int scalar_int_stmt_cost; /* Cost of any int scalar operation,
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180 excluding load and store. */
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181 const int scalar_fp_stmt_cost; /* Cost of any fp scalar operation,
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182 excluding load and store. */
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183 const int scalar_load_cost; /* Cost of scalar load. */
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184 const int scalar_store_cost; /* Cost of scalar store. */
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185 const int vec_int_stmt_cost; /* Cost of any int vector operation,
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186 excluding load, store, permute,
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187 vector-to-scalar and
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188 scalar-to-vector operation. */
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189 const int vec_fp_stmt_cost; /* Cost of any fp vector operation,
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190 excluding load, store, permute,
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191 vector-to-scalar and
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192 scalar-to-vector operation. */
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193 const int vec_permute_cost; /* Cost of permute operation. */
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194 const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */
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195 const int scalar_to_vec_cost; /* Cost of scalar-to-vector
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196 operation. */
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197 const int vec_align_load_cost; /* Cost of aligned vector load. */
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198 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
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199 const int vec_unalign_store_cost; /* Cost of unaligned vector store. */
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200 const int vec_store_cost; /* Cost of vector store. */
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201 const int cond_taken_branch_cost; /* Cost of taken branch. */
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202 const int cond_not_taken_branch_cost; /* Cost of not taken branch. */
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203 };
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204
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205 /* Branch costs. */
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206 struct cpu_branch_cost
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207 {
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208 const int predictable; /* Predictable branch or optimizing for size. */
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209 const int unpredictable; /* Unpredictable branch or optimizing for speed. */
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210 };
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211
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212 /* Control approximate alternatives to certain FP operators. */
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213 #define AARCH64_APPROX_MODE(MODE) \
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214 ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
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215 ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
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216 : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
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217 ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
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218 + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
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219 : (0))
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220 #define AARCH64_APPROX_NONE (0)
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221 #define AARCH64_APPROX_ALL (-1)
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222
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223 /* Allowed modes for approximations. */
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224 struct cpu_approx_modes
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225 {
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226 const unsigned int division; /* Division. */
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227 const unsigned int sqrt; /* Square root. */
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228 const unsigned int recip_sqrt; /* Reciprocal square root. */
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229 };
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230
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231 /* Cache prefetch settings for prefetch-loop-arrays. */
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232 struct cpu_prefetch_tune
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233 {
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234 const int num_slots;
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235 const int l1_cache_size;
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236 const int l1_cache_line_size;
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237 const int l2_cache_size;
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131
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238 /* Whether software prefetch hints should be issued for non-constant
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239 strides. */
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240 const bool prefetch_dynamic_strides;
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241 /* The minimum constant stride beyond which we should use prefetch
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242 hints for. */
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243 const int minimum_stride;
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244 const int default_opt_level;
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245 };
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246
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247 struct tune_params
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248 {
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249 const struct cpu_cost_table *insn_extra_cost;
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250 const struct cpu_addrcost_table *addr_cost;
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251 const struct cpu_regmove_cost *regmove_cost;
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252 const struct cpu_vector_cost *vec_costs;
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253 const struct cpu_branch_cost *branch_costs;
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254 const struct cpu_approx_modes *approx_modes;
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145
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255 /* Width of the SVE registers or SVE_NOT_IMPLEMENTED if not applicable.
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256 Only used for tuning decisions, does not disable VLA
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257 vectorization. */
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258 enum aarch64_sve_vector_bits_enum sve_width;
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111
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259 int memmov_cost;
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260 int issue_rate;
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261 unsigned int fusible_ops;
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131
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262 const char *function_align;
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263 const char *jump_align;
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264 const char *loop_align;
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111
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265 int int_reassoc_width;
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266 int fp_reassoc_width;
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267 int vec_reassoc_width;
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268 int min_div_recip_mul_sf;
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269 int min_div_recip_mul_df;
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270 /* Value for aarch64_case_values_threshold; or 0 for the default. */
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271 unsigned int max_case_values;
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272 /* An enum specifying how to take into account CPU autoprefetch capabilities
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273 during instruction scheduling:
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274 - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account.
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275 - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of
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276 offsets but allow the pipeline hazard recognizer to alter that order to
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277 maximize multi-issue opportunities.
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278 - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of
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279 offsets and prefer this even if it restricts multi-issue opportunities. */
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280
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281 enum aarch64_autoprefetch_model
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282 {
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283 AUTOPREFETCHER_OFF,
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284 AUTOPREFETCHER_WEAK,
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285 AUTOPREFETCHER_STRONG
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286 } autoprefetcher_model;
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287
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288 unsigned int extra_tuning_flags;
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289
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290 /* Place prefetch struct pointer at the end to enable type checking
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291 errors when tune_params misses elements (e.g., from erroneous merges). */
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292 const struct cpu_prefetch_tune *prefetch;
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293 };
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294
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131
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295 /* Classifies an address.
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296
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297 ADDRESS_REG_IMM
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298 A simple base register plus immediate offset.
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299
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300 ADDRESS_REG_WB
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301 A base register indexed by immediate offset with writeback.
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302
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303 ADDRESS_REG_REG
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304 A base register indexed by (optionally scaled) register.
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305
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306 ADDRESS_REG_UXTW
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307 A base register indexed by (optionally scaled) zero-extended register.
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308
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309 ADDRESS_REG_SXTW
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310 A base register indexed by (optionally scaled) sign-extended register.
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311
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312 ADDRESS_LO_SUM
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313 A LO_SUM rtx with a base register and "LO12" symbol relocation.
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314
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315 ADDRESS_SYMBOLIC:
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316 A constant symbolic address, in pc-relative literal pool. */
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317
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318 enum aarch64_address_type {
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319 ADDRESS_REG_IMM,
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320 ADDRESS_REG_WB,
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321 ADDRESS_REG_REG,
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322 ADDRESS_REG_UXTW,
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323 ADDRESS_REG_SXTW,
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324 ADDRESS_LO_SUM,
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325 ADDRESS_SYMBOLIC
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326 };
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327
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328 /* Address information. */
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329 struct aarch64_address_info {
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330 enum aarch64_address_type type;
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331 rtx base;
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332 rtx offset;
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333 poly_int64 const_offset;
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334 int shift;
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335 enum aarch64_symbol_type symbol_type;
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336 };
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337
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111
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338 #define AARCH64_FUSION_PAIR(x, name) \
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339 AARCH64_FUSE_##name##_index,
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340 /* Supported fusion operations. */
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341 enum aarch64_fusion_pairs_index
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342 {
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343 #include "aarch64-fusion-pairs.def"
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344 AARCH64_FUSE_index_END
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345 };
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346
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347 #define AARCH64_FUSION_PAIR(x, name) \
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348 AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index),
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349 /* Supported fusion operations. */
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350 enum aarch64_fusion_pairs
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351 {
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352 AARCH64_FUSE_NOTHING = 0,
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353 #include "aarch64-fusion-pairs.def"
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354 AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1
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355 };
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356
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357 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
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358 AARCH64_EXTRA_TUNE_##name##_index,
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359 /* Supported tuning flags indexes. */
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360 enum aarch64_extra_tuning_flags_index
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361 {
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362 #include "aarch64-tuning-flags.def"
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363 AARCH64_EXTRA_TUNE_index_END
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364 };
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365
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366
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367 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
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368 AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
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369 /* Supported tuning flags. */
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370 enum aarch64_extra_tuning_flags
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371 {
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372 AARCH64_EXTRA_TUNE_NONE = 0,
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373 #include "aarch64-tuning-flags.def"
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374 AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
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375 };
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376
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377 /* Enum describing the various ways that the
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378 aarch64_parse_{arch,tune,cpu,extension} functions can fail.
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379 This way their callers can choose what kind of error to give. */
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380
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381 enum aarch64_parse_opt_result
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382 {
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383 AARCH64_PARSE_OK, /* Parsing was successful. */
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384 AARCH64_PARSE_MISSING_ARG, /* Missing argument. */
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385 AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */
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386 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
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387 };
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388
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389 /* Enum to distinguish which type of check is to be done in
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390 aarch64_simd_valid_immediate. This is used as a bitmask where
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391 AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will
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392 perform all checks. Adding new types would require changes accordingly. */
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393 enum simd_immediate_check {
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394 AARCH64_CHECK_ORR = 1 << 0,
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395 AARCH64_CHECK_BIC = 1 << 1,
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396 AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
|
|
|
397 };
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|
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398
|
|
145
|
399 /* The key type that -msign-return-address should use. */
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|
|
400 enum aarch64_key_type {
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|
|
401 AARCH64_KEY_A,
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|
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402 AARCH64_KEY_B
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|
|
403 };
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|
|
404
|
|
|
405 extern enum aarch64_key_type aarch64_ra_sign_key;
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|
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406
|
|
111
|
407 extern struct tune_params aarch64_tune_params;
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|
|
408
|
|
145
|
409 /* The available SVE predicate patterns, known in the ACLE as "svpattern". */
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|
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410 #define AARCH64_FOR_SVPATTERN(T) \
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|
|
411 T (POW2, pow2, 0) \
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|
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412 T (VL1, vl1, 1) \
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|
|
413 T (VL2, vl2, 2) \
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|
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414 T (VL3, vl3, 3) \
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|
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415 T (VL4, vl4, 4) \
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416 T (VL5, vl5, 5) \
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|
|
417 T (VL6, vl6, 6) \
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|
|
418 T (VL7, vl7, 7) \
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|
|
419 T (VL8, vl8, 8) \
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|
|
420 T (VL16, vl16, 9) \
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|
421 T (VL32, vl32, 10) \
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|
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422 T (VL64, vl64, 11) \
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|
|
423 T (VL128, vl128, 12) \
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|
|
424 T (VL256, vl256, 13) \
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425 T (MUL4, mul4, 29) \
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|
|
426 T (MUL3, mul3, 30) \
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|
|
427 T (ALL, all, 31)
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|
|
428
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|
|
429 /* The available SVE prefetch operations, known in the ACLE as "svprfop". */
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|
|
430 #define AARCH64_FOR_SVPRFOP(T) \
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|
|
431 T (PLDL1KEEP, pldl1keep, 0) \
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432 T (PLDL1STRM, pldl1strm, 1) \
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433 T (PLDL2KEEP, pldl2keep, 2) \
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434 T (PLDL2STRM, pldl2strm, 3) \
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|
435 T (PLDL3KEEP, pldl3keep, 4) \
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436 T (PLDL3STRM, pldl3strm, 5) \
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|
|
437 T (PSTL1KEEP, pstl1keep, 8) \
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|
|
438 T (PSTL1STRM, pstl1strm, 9) \
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|
|
439 T (PSTL2KEEP, pstl2keep, 10) \
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|
440 T (PSTL2STRM, pstl2strm, 11) \
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|
441 T (PSTL3KEEP, pstl3keep, 12) \
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|
|
442 T (PSTL3STRM, pstl3strm, 13)
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|
|
443
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|
|
444 #define AARCH64_SVENUM(UPPER, LOWER, VALUE) AARCH64_SV_##UPPER = VALUE,
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|
|
445 enum aarch64_svpattern {
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|
|
446 AARCH64_FOR_SVPATTERN (AARCH64_SVENUM)
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|
|
447 AARCH64_NUM_SVPATTERNS
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|
|
448 };
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|
|
449
|
|
|
450 enum aarch64_svprfop {
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|
|
451 AARCH64_FOR_SVPRFOP (AARCH64_SVENUM)
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|
|
452 AARCH64_NUM_SVPRFOPS
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|
|
453 };
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|
|
454 #undef AARCH64_SVENUM
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|
|
455
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|
|
456 /* It's convenient to divide the built-in function codes into groups,
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|
|
457 rather than having everything in a single enum. This type enumerates
|
|
|
458 those groups. */
|
|
|
459 enum aarch64_builtin_class
|
|
|
460 {
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|
|
461 AARCH64_BUILTIN_GENERAL,
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|
|
462 AARCH64_BUILTIN_SVE
|
|
|
463 };
|
|
|
464
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|
|
465 /* Built-in function codes are structured so that the low
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|
|
466 AARCH64_BUILTIN_SHIFT bits contain the aarch64_builtin_class
|
|
|
467 and the upper bits contain a group-specific subcode. */
|
|
|
468 const unsigned int AARCH64_BUILTIN_SHIFT = 1;
|
|
|
469
|
|
|
470 /* Mask that selects the aarch64_builtin_class part of a function code. */
|
|
|
471 const unsigned int AARCH64_BUILTIN_CLASS = (1 << AARCH64_BUILTIN_SHIFT) - 1;
|
|
|
472
|
|
|
473 void aarch64_post_cfi_startproc (void);
|
|
131
|
474 poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned);
|
|
111
|
475 int aarch64_get_condition_code (rtx);
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|
|
476 bool aarch64_address_valid_for_prefetch_p (rtx, bool);
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|
|
477 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
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|
|
478 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);
|
|
|
479 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);
|
|
|
480 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode);
|
|
|
481 int aarch64_branch_cost (bool, bool);
|
|
|
482 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
|
|
145
|
483 opt_machine_mode aarch64_vq_mode (scalar_mode);
|
|
|
484 opt_machine_mode aarch64_full_sve_mode (scalar_mode);
|
|
111
|
485 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode);
|
|
|
486 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
|
|
131
|
487 bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
|
|
|
488 HOST_WIDE_INT);
|
|
111
|
489 bool aarch64_constant_address_p (rtx);
|
|
|
490 bool aarch64_emit_approx_div (rtx, rtx, rtx);
|
|
|
491 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
|
|
145
|
492 void aarch64_expand_call (rtx, rtx, rtx, bool);
|
|
|
493 bool aarch64_expand_cpymem (rtx *);
|
|
111
|
494 bool aarch64_float_const_zero_rtx_p (rtx);
|
|
|
495 bool aarch64_float_const_rtx_p (rtx);
|
|
|
496 bool aarch64_function_arg_regno_p (unsigned);
|
|
|
497 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
|
|
145
|
498 bool aarch64_gen_cpymemqi (rtx *);
|
|
111
|
499 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx);
|
|
|
500 bool aarch64_is_long_call_p (rtx);
|
|
|
501 bool aarch64_is_noplt_call_p (rtx);
|
|
|
502 bool aarch64_label_mentioned_p (rtx);
|
|
|
503 void aarch64_declare_function_name (FILE *, const char*, tree);
|
|
145
|
504 void aarch64_asm_output_alias (FILE *, const tree, const tree);
|
|
|
505 void aarch64_asm_output_external (FILE *, tree, const char*);
|
|
111
|
506 bool aarch64_legitimate_pic_operand_p (rtx);
|
|
|
507 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx);
|
|
145
|
508 bool aarch64_masks_and_shift_for_bfi_p (scalar_int_mode, unsigned HOST_WIDE_INT,
|
|
|
509 unsigned HOST_WIDE_INT,
|
|
|
510 unsigned HOST_WIDE_INT);
|
|
111
|
511 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
|
|
|
512 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
|
|
145
|
513 machine_mode aarch64_sve_int_mode (machine_mode);
|
|
131
|
514 opt_machine_mode aarch64_sve_pred_mode (unsigned int);
|
|
145
|
515 machine_mode aarch64_sve_pred_mode (machine_mode);
|
|
|
516 opt_machine_mode aarch64_sve_data_mode (scalar_mode, poly_uint64);
|
|
|
517 bool aarch64_sve_mode_p (machine_mode);
|
|
|
518 HOST_WIDE_INT aarch64_fold_sve_cnt_pat (aarch64_svpattern, unsigned int);
|
|
131
|
519 bool aarch64_sve_cnt_immediate_p (rtx);
|
|
145
|
520 bool aarch64_sve_scalar_inc_dec_immediate_p (rtx);
|
|
131
|
521 bool aarch64_sve_addvl_addpl_immediate_p (rtx);
|
|
145
|
522 bool aarch64_sve_vector_inc_dec_immediate_p (rtx);
|
|
131
|
523 int aarch64_add_offset_temporaries (rtx);
|
|
|
524 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
|
|
111
|
525 bool aarch64_mov_operand_p (rtx, machine_mode);
|
|
131
|
526 rtx aarch64_reverse_mask (machine_mode, unsigned int);
|
|
|
527 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64);
|
|
|
528 bool aarch64_offset_9bit_signed_unscaled_p (machine_mode, poly_int64);
|
|
145
|
529 char *aarch64_output_sve_prefetch (const char *, rtx, const char *);
|
|
131
|
530 char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx);
|
|
145
|
531 char *aarch64_output_sve_cnt_pat_immediate (const char *, const char *, rtx *);
|
|
|
532 char *aarch64_output_sve_scalar_inc_dec (rtx);
|
|
|
533 char *aarch64_output_sve_addvl_addpl (rtx);
|
|
|
534 char *aarch64_output_sve_vector_inc_dec (const char *, rtx);
|
|
111
|
535 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
|
|
131
|
536 char *aarch64_output_simd_mov_immediate (rtx, unsigned,
|
|
111
|
537 enum simd_immediate_check w = AARCH64_CHECK_MOV);
|
|
131
|
538 char *aarch64_output_sve_mov_immediate (rtx);
|
|
145
|
539 char *aarch64_output_sve_ptrues (rtx);
|
|
111
|
540 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
|
|
|
541 bool aarch64_regno_ok_for_base_p (int, bool);
|
|
|
542 bool aarch64_regno_ok_for_index_p (int, bool);
|
|
|
543 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail);
|
|
|
544 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
|
|
|
545 bool high);
|
|
|
546 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
|
|
|
547 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
|
|
145
|
548 bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);
|
|
131
|
549 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
|
|
111
|
550 enum simd_immediate_check w = AARCH64_CHECK_MOV);
|
|
131
|
551 rtx aarch64_check_zero_based_sve_index_immediate (rtx);
|
|
|
552 bool aarch64_sve_index_immediate_p (rtx);
|
|
145
|
553 bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);
|
|
|
554 bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);
|
|
131
|
555 bool aarch64_sve_bitmask_immediate_p (rtx);
|
|
|
556 bool aarch64_sve_dup_immediate_p (rtx);
|
|
|
557 bool aarch64_sve_cmp_immediate_p (rtx, bool);
|
|
|
558 bool aarch64_sve_float_arith_immediate_p (rtx, bool);
|
|
|
559 bool aarch64_sve_float_mul_immediate_p (rtx);
|
|
111
|
560 bool aarch64_split_dimode_const_store (rtx, rtx);
|
|
|
561 bool aarch64_symbolic_address_p (rtx);
|
|
|
562 bool aarch64_uimm12_shift (HOST_WIDE_INT);
|
|
145
|
563 int aarch64_movk_shift (const wide_int_ref &, const wide_int_ref &);
|
|
111
|
564 bool aarch64_use_return_insn_p (void);
|
|
|
565 const char *aarch64_output_casesi (rtx *);
|
|
|
566
|
|
145
|
567 unsigned int aarch64_tlsdesc_abi_id ();
|
|
131
|
568 enum aarch64_symbol_type aarch64_classify_symbol (rtx, HOST_WIDE_INT);
|
|
111
|
569 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
|
|
|
570 enum reg_class aarch64_regno_regclass (unsigned);
|
|
|
571 int aarch64_asm_preferred_eh_data_format (int, int);
|
|
|
572 int aarch64_fpconst_pow_of_2 (rtx);
|
|
145
|
573 int aarch64_fpconst_pow2_recip (rtx);
|
|
111
|
574 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
|
|
|
575 machine_mode);
|
|
|
576 int aarch64_uxt_size (int, HOST_WIDE_INT);
|
|
|
577 int aarch64_vec_fpconst_pow_of_2 (rtx);
|
|
|
578 rtx aarch64_eh_return_handler_rtx (void);
|
|
|
579 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
|
|
|
580 const char *aarch64_output_move_struct (rtx *operands);
|
|
|
581 rtx aarch64_return_addr (int, rtx);
|
|
|
582 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
|
|
|
583 bool aarch64_simd_mem_operand_p (rtx);
|
|
131
|
584 bool aarch64_sve_ld1r_operand_p (rtx);
|
|
145
|
585 bool aarch64_sve_ld1rq_operand_p (rtx);
|
|
|
586 bool aarch64_sve_ld1ro_operand_p (rtx, scalar_mode);
|
|
|
587 bool aarch64_sve_ldff1_operand_p (rtx);
|
|
|
588 bool aarch64_sve_ldnf1_operand_p (rtx);
|
|
131
|
589 bool aarch64_sve_ldr_operand_p (rtx);
|
|
145
|
590 bool aarch64_sve_prefetch_operand_p (rtx, machine_mode);
|
|
131
|
591 bool aarch64_sve_struct_memory_operand_p (rtx);
|
|
|
592 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool);
|
|
145
|
593 rtx aarch64_gen_stepped_int_parallel (unsigned int, int, int);
|
|
|
594 bool aarch64_stepped_int_parallel_p (rtx, int);
|
|
111
|
595 rtx aarch64_tls_get_addr (void);
|
|
|
596 unsigned aarch64_dbx_register_number (unsigned);
|
|
|
597 unsigned aarch64_trampoline_size (void);
|
|
|
598 void aarch64_asm_output_labelref (FILE *, const char *);
|
|
|
599 void aarch64_cpu_cpp_builtins (cpp_reader *);
|
|
|
600 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
|
|
|
601 const char * aarch64_output_probe_stack_range (rtx, rtx);
|
|
131
|
602 const char * aarch64_output_probe_sve_stack_clash (rtx, rtx, rtx, rtx);
|
|
|
603 void aarch64_err_no_fpadvsimd (machine_mode);
|
|
111
|
604 void aarch64_expand_epilogue (bool);
|
|
145
|
605 rtx aarch64_ptrue_all (unsigned int);
|
|
|
606 opt_machine_mode aarch64_ptrue_all_mode (rtx);
|
|
|
607 rtx aarch64_convert_sve_data_to_pred (rtx, machine_mode, rtx);
|
|
|
608 rtx aarch64_expand_sve_dupq (rtx, machine_mode, rtx);
|
|
|
609 void aarch64_expand_mov_immediate (rtx, rtx);
|
|
|
610 rtx aarch64_ptrue_reg (machine_mode);
|
|
|
611 rtx aarch64_pfalse_reg (machine_mode);
|
|
|
612 bool aarch64_sve_pred_dominates_p (rtx *, rtx);
|
|
|
613 bool aarch64_sve_same_pred_for_ptest_p (rtx *, rtx *);
|
|
131
|
614 void aarch64_emit_sve_pred_move (rtx, rtx, rtx);
|
|
|
615 void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode);
|
|
|
616 bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx);
|
|
145
|
617 rtx aarch64_replace_reg_mode (rtx, machine_mode);
|
|
131
|
618 void aarch64_split_sve_subreg_move (rtx, rtx, rtx);
|
|
111
|
619 void aarch64_expand_prologue (void);
|
|
|
620 void aarch64_expand_vector_init (rtx, rtx);
|
|
145
|
621 void aarch64_sve_expand_vector_init (rtx, rtx);
|
|
111
|
622 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
|
|
145
|
623 const_tree, unsigned, bool = false);
|
|
111
|
624 void aarch64_init_expanders (void);
|
|
|
625 void aarch64_init_simd_builtins (void);
|
|
|
626 void aarch64_emit_call_insn (rtx);
|
|
|
627 void aarch64_register_pragmas (void);
|
|
|
628 void aarch64_relayout_simd_types (void);
|
|
|
629 void aarch64_reset_previous_fndecl (void);
|
|
|
630 bool aarch64_return_address_signing_enabled (void);
|
|
145
|
631 bool aarch64_bti_enabled (void);
|
|
111
|
632 void aarch64_save_restore_target_globals (tree);
|
|
131
|
633 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
|
|
|
634 rtx *, rtx *,
|
|
|
635 rtx *, rtx *,
|
|
|
636 rtx *);
|
|
|
637 void aarch64_subvti_scratch_regs (rtx, rtx, rtx *,
|
|
|
638 rtx *, rtx *,
|
|
|
639 rtx *, rtx *, rtx *);
|
|
|
640 void aarch64_expand_subvti (rtx, rtx, rtx,
|
|
145
|
641 rtx, rtx, rtx, rtx, bool);
|
|
131
|
642
|
|
111
|
643
|
|
|
644 /* Initialize builtins for SIMD intrinsics. */
|
|
|
645 void init_aarch64_simd_builtins (void);
|
|
|
646
|
|
|
647 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
|
|
|
648
|
|
|
649 /* Expand builtins for SIMD intrinsics. */
|
|
|
650 rtx aarch64_simd_expand_builtin (int, tree, rtx);
|
|
|
651
|
|
|
652 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
|
|
131
|
653 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int);
|
|
111
|
654
|
|
|
655 void aarch64_split_128bit_move (rtx, rtx);
|
|
|
656
|
|
|
657 bool aarch64_split_128bit_move_p (rtx, rtx);
|
|
|
658
|
|
131
|
659 bool aarch64_mov128_immediate (rtx);
|
|
|
660
|
|
111
|
661 void aarch64_split_simd_combine (rtx, rtx, rtx);
|
|
|
662
|
|
|
663 void aarch64_split_simd_move (rtx, rtx);
|
|
|
664
|
|
|
665 /* Check for a legitimate floating point constant for FMOV. */
|
|
|
666 bool aarch64_float_const_representable_p (rtx);
|
|
|
667
|
|
145
|
668 extern int aarch64_epilogue_uses (int);
|
|
|
669
|
|
111
|
670 #if defined (RTX_CODE)
|
|
131
|
671 void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
|
|
|
672 rtx label_ref);
|
|
|
673 bool aarch64_legitimate_address_p (machine_mode, rtx, bool,
|
|
|
674 aarch64_addr_query_type = ADDR_QUERY_M);
|
|
111
|
675 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
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676 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
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677 rtx aarch64_load_tp (rtx);
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678
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679 void aarch64_expand_compare_and_swap (rtx op[]);
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680 void aarch64_split_compare_and_swap (rtx op[]);
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681
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682 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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683
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684 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
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131
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685
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686 void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx);
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687 bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
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688 void aarch64_expand_sve_vcond (machine_mode, machine_mode, rtx *);
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145
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689
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690 bool aarch64_prepare_sve_int_fma (rtx *, rtx_code);
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691 bool aarch64_prepare_sve_cond_int_fma (rtx *, rtx_code);
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111
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692 #endif /* RTX_CODE */
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693
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131
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694 bool aarch64_process_target_attr (tree);
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111
|
695 void aarch64_override_options_internal (struct gcc_options *);
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|
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696
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145
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697 const char *aarch64_general_mangle_builtin_type (const_tree);
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698 void aarch64_general_init_builtins (void);
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699 tree aarch64_general_fold_builtin (unsigned int, tree, unsigned int, tree *);
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700 gimple *aarch64_general_gimple_fold_builtin (unsigned int, gcall *);
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701 rtx aarch64_general_expand_builtin (unsigned int, tree, rtx, int);
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|
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702 tree aarch64_general_builtin_decl (unsigned, bool);
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|
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703 tree aarch64_general_builtin_rsqrt (unsigned int);
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111
|
704 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
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705
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145
|
706 namespace aarch64_sve {
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707 void init_builtins ();
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708 void handle_arm_sve_h ();
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709 tree builtin_decl (unsigned, bool);
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710 bool builtin_type_p (const_tree);
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711 bool builtin_type_p (const_tree, unsigned int *, unsigned int *);
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|
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712 const char *mangle_builtin_type (const_tree);
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713 tree resolve_overloaded_builtin (location_t, unsigned int,
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|
714 vec<tree, va_gc> *);
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715 bool check_builtin_call (location_t, vec<location_t>, unsigned int,
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|
716 tree, unsigned int, tree *);
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|
|
717 gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
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|
|
718 rtx expand_builtin (unsigned int, tree, rtx);
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|
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719 #ifdef GCC_TARGET_H
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720 bool verify_type_context (location_t, type_context_kind, const_tree, bool);
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|
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721 #endif
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|
722 }
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723
|
|
111
|
724 extern void aarch64_split_combinev16qi (rtx operands[3]);
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|
131
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725 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int);
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|
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726 extern void aarch64_expand_sve_vec_perm (rtx, rtx, rtx, rtx);
|
|
111
|
727 extern bool aarch64_madd_needs_nop (rtx_insn *);
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|
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728 extern void aarch64_final_prescan_insn (rtx_insn *);
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|
|
729 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
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|
|
730 int aarch64_ccmp_mode_to_code (machine_mode mode);
|
|
|
731
|
|
|
732 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
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|
|
733 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
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|
|
734 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
|
|
131
|
735 void aarch64_swap_ldrstr_operands (rtx *, bool);
|
|
111
|
736
|
|
|
737 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
|
|
|
738 tree, HOST_WIDE_INT);
|
|
|
739
|
|
131
|
740
|
|
|
741 extern bool aarch64_classify_address (struct aarch64_address_info *, rtx,
|
|
|
742 machine_mode, bool,
|
|
|
743 aarch64_addr_query_type = ADDR_QUERY_M);
|
|
|
744
|
|
111
|
745 /* Defined in common/config/aarch64-common.c. */
|
|
|
746 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *,
|
|
|
747 const struct cl_decoded_option *, location_t);
|
|
|
748 const char *aarch64_rewrite_selected_cpu (const char *name);
|
|
|
749 enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
|
|
145
|
750 uint64_t *,
|
|
|
751 std::string *);
|
|
|
752 void aarch64_get_all_extension_candidates (auto_vec<const char *> *candidates);
|
|
|
753 std::string aarch64_get_extension_string_for_isa_flags (uint64_t, uint64_t);
|
|
|
754
|
|
|
755 /* Defined in aarch64-d.c */
|
|
|
756 extern void aarch64_d_target_versions (void);
|
|
111
|
757
|
|
131
|
758 rtl_opt_pass *make_pass_fma_steering (gcc::context *);
|
|
|
759 rtl_opt_pass *make_pass_track_speculation (gcc::context *);
|
|
|
760 rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *);
|
|
145
|
761 rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt);
|
|
131
|
762
|
|
|
763 poly_uint64 aarch64_regmode_natural_size (machine_mode);
|
|
|
764
|
|
|
765 bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT);
|
|
111
|
766
|
|
145
|
767 struct atomic_ool_names
|
|
|
768 {
|
|
|
769 const char *str[5][4];
|
|
|
770 };
|
|
|
771
|
|
|
772 rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
|
|
|
773 const atomic_ool_names *names);
|
|
|
774 extern const atomic_ool_names aarch64_ool_swp_names;
|
|
|
775 extern const atomic_ool_names aarch64_ool_ldadd_names;
|
|
|
776 extern const atomic_ool_names aarch64_ool_ldset_names;
|
|
|
777 extern const atomic_ool_names aarch64_ool_ldclr_names;
|
|
|
778 extern const atomic_ool_names aarch64_ool_ldeor_names;
|
|
|
779
|
|
|
780 tree aarch64_resolve_overloaded_builtin_general (location_t, tree, void *);
|
|
|
781
|
|
111
|
782 #endif /* GCC_AARCH64_PROTOS_H */
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