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annotate gcc/config/rs6000/power5.md @ 158:494b0b89df80 default tip

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 18:13:55 +0900
parents 1830386684a0
children
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1 ;; Scheduling description for IBM POWER5 processor.
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2 ;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Sources: IBM Red Book and White Paper on POWER5
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21
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22 ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
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23 ;; Instructions that update more than one register get broken into two
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24 ;; (split) or more internal ops. The chip can issue up to 5
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25 ;; internal ops per cycle.
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27 (define_automaton "power5iu,power5fpu,power5misc")
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29 (define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
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30 (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
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31 (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
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32 (define_cpu_unit "bpu_power5,cru_power5" "power5misc")
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33 (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
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34 "power5misc")
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35
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36 (define_reservation "lsq_power5"
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37 "(du1_power5,lsu1_power5)\
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38 |(du2_power5,lsu2_power5)\
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39 |(du3_power5,lsu2_power5)\
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40 |(du4_power5,lsu1_power5)")
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42 (define_reservation "iq_power5"
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43 "(du1_power5|du2_power5|du3_power5|du4_power5),\
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44 (iu1_power5|iu2_power5)")
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46 (define_reservation "fpq_power5"
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47 "(du1_power5|du2_power5|du3_power5|du4_power5),\
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48 (fpu1_power5|fpu2_power5)")
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49
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50 ; Dispatch slots are allocated in order conforming to program order.
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51 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
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52 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
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53 (absence_set "du3_power5" "du4_power5,du5_power5")
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54 (absence_set "du4_power5" "du5_power5")
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57 ; Load/store
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58 (define_insn_reservation "power5-load" 4 ; 3
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59 (and (eq_attr "type" "load")
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60 (eq_attr "sign_extend" "no")
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61 (eq_attr "update" "no")
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62 (eq_attr "cpu" "power5"))
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63 "lsq_power5")
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65 (define_insn_reservation "power5-load-ext" 5
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66 (and (eq_attr "type" "load")
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67 (eq_attr "sign_extend" "yes")
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68 (eq_attr "update" "no")
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69 (eq_attr "cpu" "power5"))
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70 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
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72 (define_insn_reservation "power5-load-ext-update" 5
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73 (and (eq_attr "type" "load")
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74 (eq_attr "sign_extend" "yes")
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75 (eq_attr "update" "yes")
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76 (eq_attr "indexed" "no")
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77 (eq_attr "cpu" "power5"))
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78 "du1_power5+du2_power5+du3_power5+du4_power5,\
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79 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
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80
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81 (define_insn_reservation "power5-load-ext-update-indexed" 5
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82 (and (eq_attr "type" "load")
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83 (eq_attr "sign_extend" "yes")
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84 (eq_attr "update" "yes")
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85 (eq_attr "indexed" "yes")
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86 (eq_attr "cpu" "power5"))
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87 "du1_power5+du2_power5+du3_power5+du4_power5,\
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88 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
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89
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90 (define_insn_reservation "power5-load-update-indexed" 3
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91 (and (eq_attr "type" "load")
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92 (eq_attr "sign_extend" "no")
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93 (eq_attr "update" "yes")
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94 (eq_attr "indexed" "yes")
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95 (eq_attr "cpu" "power5"))
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96 "du1_power5+du2_power5+du3_power5+du4_power5,\
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97 iu1_power5,lsu2_power5+iu2_power5")
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98
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99 (define_insn_reservation "power5-load-update" 4 ; 3
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100 (and (eq_attr "type" "load")
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101 (eq_attr "sign_extend" "no")
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102 (eq_attr "update" "yes")
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103 (eq_attr "indexed" "no")
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104 (eq_attr "cpu" "power5"))
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105 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
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106
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107 (define_insn_reservation "power5-fpload" 6 ; 5
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108 (and (eq_attr "type" "fpload")
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109 (eq_attr "update" "no")
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110 (eq_attr "cpu" "power5"))
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111 "lsq_power5")
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112
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113 (define_insn_reservation "power5-fpload-update" 6 ; 5
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114 (and (eq_attr "type" "fpload")
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115 (eq_attr "update" "yes")
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116 (eq_attr "cpu" "power5"))
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117 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
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118
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119 (define_insn_reservation "power5-store" 12
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120 (and (eq_attr "type" "store")
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121 (eq_attr "update" "no")
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122 (eq_attr "cpu" "power5"))
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123 "((du1_power5,lsu1_power5)\
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124 |(du2_power5,lsu2_power5)\
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125 |(du3_power5,lsu2_power5)\
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126 |(du4_power5,lsu1_power5)),\
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127 (iu1_power5|iu2_power5)")
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128
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129 (define_insn_reservation "power5-store-update" 12
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130 (and (eq_attr "type" "store")
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131 (eq_attr "update" "yes")
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132 (eq_attr "indexed" "no")
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133 (eq_attr "cpu" "power5"))
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134 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
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135
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136 (define_insn_reservation "power5-store-update-indexed" 12
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137 (and (eq_attr "type" "store")
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138 (eq_attr "update" "yes")
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139 (eq_attr "indexed" "yes")
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140 (eq_attr "cpu" "power5"))
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141 "du1_power5+du2_power5+du3_power5+du4_power5,\
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142 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
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143
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144 (define_insn_reservation "power5-fpstore" 12
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145 (and (eq_attr "type" "fpstore")
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146 (eq_attr "update" "no")
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147 (eq_attr "cpu" "power5"))
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148 "((du1_power5,lsu1_power5)\
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149 |(du2_power5,lsu2_power5)\
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150 |(du3_power5,lsu2_power5)\
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151 |(du4_power5,lsu1_power5)),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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152 (fpu1_power5|fpu2_power5)")
0
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153
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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154 (define_insn_reservation "power5-fpstore-update" 12
111
kono
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155 (and (eq_attr "type" "fpstore")
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156 (eq_attr "update" "yes")
0
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157 (eq_attr "cpu" "power5"))
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158 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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159
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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160 (define_insn_reservation "power5-llsc" 11
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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161 (and (eq_attr "type" "load_l,store_c,sync")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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162 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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163 "du1_power5+du2_power5+du3_power5+du4_power5,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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164 lsu1_power5")
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165
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166
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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167 ; Integer latency is 2 cycles
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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168 (define_insn_reservation "power5-integer" 2
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kono
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169 (and (ior (eq_attr "type" "integer,trap,cntlz,isel,popcnt")
kono
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170 (and (eq_attr "type" "add,logical,shift,exts")
kono
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171 (eq_attr "dot" "no"))
kono
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172 (and (eq_attr "type" "insert")
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173 (eq_attr "size" "64")))
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174 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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175 "iq_power5")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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176
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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177 (define_insn_reservation "power5-two" 2
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178 (and (eq_attr "type" "two")
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179 (eq_attr "cpu" "power5"))
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180 "((du1_power5+du2_power5)\
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181 |(du2_power5+du3_power5)\
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182 |(du3_power5+du4_power5)\
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183 |(du4_power5+du1_power5)),\
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184 ((iu1_power5,nothing,iu2_power5)\
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185 |(iu2_power5,nothing,iu2_power5)\
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186 |(iu2_power5,nothing,iu1_power5)\
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187 |(iu1_power5,nothing,iu1_power5))")
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188
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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189 (define_insn_reservation "power5-three" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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190 (and (eq_attr "type" "three")
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191 (eq_attr "cpu" "power5"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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192 "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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193 |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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diff changeset
194 ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
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195 |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
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196 |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
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197 |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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198
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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199 (define_insn_reservation "power5-insert" 4
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kono
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200 (and (eq_attr "type" "insert")
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201 (eq_attr "size" "32")
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202 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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203 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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204
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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205 (define_insn_reservation "power5-cmp" 3
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206 (and (ior (eq_attr "type" "cmp")
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207 (and (eq_attr "type" "add,logical")
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208 (eq_attr "dot" "yes")))
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209 (eq_attr "cpu" "power5"))
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210 "iq_power5")
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211
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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212 (define_insn_reservation "power5-compare" 2
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213 (and (eq_attr "type" "shift,exts")
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214 (eq_attr "dot" "yes")
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215 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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216 "du1_power5+du2_power5,iu1_power5,iu2_power5")
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217
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218 (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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219
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220 (define_insn_reservation "power5-lmul-cmp" 7
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221 (and (eq_attr "type" "mul")
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222 (eq_attr "dot" "yes")
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223 (eq_attr "size" "64")
0
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224 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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225 "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
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226
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227 (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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228
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229 (define_insn_reservation "power5-imul-cmp" 5
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230 (and (eq_attr "type" "mul")
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231 (eq_attr "dot" "yes")
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232 (eq_attr "size" "32")
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233 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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234 "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
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235
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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236 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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237
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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238 (define_insn_reservation "power5-lmul" 7
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239 (and (eq_attr "type" "mul")
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240 (eq_attr "dot" "no")
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241 (eq_attr "size" "64")
0
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242 (eq_attr "cpu" "power5"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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diff changeset
243 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
0
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244
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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245 (define_insn_reservation "power5-imul" 5
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246 (and (eq_attr "type" "mul")
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247 (eq_attr "dot" "no")
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248 (eq_attr "size" "32")
0
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249 (eq_attr "cpu" "power5"))
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diff changeset
250 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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251
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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252 (define_insn_reservation "power5-imul3" 4
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253 (and (eq_attr "type" "mul")
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254 (eq_attr "size" "8,16")
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255 (eq_attr "cpu" "power5"))
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diff changeset
256 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
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257
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258
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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259 ; SPR move only executes in first IU.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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260 ; Integer division only executes in second IU.
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261 (define_insn_reservation "power5-idiv" 36
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262 (and (eq_attr "type" "div")
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263 (eq_attr "size" "32")
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264 (eq_attr "cpu" "power5"))
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265 "du1_power5+du2_power5,iu2_power5*35")
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266
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267 (define_insn_reservation "power5-ldiv" 68
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268 (and (eq_attr "type" "div")
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269 (eq_attr "size" "64")
0
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270 (eq_attr "cpu" "power5"))
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271 "du1_power5+du2_power5,iu2_power5*67")
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272
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273
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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274 (define_insn_reservation "power5-mtjmpr" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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275 (and (eq_attr "type" "mtjmpr,mfjmpr")
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276 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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277 "du1_power5,bpu_power5")
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278
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279
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280 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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281 ; grabbing previous dispatch slots once this is assigned.
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282 (define_insn_reservation "power5-branch" 2
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283 (and (eq_attr "type" "jmpreg,branch")
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284 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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285 "(du5_power5\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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286 |du4_power5+du5_power5\
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287 |du3_power5+du4_power5+du5_power5\
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288 |du2_power5+du3_power5+du4_power5+du5_power5\
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289 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
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290
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291
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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292 ; Condition Register logical ops are split if non-destructive (RT != RB)
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293 (define_insn_reservation "power5-crlogical" 2
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294 (and (eq_attr "type" "cr_logical")
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84e7813d76e9 gcc-8.2
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295 (eq_attr "cr_logical_3op" "no")
0
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296 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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297 "du1_power5,cru_power5")
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298
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299 (define_insn_reservation "power5-delayedcr" 4
131
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300 (and (eq_attr "type" "cr_logical")
84e7813d76e9 gcc-8.2
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301 (eq_attr "cr_logical_3op" "yes")
0
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302 (eq_attr "cpu" "power5"))
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303 "du1_power5+du2_power5,cru_power5,cru_power5")
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304
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305 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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306 (define_insn_reservation "power5-mfcr" 6
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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307 (and (eq_attr "type" "mfcr")
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308 (eq_attr "cpu" "power5"))
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309 "du1_power5+du2_power5+du3_power5+du4_power5,\
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310 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
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311 cru_power5,cru_power5,cru_power5")
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312
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313 ; mfcrf (1 field)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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314 (define_insn_reservation "power5-mfcrf" 3
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315 (and (eq_attr "type" "mfcrf")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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316 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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317 "du1_power5,cru_power5")
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318
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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319 ; mtcrf (1 field)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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320 (define_insn_reservation "power5-mtcr" 4
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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321 (and (eq_attr "type" "mtcr")
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322 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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323 "du1_power5,iu1_power5")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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324
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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325 ; Basic FP latency is 6 cycles
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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326 (define_insn_reservation "power5-fp" 6
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kono
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327 (and (eq_attr "type" "fp,fpsimple,dmul")
0
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328 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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329 "fpq_power5")
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330
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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331 (define_insn_reservation "power5-fpcompare" 5
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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332 (and (eq_attr "type" "fpcompare")
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333 (eq_attr "cpu" "power5"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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334 "fpq_power5")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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335
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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336 (define_insn_reservation "power5-sdiv" 33
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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337 (and (eq_attr "type" "sdiv,ddiv")
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338 (eq_attr "cpu" "power5"))
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77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
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339 "(du1_power5|du2_power5|du3_power5|du4_power5),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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340 (fpu1_power5*28|fpu2_power5*28)")
0
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341
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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342 (define_insn_reservation "power5-sqrt" 40
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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343 (and (eq_attr "type" "ssqrt,dsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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344 (eq_attr "cpu" "power5"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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345 "(du1_power5|du2_power5|du3_power5|du4_power5),\
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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346 (fpu1_power5*35|fpu2_power5*35)")
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347
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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348 (define_insn_reservation "power5-isync" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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349 (and (eq_attr "type" "isync")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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350 (eq_attr "cpu" "power5"))
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351 "du1_power5+du2_power5+du3_power5+du4_power5,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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352 lsu1_power5")
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353