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comparison gcc/config/aarch64/constraints.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 (define_register_constraint "k" "STACK_REG"
22 "@internal The stack register.")
23
24 (define_register_constraint "Ucs" "CALLER_SAVE_REGS"
25 "@internal The caller save registers.")
26
27 (define_register_constraint "w" "FP_REGS"
28 "Floating point and SIMD vector registers.")
29
30 (define_register_constraint "x" "FP_LO_REGS"
31 "Floating point and SIMD vector registers V0 - V15.")
32
33 (define_constraint "I"
34 "A constant that can be used with an ADD operation."
35 (and (match_code "const_int")
36 (match_test "aarch64_uimm12_shift (ival)")))
37
38 (define_constraint "Upl"
39 "@internal A constant that matches two uses of add instructions."
40 (and (match_code "const_int")
41 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
42
43 (define_constraint "J"
44 "A constant that can be used with a SUB operation (once negated)."
45 (and (match_code "const_int")
46 (match_test "aarch64_uimm12_shift (-ival)")))
47
48 ;; We can't use the mode of a CONST_INT to determine the context in
49 ;; which it is being used, so we must have a separate constraint for
50 ;; each context.
51
52 (define_constraint "K"
53 "A constant that can be used with a 32-bit logical operation."
54 (and (match_code "const_int")
55 (match_test "aarch64_bitmask_imm (ival, SImode)")))
56
57 (define_constraint "L"
58 "A constant that can be used with a 64-bit logical operation."
59 (and (match_code "const_int")
60 (match_test "aarch64_bitmask_imm (ival, DImode)")))
61
62 (define_constraint "M"
63 "A constant that can be used with a 32-bit MOV immediate operation."
64 (and (match_code "const_int")
65 (match_test "aarch64_move_imm (ival, SImode)")))
66
67 (define_constraint "N"
68 "A constant that can be used with a 64-bit MOV immediate operation."
69 (and (match_code "const_int")
70 (match_test "aarch64_move_imm (ival, DImode)")))
71
72 (define_constraint "UsO"
73 "A constant that can be used with a 32-bit and operation."
74 (and (match_code "const_int")
75 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
76
77 (define_constraint "UsP"
78 "A constant that can be used with a 64-bit and operation."
79 (and (match_code "const_int")
80 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
81
82 (define_constraint "S"
83 "A constraint that matches an absolute symbolic address."
84 (and (match_code "const,symbol_ref,label_ref")
85 (match_test "aarch64_symbolic_address_p (op)")))
86
87 (define_constraint "Y"
88 "Floating point constant zero."
89 (and (match_code "const_double")
90 (match_test "aarch64_float_const_zero_rtx_p (op)")))
91
92 (define_constraint "Z"
93 "Integer constant zero."
94 (match_test "op == const0_rtx"))
95
96 (define_constraint "Ush"
97 "A constraint that matches an absolute symbolic address high part."
98 (and (match_code "high")
99 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
100
101 (define_constraint "Usa"
102 "@internal
103 A constraint that matches an absolute symbolic address that can be
104 loaded by a single ADR."
105 (and (match_code "const,symbol_ref,label_ref")
106 (match_test "aarch64_symbolic_address_p (op)")
107 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
108
109 (define_constraint "Uss"
110 "@internal
111 A constraint that matches an immediate shift constant in SImode."
112 (and (match_code "const_int")
113 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
114
115 (define_constraint "Usn"
116 "A constant that can be used with a CCMN operation (once negated)."
117 (and (match_code "const_int")
118 (match_test "IN_RANGE (ival, -31, 0)")))
119
120 (define_constraint "Usd"
121 "@internal
122 A constraint that matches an immediate shift constant in DImode."
123 (and (match_code "const_int")
124 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
125
126 (define_constraint "Usf"
127 "@internal Usf is a symbol reference under the context where plt stub allowed."
128 (and (match_code "symbol_ref")
129 (match_test "!(aarch64_is_noplt_call_p (op)
130 || aarch64_is_long_call_p (op))")))
131
132 (define_constraint "UsM"
133 "@internal
134 A constraint that matches the immediate constant -1."
135 (match_test "op == constm1_rtx"))
136
137 (define_constraint "Ui1"
138 "@internal
139 A constraint that matches the immediate constant +1."
140 (match_test "op == const1_rtx"))
141
142 (define_constraint "Ui3"
143 "@internal
144 A constraint that matches the integers 0...4."
145 (and (match_code "const_int")
146 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
147
148 (define_constraint "Up3"
149 "@internal
150 A constraint that matches the integers 2^(0...4)."
151 (and (match_code "const_int")
152 (match_test "(unsigned) exact_log2 (ival) <= 4")))
153
154 (define_memory_constraint "Q"
155 "A memory address which uses a single base register with no offset."
156 (and (match_code "mem")
157 (match_test "REG_P (XEXP (op, 0))")))
158
159 (define_memory_constraint "Umq"
160 "@internal
161 A memory address which uses a base register with an offset small enough for
162 a load/store pair operation in DI mode."
163 (and (match_code "mem")
164 (match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0),
165 PARALLEL, false)")))
166
167 (define_memory_constraint "Ump"
168 "@internal
169 A memory address suitable for a load/store pair operation."
170 (and (match_code "mem")
171 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
172 PARALLEL, 1)")))
173
174 (define_memory_constraint "Utv"
175 "@internal
176 An address valid for loading/storing opaque structure
177 types wider than TImode."
178 (and (match_code "mem")
179 (match_test "aarch64_simd_mem_operand_p (op)")))
180
181 (define_constraint "Ufc"
182 "A floating point constant which can be used with an\
183 FMOV immediate operation."
184 (and (match_code "const_double")
185 (match_test "aarch64_float_const_representable_p (op)")))
186
187 (define_constraint "Uvi"
188 "A floating point constant which can be used with a\
189 MOVI immediate operation."
190 (and (match_code "const_double")
191 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
192
193 (define_constraint "Do"
194 "@internal
195 A constraint that matches vector of immediates for orr."
196 (and (match_code "const_vector")
197 (match_test "aarch64_simd_valid_immediate (op, mode, false,
198 NULL, AARCH64_CHECK_ORR)")))
199
200 (define_constraint "Db"
201 "@internal
202 A constraint that matches vector of immediates for bic."
203 (and (match_code "const_vector")
204 (match_test "aarch64_simd_valid_immediate (op, mode, false,
205 NULL, AARCH64_CHECK_BIC)")))
206
207 (define_constraint "Dn"
208 "@internal
209 A constraint that matches vector of immediates."
210 (and (match_code "const_vector")
211 (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op),
212 false, NULL)")))
213
214 (define_constraint "Dh"
215 "@internal
216 A constraint that matches an immediate operand valid for\
217 AdvSIMD scalar move in HImode."
218 (and (match_code "const_int")
219 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
220 HImode)")))
221
222 (define_constraint "Dq"
223 "@internal
224 A constraint that matches an immediate operand valid for\
225 AdvSIMD scalar move in QImode."
226 (and (match_code "const_int")
227 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
228 QImode)")))
229
230 (define_constraint "Dl"
231 "@internal
232 A constraint that matches vector of immediates for left shifts."
233 (and (match_code "const_vector")
234 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
235 true)")))
236
237 (define_constraint "Dr"
238 "@internal
239 A constraint that matches vector of immediates for right shifts."
240 (and (match_code "const_vector")
241 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
242 false)")))
243 (define_constraint "Dz"
244 "@internal
245 A constraint that matches vector of immediate zero."
246 (and (match_code "const_vector")
247 (match_test "aarch64_simd_imm_zero_p (op, GET_MODE (op))")))
248
249 (define_constraint "Dd"
250 "@internal
251 A constraint that matches an integer immediate operand valid\
252 for AdvSIMD scalar operations in DImode."
253 (and (match_code "const_int")
254 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
255
256 (define_constraint "Ds"
257 "@internal
258 A constraint that matches an integer immediate operand valid\
259 for AdvSIMD scalar operations in SImode."
260 (and (match_code "const_int")
261 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
262
263 (define_address_constraint "Dp"
264 "@internal
265 An address valid for a prefetch instruction."
266 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))