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111
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1 ;; Machine description for AArch64 architecture.
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2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_register_constraint "k" "STACK_REG"
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22 "@internal The stack register.")
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23
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24 (define_register_constraint "Ucs" "CALLER_SAVE_REGS"
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25 "@internal The caller save registers.")
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26
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27 (define_register_constraint "w" "FP_REGS"
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28 "Floating point and SIMD vector registers.")
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29
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30 (define_register_constraint "x" "FP_LO_REGS"
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31 "Floating point and SIMD vector registers V0 - V15.")
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32
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33 (define_constraint "I"
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34 "A constant that can be used with an ADD operation."
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35 (and (match_code "const_int")
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36 (match_test "aarch64_uimm12_shift (ival)")))
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37
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38 (define_constraint "Upl"
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39 "@internal A constant that matches two uses of add instructions."
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40 (and (match_code "const_int")
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41 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
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42
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43 (define_constraint "J"
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44 "A constant that can be used with a SUB operation (once negated)."
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45 (and (match_code "const_int")
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46 (match_test "aarch64_uimm12_shift (-ival)")))
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47
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48 ;; We can't use the mode of a CONST_INT to determine the context in
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49 ;; which it is being used, so we must have a separate constraint for
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50 ;; each context.
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51
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52 (define_constraint "K"
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53 "A constant that can be used with a 32-bit logical operation."
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54 (and (match_code "const_int")
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55 (match_test "aarch64_bitmask_imm (ival, SImode)")))
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56
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57 (define_constraint "L"
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58 "A constant that can be used with a 64-bit logical operation."
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59 (and (match_code "const_int")
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60 (match_test "aarch64_bitmask_imm (ival, DImode)")))
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61
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62 (define_constraint "M"
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63 "A constant that can be used with a 32-bit MOV immediate operation."
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64 (and (match_code "const_int")
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65 (match_test "aarch64_move_imm (ival, SImode)")))
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66
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67 (define_constraint "N"
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68 "A constant that can be used with a 64-bit MOV immediate operation."
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69 (and (match_code "const_int")
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70 (match_test "aarch64_move_imm (ival, DImode)")))
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71
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72 (define_constraint "UsO"
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73 "A constant that can be used with a 32-bit and operation."
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74 (and (match_code "const_int")
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75 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
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76
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77 (define_constraint "UsP"
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78 "A constant that can be used with a 64-bit and operation."
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79 (and (match_code "const_int")
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80 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
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81
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82 (define_constraint "S"
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83 "A constraint that matches an absolute symbolic address."
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84 (and (match_code "const,symbol_ref,label_ref")
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85 (match_test "aarch64_symbolic_address_p (op)")))
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86
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87 (define_constraint "Y"
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88 "Floating point constant zero."
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89 (and (match_code "const_double")
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90 (match_test "aarch64_float_const_zero_rtx_p (op)")))
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91
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92 (define_constraint "Z"
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93 "Integer constant zero."
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94 (match_test "op == const0_rtx"))
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95
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96 (define_constraint "Ush"
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97 "A constraint that matches an absolute symbolic address high part."
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98 (and (match_code "high")
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99 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
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100
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101 (define_constraint "Usa"
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102 "@internal
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103 A constraint that matches an absolute symbolic address that can be
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104 loaded by a single ADR."
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105 (and (match_code "const,symbol_ref,label_ref")
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106 (match_test "aarch64_symbolic_address_p (op)")
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107 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
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108
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109 (define_constraint "Uss"
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110 "@internal
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111 A constraint that matches an immediate shift constant in SImode."
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112 (and (match_code "const_int")
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113 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
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114
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115 (define_constraint "Usn"
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116 "A constant that can be used with a CCMN operation (once negated)."
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117 (and (match_code "const_int")
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118 (match_test "IN_RANGE (ival, -31, 0)")))
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119
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120 (define_constraint "Usd"
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121 "@internal
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122 A constraint that matches an immediate shift constant in DImode."
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123 (and (match_code "const_int")
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124 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
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125
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126 (define_constraint "Usf"
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127 "@internal Usf is a symbol reference under the context where plt stub allowed."
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128 (and (match_code "symbol_ref")
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129 (match_test "!(aarch64_is_noplt_call_p (op)
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130 || aarch64_is_long_call_p (op))")))
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131
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132 (define_constraint "UsM"
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133 "@internal
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134 A constraint that matches the immediate constant -1."
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135 (match_test "op == constm1_rtx"))
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136
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137 (define_constraint "Ui1"
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138 "@internal
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139 A constraint that matches the immediate constant +1."
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140 (match_test "op == const1_rtx"))
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141
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142 (define_constraint "Ui3"
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143 "@internal
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144 A constraint that matches the integers 0...4."
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145 (and (match_code "const_int")
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146 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
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147
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148 (define_constraint "Up3"
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149 "@internal
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150 A constraint that matches the integers 2^(0...4)."
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151 (and (match_code "const_int")
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152 (match_test "(unsigned) exact_log2 (ival) <= 4")))
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153
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154 (define_memory_constraint "Q"
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155 "A memory address which uses a single base register with no offset."
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156 (and (match_code "mem")
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157 (match_test "REG_P (XEXP (op, 0))")))
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158
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159 (define_memory_constraint "Umq"
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160 "@internal
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161 A memory address which uses a base register with an offset small enough for
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162 a load/store pair operation in DI mode."
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163 (and (match_code "mem")
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164 (match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0),
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165 PARALLEL, false)")))
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166
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167 (define_memory_constraint "Ump"
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168 "@internal
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169 A memory address suitable for a load/store pair operation."
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170 (and (match_code "mem")
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171 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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172 PARALLEL, 1)")))
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173
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174 (define_memory_constraint "Utv"
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175 "@internal
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176 An address valid for loading/storing opaque structure
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177 types wider than TImode."
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178 (and (match_code "mem")
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179 (match_test "aarch64_simd_mem_operand_p (op)")))
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180
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181 (define_constraint "Ufc"
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182 "A floating point constant which can be used with an\
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183 FMOV immediate operation."
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184 (and (match_code "const_double")
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185 (match_test "aarch64_float_const_representable_p (op)")))
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186
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187 (define_constraint "Uvi"
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188 "A floating point constant which can be used with a\
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189 MOVI immediate operation."
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190 (and (match_code "const_double")
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191 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
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192
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193 (define_constraint "Do"
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194 "@internal
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195 A constraint that matches vector of immediates for orr."
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196 (and (match_code "const_vector")
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197 (match_test "aarch64_simd_valid_immediate (op, mode, false,
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198 NULL, AARCH64_CHECK_ORR)")))
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199
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200 (define_constraint "Db"
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201 "@internal
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202 A constraint that matches vector of immediates for bic."
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203 (and (match_code "const_vector")
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204 (match_test "aarch64_simd_valid_immediate (op, mode, false,
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205 NULL, AARCH64_CHECK_BIC)")))
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206
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207 (define_constraint "Dn"
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208 "@internal
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209 A constraint that matches vector of immediates."
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210 (and (match_code "const_vector")
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211 (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op),
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212 false, NULL)")))
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213
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214 (define_constraint "Dh"
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215 "@internal
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216 A constraint that matches an immediate operand valid for\
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217 AdvSIMD scalar move in HImode."
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218 (and (match_code "const_int")
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219 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
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220 HImode)")))
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221
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222 (define_constraint "Dq"
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223 "@internal
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224 A constraint that matches an immediate operand valid for\
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225 AdvSIMD scalar move in QImode."
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226 (and (match_code "const_int")
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227 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
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228 QImode)")))
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229
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230 (define_constraint "Dl"
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231 "@internal
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232 A constraint that matches vector of immediates for left shifts."
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233 (and (match_code "const_vector")
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234 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
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235 true)")))
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236
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237 (define_constraint "Dr"
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238 "@internal
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239 A constraint that matches vector of immediates for right shifts."
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240 (and (match_code "const_vector")
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241 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
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242 false)")))
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243 (define_constraint "Dz"
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244 "@internal
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245 A constraint that matches vector of immediate zero."
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246 (and (match_code "const_vector")
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247 (match_test "aarch64_simd_imm_zero_p (op, GET_MODE (op))")))
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248
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249 (define_constraint "Dd"
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250 "@internal
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251 A constraint that matches an integer immediate operand valid\
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252 for AdvSIMD scalar operations in DImode."
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253 (and (match_code "const_int")
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254 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
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255
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256 (define_constraint "Ds"
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257 "@internal
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258 A constraint that matches an integer immediate operand valid\
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259 for AdvSIMD scalar operations in SImode."
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260 (and (match_code "const_int")
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261 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
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262
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263 (define_address_constraint "Dp"
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264 "@internal
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265 An address valid for a prefetch instruction."
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266 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
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