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comparison gcc/config/arm/arm-generic.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Generic ARM Pipeline Description 1 ;; Generic ARM Pipeline Description
2 ;; Copyright (C) 2003, 2007, 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by 7 ;; under the terms of the GNU General Public License as published by
36 36
37 ;; Write blockage unit 37 ;; Write blockage unit
38 ; 38 ;
39 ; The write_blockage unit models (partially), the fact that reads will stall 39 ; The write_blockage unit models (partially), the fact that reads will stall
40 ; until the write buffer empties. 40 ; until the write buffer empties.
41 ; The f_mem_r and r_mem_f could also block, but they are to the stack,
42 ; so we don't model them here
43 (define_cpu_unit "write_blockage" "arm") 41 (define_cpu_unit "write_blockage" "arm")
44 42
45 ;; Core 43 ;; Core
46 ; 44 ;
47 (define_cpu_unit "core" "arm") 45 (define_cpu_unit "core" "arm")
48 46
49 (define_insn_reservation "r_mem_f_wbuf" 5
50 (and (eq_attr "generic_sched" "yes")
51 (and (eq_attr "model_wbuf" "yes")
52 (eq_attr "type" "r_mem_f")))
53 "core+write_buf*3")
54
55 (define_insn_reservation "store_wbuf" 5 47 (define_insn_reservation "store_wbuf" 5
56 (and (eq_attr "generic_sched" "yes") 48 (and (eq_attr "generic_sched" "yes")
57 (and (eq_attr "model_wbuf" "yes") 49 (and (eq_attr "model_wbuf" "yes")
58 (eq_attr "type" "store1"))) 50 (eq_attr "type" "store_4")))
59 "core+write_buf*3+write_blockage*5") 51 "core+write_buf*3+write_blockage*5")
60 52
61 (define_insn_reservation "store2_wbuf" 7 53 (define_insn_reservation "store2_wbuf" 7
62 (and (eq_attr "generic_sched" "yes") 54 (and (eq_attr "generic_sched" "yes")
63 (and (eq_attr "model_wbuf" "yes") 55 (and (eq_attr "model_wbuf" "yes")
64 (eq_attr "type" "store2"))) 56 (eq_attr "type" "store_8")))
65 "core+write_buf*4+write_blockage*7") 57 "core+write_buf*4+write_blockage*7")
66 58
67 (define_insn_reservation "store3_wbuf" 9 59 (define_insn_reservation "store3_wbuf" 9
68 (and (eq_attr "generic_sched" "yes") 60 (and (eq_attr "generic_sched" "yes")
69 (and (eq_attr "model_wbuf" "yes") 61 (and (eq_attr "model_wbuf" "yes")
70 (eq_attr "type" "store3"))) 62 (eq_attr "type" "store_12")))
71 "core+write_buf*5+write_blockage*9") 63 "core+write_buf*5+write_blockage*9")
72 64
73 (define_insn_reservation "store4_wbuf" 11 65 (define_insn_reservation "store4_wbuf" 11
74 (and (eq_attr "generic_sched" "yes") 66 (and (eq_attr "generic_sched" "yes")
75 (and (eq_attr "model_wbuf" "yes") 67 (and (eq_attr "model_wbuf" "yes")
76 (eq_attr "type" "store4"))) 68 (eq_attr "type" "store_16")))
77 "core+write_buf*6+write_blockage*11") 69 "core+write_buf*6+write_blockage*11")
78 70
79 (define_insn_reservation "store2" 3 71 (define_insn_reservation "store2" 3
80 (and (eq_attr "generic_sched" "yes") 72 (and (eq_attr "generic_sched" "yes")
81 (and (eq_attr "model_wbuf" "no") 73 (and (eq_attr "model_wbuf" "no")
82 (eq_attr "type" "store2"))) 74 (eq_attr "type" "store_8")))
83 "core*3") 75 "core*3")
84 76
85 (define_insn_reservation "store3" 4 77 (define_insn_reservation "store3" 4
86 (and (eq_attr "generic_sched" "yes") 78 (and (eq_attr "generic_sched" "yes")
87 (and (eq_attr "model_wbuf" "no") 79 (and (eq_attr "model_wbuf" "no")
88 (eq_attr "type" "store3"))) 80 (eq_attr "type" "store_12")))
89 "core*4") 81 "core*4")
90 82
91 (define_insn_reservation "store4" 5 83 (define_insn_reservation "store4" 5
92 (and (eq_attr "generic_sched" "yes") 84 (and (eq_attr "generic_sched" "yes")
93 (and (eq_attr "model_wbuf" "no") 85 (and (eq_attr "model_wbuf" "no")
94 (eq_attr "type" "store4"))) 86 (eq_attr "type" "store_16")))
95 "core*5") 87 "core*5")
96 88
97 (define_insn_reservation "store_ldsched" 1 89 (define_insn_reservation "store_ldsched" 1
98 (and (eq_attr "generic_sched" "yes") 90 (and (eq_attr "generic_sched" "yes")
99 (and (eq_attr "ldsched" "yes") 91 (and (eq_attr "ldsched" "yes")
100 (eq_attr "type" "store1"))) 92 (eq_attr "type" "store_4")))
101 "core") 93 "core")
102 94
103 (define_insn_reservation "load_ldsched_xscale" 3 95 (define_insn_reservation "load_ldsched_xscale" 3
104 (and (eq_attr "generic_sched" "yes") 96 (and (eq_attr "generic_sched" "yes")
105 (and (eq_attr "ldsched" "yes") 97 (and (eq_attr "ldsched" "yes")
106 (and (eq_attr "type" "load_byte,load1") 98 (and (eq_attr "type" "load_byte,load_4")
107 (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) 99 (eq_attr "tune" "xscale,iwmmxt,iwmmxt2"))))
108 "core") 100 "core")
109 101
110 (define_insn_reservation "load_ldsched" 2 102 (define_insn_reservation "load_ldsched" 2
111 (and (eq_attr "generic_sched" "yes") 103 (and (eq_attr "generic_sched" "yes")
112 (and (eq_attr "ldsched" "yes") 104 (and (eq_attr "ldsched" "yes")
113 (and (eq_attr "type" "load_byte,load1") 105 (and (eq_attr "type" "load_byte,load_4")
114 (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) 106 (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"))))
115 "core") 107 "core")
116 108
117 (define_insn_reservation "load_or_store" 2 109 (define_insn_reservation "load_or_store" 2
118 (and (eq_attr "generic_sched" "yes") 110 (and (eq_attr "generic_sched" "yes")
119 (and (eq_attr "ldsched" "!yes") 111 (and (eq_attr "ldsched" "!yes")
120 (eq_attr "type" "load_byte,load1,load2,load3,load4,store1"))) 112 (eq_attr "type" "load_byte,load_4,load_8,load_12,load_16,store_4")))
121 "core*2") 113 "core*2")
122 114
123 (define_insn_reservation "mult" 16 115 (define_insn_reservation "mult" 16
124 (and (eq_attr "generic_sched" "yes") 116 (and (eq_attr "generic_sched" "yes")
125 (and (eq_attr "ldsched" "no") (eq_attr "type" "mult"))) 117 (and (eq_attr "ldsched" "no")
118 (ior (eq_attr "mul32" "yes")
119 (eq_attr "mul64" "yes"))))
126 "core*16") 120 "core*16")
127 121
128 (define_insn_reservation "mult_ldsched_strongarm" 3 122 (define_insn_reservation "mult_ldsched_strongarm" 3
129 (and (eq_attr "generic_sched" "yes") 123 (and (eq_attr "generic_sched" "yes")
130 (and (eq_attr "ldsched" "yes") 124 (and (eq_attr "ldsched" "yes")
131 (and (eq_attr "tune" 125 (and (eq_attr "tune"
132 "strongarm,strongarm110,strongarm1100,strongarm1110") 126 "strongarm,strongarm110,strongarm1100,strongarm1110")
133 (eq_attr "type" "mult")))) 127 (ior (eq_attr "mul32" "yes")
128 (eq_attr "mul64" "yes")))))
134 "core*2") 129 "core*2")
135 130
136 (define_insn_reservation "mult_ldsched" 4 131 (define_insn_reservation "mult_ldsched" 4
137 (and (eq_attr "generic_sched" "yes") 132 (and (eq_attr "generic_sched" "yes")
138 (and (eq_attr "ldsched" "yes") 133 (and (eq_attr "ldsched" "yes")
139 (and (eq_attr "tune" 134 (and (eq_attr "tune"
140 "!strongarm,strongarm110,strongarm1100,strongarm1110") 135 "!strongarm,strongarm110,strongarm1100,strongarm1110")
141 (eq_attr "type" "mult")))) 136 (ior (eq_attr "mul32" "yes")
137 (eq_attr "mul64" "yes")))))
142 "core*4") 138 "core*4")
143 139
144 (define_insn_reservation "multi_cycle" 32 140 (define_insn_reservation "multi_cycle" 32
145 (and (eq_attr "generic_sched" "yes") 141 (and (eq_attr "generic_sched" "yes")
146 (and (eq_attr "core_cycles" "multi") 142 (and (eq_attr "core_cycles" "multi")
147 (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4"))) 143 (and (eq_attr "type" "!load_byte,load_4,load_8,load_12,load_16,\
144 store_4,store_8,store_12,store_16")
145 (not (ior (eq_attr "mul32" "yes")
146 (eq_attr "mul64" "yes"))))))
148 "core*32") 147 "core*32")
149 148
150 (define_insn_reservation "single_cycle" 1 149 (define_insn_reservation "single_cycle" 1
151 (and (eq_attr "generic_sched" "yes") 150 (and (eq_attr "generic_sched" "yes")
152 (eq_attr "core_cycles" "single")) 151 (eq_attr "core_cycles" "single"))