--- a/gcc/config/arm/arm-generic.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/arm/arm-generic.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; Generic ARM Pipeline Description
-;; Copyright (C) 2003, 2007, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -38,91 +38,85 @@
 ;
 ; The write_blockage unit models (partially), the fact that reads will stall
 ; until the write buffer empties.
-; The f_mem_r and r_mem_f could also block, but they are to the stack,
-; so we don't model them here
 (define_cpu_unit "write_blockage" "arm")
 
 ;; Core
 ;
 (define_cpu_unit "core" "arm")
 
-(define_insn_reservation "r_mem_f_wbuf" 5
-  (and (eq_attr "generic_sched" "yes")
-       (and (eq_attr "model_wbuf" "yes")
-	    (eq_attr "type" "r_mem_f")))
-  "core+write_buf*3")
-
 (define_insn_reservation "store_wbuf" 5
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "yes")
-       	    (eq_attr "type" "store1")))
+       	    (eq_attr "type" "store_4")))
   "core+write_buf*3+write_blockage*5")
 
 (define_insn_reservation "store2_wbuf" 7
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "yes")
-	    (eq_attr "type" "store2")))
+	    (eq_attr "type" "store_8")))
   "core+write_buf*4+write_blockage*7")
 
 (define_insn_reservation "store3_wbuf" 9
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "yes")
-	    (eq_attr "type" "store3")))
+	    (eq_attr "type" "store_12")))
   "core+write_buf*5+write_blockage*9")
 
 (define_insn_reservation "store4_wbuf" 11
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "yes")
-            (eq_attr "type" "store4")))
+            (eq_attr "type" "store_16")))
   "core+write_buf*6+write_blockage*11")
 
 (define_insn_reservation "store2" 3
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "no")
-            (eq_attr "type" "store2")))
+            (eq_attr "type" "store_8")))
   "core*3")
 
 (define_insn_reservation "store3" 4
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "no")
-            (eq_attr "type" "store3")))
+            (eq_attr "type" "store_12")))
   "core*4")
 
 (define_insn_reservation "store4" 5
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "no")
-	    (eq_attr "type" "store4")))
+	    (eq_attr "type" "store_16")))
   "core*5")
 
 (define_insn_reservation "store_ldsched" 1
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "ldsched" "yes") 
-	    (eq_attr "type" "store1")))
+	    (eq_attr "type" "store_4")))
   "core")
 
 (define_insn_reservation "load_ldsched_xscale" 3
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "ldsched" "yes") 
-	    (and (eq_attr "type" "load_byte,load1")
+	    (and (eq_attr "type" "load_byte,load_4")
 	         (eq_attr "tune" "xscale,iwmmxt,iwmmxt2"))))
   "core")
 
 (define_insn_reservation "load_ldsched" 2
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "ldsched" "yes") 
-	    (and (eq_attr "type" "load_byte,load1")
+	    (and (eq_attr "type" "load_byte,load_4")
 	         (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"))))
   "core")
 
 (define_insn_reservation "load_or_store" 2
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "ldsched" "!yes") 
-	    (eq_attr "type" "load_byte,load1,load2,load3,load4,store1")))
+	    (eq_attr "type" "load_byte,load_4,load_8,load_12,load_16,store_4")))
   "core*2")
 
 (define_insn_reservation "mult" 16
   (and (eq_attr "generic_sched" "yes")
-       (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")))
+       (and (eq_attr "ldsched" "no")
+	    (ior (eq_attr "mul32" "yes")
+		 (eq_attr "mul64" "yes"))))
   "core*16")
 
 (define_insn_reservation "mult_ldsched_strongarm" 3
@@ -130,7 +124,8 @@
        (and (eq_attr "ldsched" "yes") 
 	    (and (eq_attr "tune"
 		  "strongarm,strongarm110,strongarm1100,strongarm1110")
-	         (eq_attr "type" "mult"))))
+		 (ior (eq_attr "mul32" "yes")
+		      (eq_attr "mul64" "yes")))))
   "core*2")
 
 (define_insn_reservation "mult_ldsched" 4
@@ -138,13 +133,17 @@
        (and (eq_attr "ldsched" "yes") 
 	    (and (eq_attr "tune"
 		  "!strongarm,strongarm110,strongarm1100,strongarm1110")
-	         (eq_attr "type" "mult"))))
+	         (ior (eq_attr "mul32" "yes")
+		      (eq_attr "mul64" "yes")))))
   "core*4")
 
 (define_insn_reservation "multi_cycle" 32
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "core_cycles" "multi")
-            (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4")))
+            (and (eq_attr "type" "!load_byte,load_4,load_8,load_12,load_16,\
+                                  store_4,store_8,store_12,store_16")
+		 (not (ior (eq_attr "mul32" "yes")
+			   (eq_attr "mul64" "yes"))))))
   "core*32")
 
 (define_insn_reservation "single_cycle" 1