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comparison gcc/config/arm/fa606te.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Faraday FA606TE Pipeline Description 1 ;; Faraday FA606TE Pipeline Description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description. 3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it under 7 ;; GCC is free software; you can redistribute it and/or modify it under
52 ;; ALU Instructions 52 ;; ALU Instructions
53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54 54
55 ;; ALU instructions require two cycles to execute, and use the ALU 55 ;; ALU instructions require two cycles to execute, and use the ALU
56 ;; pipeline in each of the three stages. The results are available 56 ;; pipeline in each of the three stages. The results are available
57 ;; after the execute stage stage has finished. 57 ;; after the execute stage has finished.
58 ;; 58 ;;
59 ;; If the destination register is the PC, the pipelines are stalled 59 ;; If the destination register is the PC, the pipelines are stalled
60 ;; for several cycles. That case is not modeled here. 60 ;; for several cycles. That case is not modeled here.
61 61
62 ;; ALU operations 62 ;; ALU operations
63 (define_insn_reservation "606te_alu_op" 1 63 (define_insn_reservation "606te_alu_op" 1
64 (and (eq_attr "tune" "fa606te") 64 (and (eq_attr "tune" "fa606te")
65 (eq_attr "type" "alu,alu_shift,alu_shift_reg")) 65 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
66 alu_sreg,alus_sreg,logic_reg,logics_reg,\
67 adc_imm,adcs_imm,adc_reg,adcs_reg,\
68 adr,bfm,rev,\
69 shift_imm,shift_reg,extend,\
70 alu_shift_imm,alus_shift_imm,\
71 logic_shift_imm,logics_shift_imm,\
72 alu_shift_reg,alus_shift_reg,\
73 logic_shift_reg,logics_shift_reg,\
74 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
75 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
76 mrs,multiple,no_insn"))
66 "fa606te_core") 77 "fa606te_core")
67 78
68 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 79 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
69 ;; Multiplication Instructions 80 ;; Multiplication Instructions
70 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 81 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
71 82
72 (define_insn_reservation "606te_mult1" 2 83 (define_insn_reservation "606te_mult1" 2
73 (and (eq_attr "tune" "fa606te") 84 (and (eq_attr "tune" "fa606te")
74 (eq_attr "insn" "smlalxy")) 85 (eq_attr "type" "smlalxy"))
75 "fa606te_core") 86 "fa606te_core")
76 87
77 (define_insn_reservation "606te_mult2" 3 88 (define_insn_reservation "606te_mult2" 3
78 (and (eq_attr "tune" "fa606te") 89 (and (eq_attr "tune" "fa606te")
79 (eq_attr "insn" "smlaxy,smulxy,smulwy,smlawy")) 90 (eq_attr "type" "smlaxy,smulxy,smulwy,smlawy"))
80 "fa606te_core*2") 91 "fa606te_core*2")
81 92
82 (define_insn_reservation "606te_mult3" 4 93 (define_insn_reservation "606te_mult3" 4
83 (and (eq_attr "tune" "fa606te") 94 (and (eq_attr "tune" "fa606te")
84 (eq_attr "insn" "mul,mla,muls,mlas")) 95 (eq_attr "type" "mul,mla,muls,mlas"))
85 "fa606te_core*3") 96 "fa606te_core*3")
86 97
87 (define_insn_reservation "606te_mult4" 5 98 (define_insn_reservation "606te_mult4" 5
88 (and (eq_attr "tune" "fa606te") 99 (and (eq_attr "tune" "fa606te")
89 (eq_attr "insn" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals")) 100 (eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
90 "fa606te_core*4") 101 "fa606te_core*4")
91 102
92 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
93 ;; Load/Store Instructions 104 ;; Load/Store Instructions
94 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 105 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
98 ;; (such as "ldm!"). These models assume that all memory references 109 ;; (such as "ldm!"). These models assume that all memory references
99 ;; hit in dcache. 110 ;; hit in dcache.
100 111
101 (define_insn_reservation "606te_load1_op" 2 112 (define_insn_reservation "606te_load1_op" 2
102 (and (eq_attr "tune" "fa606te") 113 (and (eq_attr "tune" "fa606te")
103 (eq_attr "type" "load1,load_byte")) 114 (eq_attr "type" "load_4,load_byte"))
104 "fa606te_core") 115 "fa606te_core")
105 116
106 (define_insn_reservation "606te_load2_op" 3 117 (define_insn_reservation "606te_load2_op" 3
107 (and (eq_attr "tune" "fa606te") 118 (and (eq_attr "tune" "fa606te")
108 (eq_attr "type" "load2")) 119 (eq_attr "type" "load_8"))
109 "fa606te_core*2") 120 "fa606te_core*2")
110 121
111 (define_insn_reservation "606te_load3_op" 4 122 (define_insn_reservation "606te_load3_op" 4
112 (and (eq_attr "tune" "fa606te") 123 (and (eq_attr "tune" "fa606te")
113 (eq_attr "type" "load3")) 124 (eq_attr "type" "load_12"))
114 "fa606te_core*3") 125 "fa606te_core*3")
115 126
116 (define_insn_reservation "606te_load4_op" 5 127 (define_insn_reservation "606te_load4_op" 5
117 (and (eq_attr "tune" "fa606te") 128 (and (eq_attr "tune" "fa606te")
118 (eq_attr "type" "load4")) 129 (eq_attr "type" "load_16"))
119 "fa606te_core*4") 130 "fa606te_core*4")
120 131
121 (define_insn_reservation "606te_store1_op" 0 132 (define_insn_reservation "606te_store1_op" 0
122 (and (eq_attr "tune" "fa606te") 133 (and (eq_attr "tune" "fa606te")
123 (eq_attr "type" "store1")) 134 (eq_attr "type" "store_4"))
124 "fa606te_core") 135 "fa606te_core")
125 136
126 (define_insn_reservation "606te_store2_op" 1 137 (define_insn_reservation "606te_store2_op" 1
127 (and (eq_attr "tune" "fa606te") 138 (and (eq_attr "tune" "fa606te")
128 (eq_attr "type" "store2")) 139 (eq_attr "type" "store_8"))
129 "fa606te_core*2") 140 "fa606te_core*2")
130 141
131 (define_insn_reservation "606te_store3_op" 2 142 (define_insn_reservation "606te_store3_op" 2
132 (and (eq_attr "tune" "fa606te") 143 (and (eq_attr "tune" "fa606te")
133 (eq_attr "type" "store3")) 144 (eq_attr "type" "store_12"))
134 "fa606te_core*3") 145 "fa606te_core*3")
135 146
136 (define_insn_reservation "606te_store4_op" 3 147 (define_insn_reservation "606te_store4_op" 3
137 (and (eq_attr "tune" "fa606te") 148 (and (eq_attr "tune" "fa606te")
138 (eq_attr "type" "store4")) 149 (eq_attr "type" "store_16"))
139 "fa606te_core*4") 150 "fa606te_core*4")
140 151
141 152
142 ;;(define_insn_reservation "606te_ldm_op" 9 153 ;;(define_insn_reservation "606te_ldm_op" 9
143 ;; (and (eq_attr "tune" "fa606te") 154 ;; (and (eq_attr "tune" "fa606te")
144 ;; (eq_attr "type" "load2,load3,load4,store2,store3,store4")) 155 ;; (eq_attr "type" "load_8,load_12,load_16,store_8,store_12,store_16"))
145 ;; "fa606te_core*7") 156 ;; "fa606te_core*7")
146 157
147 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 158 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
148 ;; Branch and Call Instructions 159 ;; Branch and Call Instructions
149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 160 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;