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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
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1 ;; Faraday FA606TE Pipeline Description
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2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
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3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it under
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8 ;; the terms of the GNU General Public License as published by the Free
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9 ;; Software Foundation; either version 3, or (at your option) any later
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10 ;; version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ;; for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; FA606TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
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23
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24 ;; Modeled pipeline characteristics:
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25 ;; LD -> any use: latency = 2 (1 cycle penalty).
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26 ;; ALU -> any use: latency = 1 (0 cycle penalty).
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27
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28 ;; This automaton provides a pipeline description for the Faraday
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29 ;; FA606TE core.
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30 ;;
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31 ;; The model given here assumes that the condition for all conditional
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32 ;; instructions is "true", i.e., that all of the instructions are
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33 ;; actually executed.
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34
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35 (define_automaton "fa606te")
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36
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37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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38 ;; Pipelines
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39 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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40
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41 ;; There is a single pipeline
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42 ;;
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43 ;; The ALU pipeline has fetch, decode, execute, memory, and
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44 ;; write stages. We only need to model the execute, memory and write
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45 ;; stages.
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46
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47 ;; E M W
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48
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49 (define_cpu_unit "fa606te_core" "fa606te")
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50
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51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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52 ;; ALU Instructions
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53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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54
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55 ;; ALU instructions require two cycles to execute, and use the ALU
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56 ;; pipeline in each of the three stages. The results are available
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57 ;; after the execute stage has finished.
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58 ;;
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59 ;; If the destination register is the PC, the pipelines are stalled
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60 ;; for several cycles. That case is not modeled here.
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61
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62 ;; ALU operations
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63 (define_insn_reservation "606te_alu_op" 1
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64 (and (eq_attr "tune" "fa606te")
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65 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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66 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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67 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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68 adr,bfm,rev,\
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69 shift_imm,shift_reg,extend,\
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70 alu_shift_imm,alus_shift_imm,\
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71 logic_shift_imm,logics_shift_imm,\
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72 alu_shift_reg,alus_shift_reg,\
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73 logic_shift_reg,logics_shift_reg,\
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74 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
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75 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
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76 mrs,multiple,no_insn"))
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77 "fa606te_core")
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78
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79 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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80 ;; Multiplication Instructions
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81 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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82
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83 (define_insn_reservation "606te_mult1" 2
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84 (and (eq_attr "tune" "fa606te")
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85 (eq_attr "type" "smlalxy"))
68
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86 "fa606te_core")
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87
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88 (define_insn_reservation "606te_mult2" 3
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89 (and (eq_attr "tune" "fa606te")
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90 (eq_attr "type" "smlaxy,smulxy,smulwy,smlawy"))
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91 "fa606te_core*2")
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92
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93 (define_insn_reservation "606te_mult3" 4
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94 (and (eq_attr "tune" "fa606te")
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95 (eq_attr "type" "mul,mla,muls,mlas"))
68
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96 "fa606te_core*3")
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97
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98 (define_insn_reservation "606te_mult4" 5
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99 (and (eq_attr "tune" "fa606te")
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100 (eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals"))
68
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101 "fa606te_core*4")
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102
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103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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104 ;; Load/Store Instructions
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105 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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106
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107 ;; The models for load/store instructions do not accurately describe
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108 ;; the difference between operations with a base register writeback
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109 ;; (such as "ldm!"). These models assume that all memory references
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110 ;; hit in dcache.
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111
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112 (define_insn_reservation "606te_load1_op" 2
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113 (and (eq_attr "tune" "fa606te")
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114 (eq_attr "type" "load_4,load_byte"))
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115 "fa606te_core")
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116
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117 (define_insn_reservation "606te_load2_op" 3
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118 (and (eq_attr "tune" "fa606te")
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119 (eq_attr "type" "load_8"))
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120 "fa606te_core*2")
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121
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122 (define_insn_reservation "606te_load3_op" 4
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123 (and (eq_attr "tune" "fa606te")
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124 (eq_attr "type" "load_12"))
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125 "fa606te_core*3")
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126
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127 (define_insn_reservation "606te_load4_op" 5
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128 (and (eq_attr "tune" "fa606te")
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129 (eq_attr "type" "load_16"))
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130 "fa606te_core*4")
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131
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132 (define_insn_reservation "606te_store1_op" 0
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133 (and (eq_attr "tune" "fa606te")
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134 (eq_attr "type" "store_4"))
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135 "fa606te_core")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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136
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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137 (define_insn_reservation "606te_store2_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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138 (and (eq_attr "tune" "fa606te")
111
kono
parents: 68
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139 (eq_attr "type" "store_8"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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140 "fa606te_core*2")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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141
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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142 (define_insn_reservation "606te_store3_op" 2
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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143 (and (eq_attr "tune" "fa606te")
111
kono
parents: 68
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144 (eq_attr "type" "store_12"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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145 "fa606te_core*3")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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146
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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147 (define_insn_reservation "606te_store4_op" 3
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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148 (and (eq_attr "tune" "fa606te")
111
kono
parents: 68
diff changeset
149 (eq_attr "type" "store_16"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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150 "fa606te_core*4")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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151
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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152
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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153 ;;(define_insn_reservation "606te_ldm_op" 9
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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154 ;; (and (eq_attr "tune" "fa606te")
111
kono
parents: 68
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155 ;; (eq_attr "type" "load_8,load_12,load_16,store_8,store_12,store_16"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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156 ;; "fa606te_core*7")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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157
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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158 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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159 ;; Branch and Call Instructions
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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160 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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161
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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162 ;; Branch instructions are difficult to model accurately. The FA606TE
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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163 ;; core can predict most branches. If the branch is predicted
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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164 ;; correctly, and predicted early enough, the branch can be completely
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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165 ;; eliminated from the instruction stream. Some branches can
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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166 ;; therefore appear to require zero cycles to execute. We assume that
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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167 ;; all branches are predicted correctly, and that the latency is
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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168 ;; therefore the minimum value.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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169
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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170 (define_insn_reservation "606te_branch_op" 0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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171 (and (eq_attr "tune" "fa606te")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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172 (eq_attr "type" "branch"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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173 "fa606te_core")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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174
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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175 ;; The latency for a call is actually the latency when the result is available.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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176 ;; i.e. R0 ready for int return value. For most cases, the return value is set
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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177 ;; by a mov instruction, which has 1 cycle latency.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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178 (define_insn_reservation "606te_call_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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179 (and (eq_attr "tune" "fa606te")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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180 (eq_attr "type" "call"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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181 "fa606te_core")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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182