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comparison gcc/config/arm/ldmstm.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 /* ARM ldm/stm instruction patterns. This file was automatically generated 1 /* ARM ldm/stm instruction patterns. This file was automatically generated
2 using arm-ldmstm.ml. Please do not edit manually. 2 using arm-ldmstm.ml. Please do not edit manually.
3 3
4 Copyright (C) 2010 Free Software Foundation, Inc. 4 Copyright (C) 2010-2017 Free Software Foundation, Inc.
5 Contributed by CodeSourcery. 5 Contributed by CodeSourcery.
6 6
7 This file is part of GCC. 7 This file is part of GCC.
8 8
9 GCC is free software; you can redistribute it and/or modify it 9 GCC is free software; you can redistribute it and/or modify it
19 You should have received a copy of the GNU General Public License and 19 You should have received a copy of the GNU General Public License and
20 a copy of the GCC Runtime Library Exception along with this program; 20 a copy of the GCC Runtime Library Exception along with this program;
21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
22 <http://www.gnu.org/licenses/>. */ 22 <http://www.gnu.org/licenses/>. */
23 23
24 (define_insn "*ldm4_ia" 24 (define_insn "*ldm4_"
25 [(match_parallel 0 "load_multiple_operation" 25 [(match_parallel 0 "load_multiple_operation"
26 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 26 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
27 (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) 27 (mem:SI (match_operand:SI 5 "s_register_operand" "rk")))
28 (set (match_operand:SI 2 "arm_hard_register_operand" "") 28 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
29 (mem:SI (plus:SI (match_dup 5) 29 (mem:SI (plus:SI (match_dup 5)
30 (const_int 4)))) 30 (const_int 4))))
31 (set (match_operand:SI 3 "arm_hard_register_operand" "") 31 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
32 (mem:SI (plus:SI (match_dup 5) 32 (mem:SI (plus:SI (match_dup 5)
33 (const_int 8)))) 33 (const_int 8))))
34 (set (match_operand:SI 4 "arm_hard_register_operand" "") 34 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
35 (mem:SI (plus:SI (match_dup 5) 35 (mem:SI (plus:SI (match_dup 5)
36 (const_int 12))))])] 36 (const_int 12))))])]
37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
38 "ldm%(ia%)\t%5, {%1, %2, %3, %4}" 38 "ldm%?\t%5, {%1, %2, %3, %4}"
39 [(set_attr "type" "load4") 39 [(set_attr "type" "load_16")
40 (set_attr "predicable" "yes")]) 40 (set_attr "predicable" "yes")
41 (set_attr "predicable_short_it" "no")])
41 42
42 (define_insn "*thumb_ldm4_ia" 43 (define_insn "*thumb_ldm4_ia"
43 [(match_parallel 0 "load_multiple_operation" 44 [(match_parallel 0 "load_multiple_operation"
44 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 45 [(set (match_operand:SI 1 "low_register_operand" "")
45 (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) 46 (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
46 (set (match_operand:SI 2 "arm_hard_register_operand" "") 47 (set (match_operand:SI 2 "low_register_operand" "")
47 (mem:SI (plus:SI (match_dup 5) 48 (mem:SI (plus:SI (match_dup 5)
48 (const_int 4)))) 49 (const_int 4))))
49 (set (match_operand:SI 3 "arm_hard_register_operand" "") 50 (set (match_operand:SI 3 "low_register_operand" "")
50 (mem:SI (plus:SI (match_dup 5) 51 (mem:SI (plus:SI (match_dup 5)
51 (const_int 8)))) 52 (const_int 8))))
52 (set (match_operand:SI 4 "arm_hard_register_operand" "") 53 (set (match_operand:SI 4 "low_register_operand" "")
53 (mem:SI (plus:SI (match_dup 5) 54 (mem:SI (plus:SI (match_dup 5)
54 (const_int 12))))])] 55 (const_int 12))))])]
55 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 56 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
56 "ldm%(ia%)\t%5, {%1, %2, %3, %4}" 57 "ldmia\t%5, {%1, %2, %3, %4}"
57 [(set_attr "type" "load4")]) 58 [(set_attr "type" "load_16")])
58 59
59 (define_insn "*ldm4_ia_update" 60 (define_insn "*ldm4_ia_update"
60 [(match_parallel 0 "load_multiple_operation" 61 [(match_parallel 0 "load_multiple_operation"
61 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 62 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
62 (plus:SI (match_dup 5) (const_int 16))) 63 (plus:SI (match_dup 5) (const_int 16)))
63 (set (match_operand:SI 1 "arm_hard_register_operand" "") 64 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
64 (mem:SI (match_dup 5))) 65 (mem:SI (match_dup 5)))
65 (set (match_operand:SI 2 "arm_hard_register_operand" "") 66 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
66 (mem:SI (plus:SI (match_dup 5) 67 (mem:SI (plus:SI (match_dup 5)
67 (const_int 4)))) 68 (const_int 4))))
68 (set (match_operand:SI 3 "arm_hard_register_operand" "") 69 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
69 (mem:SI (plus:SI (match_dup 5) 70 (mem:SI (plus:SI (match_dup 5)
70 (const_int 8)))) 71 (const_int 8))))
71 (set (match_operand:SI 4 "arm_hard_register_operand" "") 72 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
72 (mem:SI (plus:SI (match_dup 5) 73 (mem:SI (plus:SI (match_dup 5)
73 (const_int 12))))])] 74 (const_int 12))))])]
74 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 75 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
75 "ldm%(ia%)\t%5!, {%1, %2, %3, %4}" 76 "ldmia%?\t%5!, {%1, %2, %3, %4}"
76 [(set_attr "type" "load4") 77 [(set_attr "type" "load_16")
77 (set_attr "predicable" "yes")]) 78 (set_attr "predicable" "yes")
79 (set_attr "predicable_short_it" "no")])
78 80
79 (define_insn "*thumb_ldm4_ia_update" 81 (define_insn "*thumb_ldm4_ia_update"
80 [(match_parallel 0 "load_multiple_operation" 82 [(match_parallel 0 "load_multiple_operation"
81 [(set (match_operand:SI 5 "s_register_operand" "+&l") 83 [(set (match_operand:SI 5 "s_register_operand" "+&l")
82 (plus:SI (match_dup 5) (const_int 16))) 84 (plus:SI (match_dup 5) (const_int 16)))
83 (set (match_operand:SI 1 "arm_hard_register_operand" "") 85 (set (match_operand:SI 1 "low_register_operand" "")
84 (mem:SI (match_dup 5))) 86 (mem:SI (match_dup 5)))
85 (set (match_operand:SI 2 "arm_hard_register_operand" "") 87 (set (match_operand:SI 2 "low_register_operand" "")
86 (mem:SI (plus:SI (match_dup 5) 88 (mem:SI (plus:SI (match_dup 5)
87 (const_int 4)))) 89 (const_int 4))))
88 (set (match_operand:SI 3 "arm_hard_register_operand" "") 90 (set (match_operand:SI 3 "low_register_operand" "")
89 (mem:SI (plus:SI (match_dup 5) 91 (mem:SI (plus:SI (match_dup 5)
90 (const_int 8)))) 92 (const_int 8))))
91 (set (match_operand:SI 4 "arm_hard_register_operand" "") 93 (set (match_operand:SI 4 "low_register_operand" "")
92 (mem:SI (plus:SI (match_dup 5) 94 (mem:SI (plus:SI (match_dup 5)
93 (const_int 12))))])] 95 (const_int 12))))])]
94 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" 96 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
95 "ldm%(ia%)\t%5!, {%1, %2, %3, %4}" 97 "ldmia\t%5!, {%1, %2, %3, %4}"
96 [(set_attr "type" "load4")]) 98 [(set_attr "type" "load_16")])
97 99
98 (define_insn "*stm4_ia" 100 (define_insn "*stm4_"
99 [(match_parallel 0 "store_multiple_operation" 101 [(match_parallel 0 "store_multiple_operation"
100 [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) 102 [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))
101 (match_operand:SI 1 "arm_hard_register_operand" "")) 103 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
102 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 104 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
103 (match_operand:SI 2 "arm_hard_register_operand" "")) 105 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
104 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 106 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
105 (match_operand:SI 3 "arm_hard_register_operand" "")) 107 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
106 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 108 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
107 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 109 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
108 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 110 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
109 "stm%(ia%)\t%5, {%1, %2, %3, %4}" 111 "stm%?\t%5, {%1, %2, %3, %4}"
110 [(set_attr "type" "store4") 112 [(set_attr "type" "store_16")
111 (set_attr "predicable" "yes")]) 113 (set_attr "predicable" "yes")
114 (set_attr "predicable_short_it" "no")])
112 115
113 (define_insn "*stm4_ia_update" 116 (define_insn "*stm4_ia_update"
114 [(match_parallel 0 "store_multiple_operation" 117 [(match_parallel 0 "store_multiple_operation"
115 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 118 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
116 (plus:SI (match_dup 5) (const_int 16))) 119 (plus:SI (match_dup 5) (const_int 16)))
117 (set (mem:SI (match_dup 5)) 120 (set (mem:SI (match_dup 5))
118 (match_operand:SI 1 "arm_hard_register_operand" "")) 121 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
119 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 122 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
120 (match_operand:SI 2 "arm_hard_register_operand" "")) 123 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
121 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 124 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
122 (match_operand:SI 3 "arm_hard_register_operand" "")) 125 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
123 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 126 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
124 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 127 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
125 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 128 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
126 "stm%(ia%)\t%5!, {%1, %2, %3, %4}" 129 "stmia%?\t%5!, {%1, %2, %3, %4}"
127 [(set_attr "type" "store4") 130 [(set_attr "type" "store_16")
128 (set_attr "predicable" "yes")]) 131 (set_attr "predicable" "yes")
132 (set_attr "predicable_short_it" "no")])
129 133
130 (define_insn "*thumb_stm4_ia_update" 134 (define_insn "*thumb_stm4_ia_update"
131 [(match_parallel 0 "store_multiple_operation" 135 [(match_parallel 0 "store_multiple_operation"
132 [(set (match_operand:SI 5 "s_register_operand" "+&l") 136 [(set (match_operand:SI 5 "s_register_operand" "+&l")
133 (plus:SI (match_dup 5) (const_int 16))) 137 (plus:SI (match_dup 5) (const_int 16)))
134 (set (mem:SI (match_dup 5)) 138 (set (mem:SI (match_dup 5))
135 (match_operand:SI 1 "arm_hard_register_operand" "")) 139 (match_operand:SI 1 "low_register_operand" ""))
136 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 140 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
137 (match_operand:SI 2 "arm_hard_register_operand" "")) 141 (match_operand:SI 2 "low_register_operand" ""))
138 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 142 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
139 (match_operand:SI 3 "arm_hard_register_operand" "")) 143 (match_operand:SI 3 "low_register_operand" ""))
140 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 144 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
141 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 145 (match_operand:SI 4 "low_register_operand" ""))])]
142 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" 146 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
143 "stm%(ia%)\t%5!, {%1, %2, %3, %4}" 147 "stmia\t%5!, {%1, %2, %3, %4}"
144 [(set_attr "type" "store4")]) 148 [(set_attr "type" "store_16")])
145 149
146 (define_insn "*ldm4_ib" 150 (define_insn "*ldm4_ib"
147 [(match_parallel 0 "load_multiple_operation" 151 [(match_parallel 0 "load_multiple_operation"
148 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 152 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
149 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 153 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
150 (const_int 4)))) 154 (const_int 4))))
151 (set (match_operand:SI 2 "arm_hard_register_operand" "") 155 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
152 (mem:SI (plus:SI (match_dup 5) 156 (mem:SI (plus:SI (match_dup 5)
153 (const_int 8)))) 157 (const_int 8))))
154 (set (match_operand:SI 3 "arm_hard_register_operand" "") 158 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
155 (mem:SI (plus:SI (match_dup 5) 159 (mem:SI (plus:SI (match_dup 5)
156 (const_int 12)))) 160 (const_int 12))))
157 (set (match_operand:SI 4 "arm_hard_register_operand" "") 161 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
158 (mem:SI (plus:SI (match_dup 5) 162 (mem:SI (plus:SI (match_dup 5)
159 (const_int 16))))])] 163 (const_int 16))))])]
160 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 164 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
161 "ldm%(ib%)\t%5, {%1, %2, %3, %4}" 165 "ldmib%?\t%5, {%1, %2, %3, %4}"
162 [(set_attr "type" "load4") 166 [(set_attr "type" "load_16")
163 (set_attr "predicable" "yes")]) 167 (set_attr "predicable" "yes")])
164 168
165 (define_insn "*ldm4_ib_update" 169 (define_insn "*ldm4_ib_update"
166 [(match_parallel 0 "load_multiple_operation" 170 [(match_parallel 0 "load_multiple_operation"
167 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 171 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
168 (plus:SI (match_dup 5) (const_int 16))) 172 (plus:SI (match_dup 5) (const_int 16)))
169 (set (match_operand:SI 1 "arm_hard_register_operand" "") 173 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
170 (mem:SI (plus:SI (match_dup 5) 174 (mem:SI (plus:SI (match_dup 5)
171 (const_int 4)))) 175 (const_int 4))))
172 (set (match_operand:SI 2 "arm_hard_register_operand" "") 176 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
173 (mem:SI (plus:SI (match_dup 5) 177 (mem:SI (plus:SI (match_dup 5)
174 (const_int 8)))) 178 (const_int 8))))
175 (set (match_operand:SI 3 "arm_hard_register_operand" "") 179 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
176 (mem:SI (plus:SI (match_dup 5) 180 (mem:SI (plus:SI (match_dup 5)
177 (const_int 12)))) 181 (const_int 12))))
178 (set (match_operand:SI 4 "arm_hard_register_operand" "") 182 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
179 (mem:SI (plus:SI (match_dup 5) 183 (mem:SI (plus:SI (match_dup 5)
180 (const_int 16))))])] 184 (const_int 16))))])]
181 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 185 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
182 "ldm%(ib%)\t%5!, {%1, %2, %3, %4}" 186 "ldmib%?\t%5!, {%1, %2, %3, %4}"
183 [(set_attr "type" "load4") 187 [(set_attr "type" "load_16")
184 (set_attr "predicable" "yes")]) 188 (set_attr "predicable" "yes")])
185 189
186 (define_insn "*stm4_ib" 190 (define_insn "*stm4_ib"
187 [(match_parallel 0 "store_multiple_operation" 191 [(match_parallel 0 "store_multiple_operation"
188 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) 192 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))
189 (match_operand:SI 1 "arm_hard_register_operand" "")) 193 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
190 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 194 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
191 (match_operand:SI 2 "arm_hard_register_operand" "")) 195 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
192 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 196 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
193 (match_operand:SI 3 "arm_hard_register_operand" "")) 197 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
194 (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) 198 (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
195 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 199 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
196 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 200 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
197 "stm%(ib%)\t%5, {%1, %2, %3, %4}" 201 "stmib%?\t%5, {%1, %2, %3, %4}"
198 [(set_attr "type" "store4") 202 [(set_attr "type" "store_16")
199 (set_attr "predicable" "yes")]) 203 (set_attr "predicable" "yes")])
200 204
201 (define_insn "*stm4_ib_update" 205 (define_insn "*stm4_ib_update"
202 [(match_parallel 0 "store_multiple_operation" 206 [(match_parallel 0 "store_multiple_operation"
203 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 207 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
204 (plus:SI (match_dup 5) (const_int 16))) 208 (plus:SI (match_dup 5) (const_int 16)))
205 (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) 209 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
206 (match_operand:SI 1 "arm_hard_register_operand" "")) 210 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
207 (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) 211 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
208 (match_operand:SI 2 "arm_hard_register_operand" "")) 212 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
209 (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) 213 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
210 (match_operand:SI 3 "arm_hard_register_operand" "")) 214 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
211 (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) 215 (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
212 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 216 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
213 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 217 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
214 "stm%(ib%)\t%5!, {%1, %2, %3, %4}" 218 "stmib%?\t%5!, {%1, %2, %3, %4}"
215 [(set_attr "type" "store4") 219 [(set_attr "type" "store_16")
216 (set_attr "predicable" "yes")]) 220 (set_attr "predicable" "yes")])
217 221
218 (define_insn "*ldm4_da" 222 (define_insn "*ldm4_da"
219 [(match_parallel 0 "load_multiple_operation" 223 [(match_parallel 0 "load_multiple_operation"
220 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 224 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
221 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 225 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
222 (const_int -12)))) 226 (const_int -12))))
223 (set (match_operand:SI 2 "arm_hard_register_operand" "") 227 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
224 (mem:SI (plus:SI (match_dup 5) 228 (mem:SI (plus:SI (match_dup 5)
225 (const_int -8)))) 229 (const_int -8))))
226 (set (match_operand:SI 3 "arm_hard_register_operand" "") 230 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
227 (mem:SI (plus:SI (match_dup 5) 231 (mem:SI (plus:SI (match_dup 5)
228 (const_int -4)))) 232 (const_int -4))))
229 (set (match_operand:SI 4 "arm_hard_register_operand" "") 233 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
230 (mem:SI (match_dup 5)))])] 234 (mem:SI (match_dup 5)))])]
231 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 235 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
232 "ldm%(da%)\t%5, {%1, %2, %3, %4}" 236 "ldmda%?\t%5, {%1, %2, %3, %4}"
233 [(set_attr "type" "load4") 237 [(set_attr "type" "load_16")
234 (set_attr "predicable" "yes")]) 238 (set_attr "predicable" "yes")])
235 239
236 (define_insn "*ldm4_da_update" 240 (define_insn "*ldm4_da_update"
237 [(match_parallel 0 "load_multiple_operation" 241 [(match_parallel 0 "load_multiple_operation"
238 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 242 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
239 (plus:SI (match_dup 5) (const_int -16))) 243 (plus:SI (match_dup 5) (const_int -16)))
240 (set (match_operand:SI 1 "arm_hard_register_operand" "") 244 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
241 (mem:SI (plus:SI (match_dup 5) 245 (mem:SI (plus:SI (match_dup 5)
242 (const_int -12)))) 246 (const_int -12))))
243 (set (match_operand:SI 2 "arm_hard_register_operand" "") 247 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
244 (mem:SI (plus:SI (match_dup 5) 248 (mem:SI (plus:SI (match_dup 5)
245 (const_int -8)))) 249 (const_int -8))))
246 (set (match_operand:SI 3 "arm_hard_register_operand" "") 250 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
247 (mem:SI (plus:SI (match_dup 5) 251 (mem:SI (plus:SI (match_dup 5)
248 (const_int -4)))) 252 (const_int -4))))
249 (set (match_operand:SI 4 "arm_hard_register_operand" "") 253 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
250 (mem:SI (match_dup 5)))])] 254 (mem:SI (match_dup 5)))])]
251 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 255 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
252 "ldm%(da%)\t%5!, {%1, %2, %3, %4}" 256 "ldmda%?\t%5!, {%1, %2, %3, %4}"
253 [(set_attr "type" "load4") 257 [(set_attr "type" "load_16")
254 (set_attr "predicable" "yes")]) 258 (set_attr "predicable" "yes")])
255 259
256 (define_insn "*stm4_da" 260 (define_insn "*stm4_da"
257 [(match_parallel 0 "store_multiple_operation" 261 [(match_parallel 0 "store_multiple_operation"
258 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) 262 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))
259 (match_operand:SI 1 "arm_hard_register_operand" "")) 263 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
260 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 264 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
261 (match_operand:SI 2 "arm_hard_register_operand" "")) 265 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
262 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 266 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
263 (match_operand:SI 3 "arm_hard_register_operand" "")) 267 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
264 (set (mem:SI (match_dup 5)) 268 (set (mem:SI (match_dup 5))
265 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 269 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
266 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 270 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
267 "stm%(da%)\t%5, {%1, %2, %3, %4}" 271 "stmda%?\t%5, {%1, %2, %3, %4}"
268 [(set_attr "type" "store4") 272 [(set_attr "type" "store_16")
269 (set_attr "predicable" "yes")]) 273 (set_attr "predicable" "yes")])
270 274
271 (define_insn "*stm4_da_update" 275 (define_insn "*stm4_da_update"
272 [(match_parallel 0 "store_multiple_operation" 276 [(match_parallel 0 "store_multiple_operation"
273 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 277 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
274 (plus:SI (match_dup 5) (const_int -16))) 278 (plus:SI (match_dup 5) (const_int -16)))
275 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 279 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
276 (match_operand:SI 1 "arm_hard_register_operand" "")) 280 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
277 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 281 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
278 (match_operand:SI 2 "arm_hard_register_operand" "")) 282 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
279 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 283 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
280 (match_operand:SI 3 "arm_hard_register_operand" "")) 284 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
281 (set (mem:SI (match_dup 5)) 285 (set (mem:SI (match_dup 5))
282 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 286 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
283 "TARGET_ARM && XVECLEN (operands[0], 0) == 5" 287 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
284 "stm%(da%)\t%5!, {%1, %2, %3, %4}" 288 "stmda%?\t%5!, {%1, %2, %3, %4}"
285 [(set_attr "type" "store4") 289 [(set_attr "type" "store_16")
286 (set_attr "predicable" "yes")]) 290 (set_attr "predicable" "yes")])
287 291
288 (define_insn "*ldm4_db" 292 (define_insn "*ldm4_db"
289 [(match_parallel 0 "load_multiple_operation" 293 [(match_parallel 0 "load_multiple_operation"
290 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 294 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
291 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") 295 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
292 (const_int -16)))) 296 (const_int -16))))
293 (set (match_operand:SI 2 "arm_hard_register_operand" "") 297 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
294 (mem:SI (plus:SI (match_dup 5) 298 (mem:SI (plus:SI (match_dup 5)
295 (const_int -12)))) 299 (const_int -12))))
296 (set (match_operand:SI 3 "arm_hard_register_operand" "") 300 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
297 (mem:SI (plus:SI (match_dup 5) 301 (mem:SI (plus:SI (match_dup 5)
298 (const_int -8)))) 302 (const_int -8))))
299 (set (match_operand:SI 4 "arm_hard_register_operand" "") 303 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
300 (mem:SI (plus:SI (match_dup 5) 304 (mem:SI (plus:SI (match_dup 5)
301 (const_int -4))))])] 305 (const_int -4))))])]
302 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 306 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
303 "ldm%(db%)\t%5, {%1, %2, %3, %4}" 307 "ldmdb%?\t%5, {%1, %2, %3, %4}"
304 [(set_attr "type" "load4") 308 [(set_attr "type" "load_16")
305 (set_attr "predicable" "yes")]) 309 (set_attr "predicable" "yes")
310 (set_attr "predicable_short_it" "no")])
306 311
307 (define_insn "*ldm4_db_update" 312 (define_insn "*ldm4_db_update"
308 [(match_parallel 0 "load_multiple_operation" 313 [(match_parallel 0 "load_multiple_operation"
309 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 314 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
310 (plus:SI (match_dup 5) (const_int -16))) 315 (plus:SI (match_dup 5) (const_int -16)))
311 (set (match_operand:SI 1 "arm_hard_register_operand" "") 316 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
312 (mem:SI (plus:SI (match_dup 5) 317 (mem:SI (plus:SI (match_dup 5)
313 (const_int -16)))) 318 (const_int -16))))
314 (set (match_operand:SI 2 "arm_hard_register_operand" "") 319 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
315 (mem:SI (plus:SI (match_dup 5) 320 (mem:SI (plus:SI (match_dup 5)
316 (const_int -12)))) 321 (const_int -12))))
317 (set (match_operand:SI 3 "arm_hard_register_operand" "") 322 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
318 (mem:SI (plus:SI (match_dup 5) 323 (mem:SI (plus:SI (match_dup 5)
319 (const_int -8)))) 324 (const_int -8))))
320 (set (match_operand:SI 4 "arm_hard_register_operand" "") 325 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
321 (mem:SI (plus:SI (match_dup 5) 326 (mem:SI (plus:SI (match_dup 5)
322 (const_int -4))))])] 327 (const_int -4))))])]
323 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 328 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
324 "ldm%(db%)\t%5!, {%1, %2, %3, %4}" 329 "ldmdb%?\t%5!, {%1, %2, %3, %4}"
325 [(set_attr "type" "load4") 330 [(set_attr "type" "load_16")
326 (set_attr "predicable" "yes")]) 331 (set_attr "predicable" "yes")
332 (set_attr "predicable_short_it" "no")])
327 333
328 (define_insn "*stm4_db" 334 (define_insn "*stm4_db"
329 [(match_parallel 0 "store_multiple_operation" 335 [(match_parallel 0 "store_multiple_operation"
330 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) 336 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))
331 (match_operand:SI 1 "arm_hard_register_operand" "")) 337 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
332 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 338 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
333 (match_operand:SI 2 "arm_hard_register_operand" "")) 339 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
334 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 340 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
335 (match_operand:SI 3 "arm_hard_register_operand" "")) 341 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
336 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 342 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
337 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 343 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
338 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 344 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
339 "stm%(db%)\t%5, {%1, %2, %3, %4}" 345 "stmdb%?\t%5, {%1, %2, %3, %4}"
340 [(set_attr "type" "store4") 346 [(set_attr "type" "store_16")
341 (set_attr "predicable" "yes")]) 347 (set_attr "predicable" "yes")
348 (set_attr "predicable_short_it" "no")])
342 349
343 (define_insn "*stm4_db_update" 350 (define_insn "*stm4_db_update"
344 [(match_parallel 0 "store_multiple_operation" 351 [(match_parallel 0 "store_multiple_operation"
345 [(set (match_operand:SI 5 "s_register_operand" "+&rk") 352 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
346 (plus:SI (match_dup 5) (const_int -16))) 353 (plus:SI (match_dup 5) (const_int -16)))
347 (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) 354 (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
348 (match_operand:SI 1 "arm_hard_register_operand" "")) 355 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
349 (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) 356 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
350 (match_operand:SI 2 "arm_hard_register_operand" "")) 357 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
351 (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) 358 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
352 (match_operand:SI 3 "arm_hard_register_operand" "")) 359 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
353 (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) 360 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
354 (match_operand:SI 4 "arm_hard_register_operand" ""))])] 361 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
355 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" 362 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
356 "stm%(db%)\t%5!, {%1, %2, %3, %4}" 363 "stmdb%?\t%5!, {%1, %2, %3, %4}"
357 [(set_attr "type" "store4") 364 [(set_attr "type" "store_16")
358 (set_attr "predicable" "yes")]) 365 (set_attr "predicable" "yes")
366 (set_attr "predicable_short_it" "no")])
359 367
360 (define_peephole2 368 (define_peephole2
361 [(set (match_operand:SI 0 "s_register_operand" "") 369 [(set (match_operand:SI 0 "s_register_operand" "")
362 (match_operand:SI 4 "memory_operand" "")) 370 (match_operand:SI 4 "memory_operand" ""))
363 (set (match_operand:SI 1 "s_register_operand" "") 371 (set (match_operand:SI 1 "s_register_operand" "")
462 DONE; 470 DONE;
463 else 471 else
464 FAIL; 472 FAIL;
465 }) 473 })
466 474
467 (define_insn "*ldm3_ia" 475 (define_insn "*ldm3_"
468 [(match_parallel 0 "load_multiple_operation" 476 [(match_parallel 0 "load_multiple_operation"
469 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 477 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
470 (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) 478 (mem:SI (match_operand:SI 4 "s_register_operand" "rk")))
471 (set (match_operand:SI 2 "arm_hard_register_operand" "") 479 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
472 (mem:SI (plus:SI (match_dup 4) 480 (mem:SI (plus:SI (match_dup 4)
473 (const_int 4)))) 481 (const_int 4))))
474 (set (match_operand:SI 3 "arm_hard_register_operand" "") 482 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
475 (mem:SI (plus:SI (match_dup 4) 483 (mem:SI (plus:SI (match_dup 4)
476 (const_int 8))))])] 484 (const_int 8))))])]
477 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 485 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
478 "ldm%(ia%)\t%4, {%1, %2, %3}" 486 "ldm%?\t%4, {%1, %2, %3}"
479 [(set_attr "type" "load3") 487 [(set_attr "type" "load_12")
480 (set_attr "predicable" "yes")]) 488 (set_attr "predicable" "yes")
489 (set_attr "predicable_short_it" "no")])
481 490
482 (define_insn "*thumb_ldm3_ia" 491 (define_insn "*thumb_ldm3_ia"
483 [(match_parallel 0 "load_multiple_operation" 492 [(match_parallel 0 "load_multiple_operation"
484 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 493 [(set (match_operand:SI 1 "low_register_operand" "")
485 (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) 494 (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
486 (set (match_operand:SI 2 "arm_hard_register_operand" "") 495 (set (match_operand:SI 2 "low_register_operand" "")
487 (mem:SI (plus:SI (match_dup 4) 496 (mem:SI (plus:SI (match_dup 4)
488 (const_int 4)))) 497 (const_int 4))))
489 (set (match_operand:SI 3 "arm_hard_register_operand" "") 498 (set (match_operand:SI 3 "low_register_operand" "")
490 (mem:SI (plus:SI (match_dup 4) 499 (mem:SI (plus:SI (match_dup 4)
491 (const_int 8))))])] 500 (const_int 8))))])]
492 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 501 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
493 "ldm%(ia%)\t%4, {%1, %2, %3}" 502 "ldmia\t%4, {%1, %2, %3}"
494 [(set_attr "type" "load3")]) 503 [(set_attr "type" "load_12")])
495 504
496 (define_insn "*ldm3_ia_update" 505 (define_insn "*ldm3_ia_update"
497 [(match_parallel 0 "load_multiple_operation" 506 [(match_parallel 0 "load_multiple_operation"
498 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 507 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
499 (plus:SI (match_dup 4) (const_int 12))) 508 (plus:SI (match_dup 4) (const_int 12)))
500 (set (match_operand:SI 1 "arm_hard_register_operand" "") 509 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
501 (mem:SI (match_dup 4))) 510 (mem:SI (match_dup 4)))
502 (set (match_operand:SI 2 "arm_hard_register_operand" "") 511 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
503 (mem:SI (plus:SI (match_dup 4) 512 (mem:SI (plus:SI (match_dup 4)
504 (const_int 4)))) 513 (const_int 4))))
505 (set (match_operand:SI 3 "arm_hard_register_operand" "") 514 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
506 (mem:SI (plus:SI (match_dup 4) 515 (mem:SI (plus:SI (match_dup 4)
507 (const_int 8))))])] 516 (const_int 8))))])]
508 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 517 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
509 "ldm%(ia%)\t%4!, {%1, %2, %3}" 518 "ldmia%?\t%4!, {%1, %2, %3}"
510 [(set_attr "type" "load3") 519 [(set_attr "type" "load_12")
511 (set_attr "predicable" "yes")]) 520 (set_attr "predicable" "yes")
521 (set_attr "predicable_short_it" "no")])
512 522
513 (define_insn "*thumb_ldm3_ia_update" 523 (define_insn "*thumb_ldm3_ia_update"
514 [(match_parallel 0 "load_multiple_operation" 524 [(match_parallel 0 "load_multiple_operation"
515 [(set (match_operand:SI 4 "s_register_operand" "+&l") 525 [(set (match_operand:SI 4 "s_register_operand" "+&l")
516 (plus:SI (match_dup 4) (const_int 12))) 526 (plus:SI (match_dup 4) (const_int 12)))
517 (set (match_operand:SI 1 "arm_hard_register_operand" "") 527 (set (match_operand:SI 1 "low_register_operand" "")
518 (mem:SI (match_dup 4))) 528 (mem:SI (match_dup 4)))
519 (set (match_operand:SI 2 "arm_hard_register_operand" "") 529 (set (match_operand:SI 2 "low_register_operand" "")
520 (mem:SI (plus:SI (match_dup 4) 530 (mem:SI (plus:SI (match_dup 4)
521 (const_int 4)))) 531 (const_int 4))))
522 (set (match_operand:SI 3 "arm_hard_register_operand" "") 532 (set (match_operand:SI 3 "low_register_operand" "")
523 (mem:SI (plus:SI (match_dup 4) 533 (mem:SI (plus:SI (match_dup 4)
524 (const_int 8))))])] 534 (const_int 8))))])]
525 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 535 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
526 "ldm%(ia%)\t%4!, {%1, %2, %3}" 536 "ldmia\t%4!, {%1, %2, %3}"
527 [(set_attr "type" "load3")]) 537 [(set_attr "type" "load_12")])
528 538
529 (define_insn "*stm3_ia" 539 (define_insn "*stm3_"
530 [(match_parallel 0 "store_multiple_operation" 540 [(match_parallel 0 "store_multiple_operation"
531 [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) 541 [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))
532 (match_operand:SI 1 "arm_hard_register_operand" "")) 542 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
533 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 543 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
534 (match_operand:SI 2 "arm_hard_register_operand" "")) 544 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
535 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 545 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
536 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 546 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
537 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 547 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
538 "stm%(ia%)\t%4, {%1, %2, %3}" 548 "stm%?\t%4, {%1, %2, %3}"
539 [(set_attr "type" "store3") 549 [(set_attr "type" "store_12")
540 (set_attr "predicable" "yes")]) 550 (set_attr "predicable" "yes")
551 (set_attr "predicable_short_it" "no")])
541 552
542 (define_insn "*stm3_ia_update" 553 (define_insn "*stm3_ia_update"
543 [(match_parallel 0 "store_multiple_operation" 554 [(match_parallel 0 "store_multiple_operation"
544 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 555 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
545 (plus:SI (match_dup 4) (const_int 12))) 556 (plus:SI (match_dup 4) (const_int 12)))
546 (set (mem:SI (match_dup 4)) 557 (set (mem:SI (match_dup 4))
547 (match_operand:SI 1 "arm_hard_register_operand" "")) 558 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
548 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 559 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
549 (match_operand:SI 2 "arm_hard_register_operand" "")) 560 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
550 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 561 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
551 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 562 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
552 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 563 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
553 "stm%(ia%)\t%4!, {%1, %2, %3}" 564 "stmia%?\t%4!, {%1, %2, %3}"
554 [(set_attr "type" "store3") 565 [(set_attr "type" "store_12")
555 (set_attr "predicable" "yes")]) 566 (set_attr "predicable" "yes")
567 (set_attr "predicable_short_it" "no")])
556 568
557 (define_insn "*thumb_stm3_ia_update" 569 (define_insn "*thumb_stm3_ia_update"
558 [(match_parallel 0 "store_multiple_operation" 570 [(match_parallel 0 "store_multiple_operation"
559 [(set (match_operand:SI 4 "s_register_operand" "+&l") 571 [(set (match_operand:SI 4 "s_register_operand" "+&l")
560 (plus:SI (match_dup 4) (const_int 12))) 572 (plus:SI (match_dup 4) (const_int 12)))
561 (set (mem:SI (match_dup 4)) 573 (set (mem:SI (match_dup 4))
562 (match_operand:SI 1 "arm_hard_register_operand" "")) 574 (match_operand:SI 1 "low_register_operand" ""))
563 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 575 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
564 (match_operand:SI 2 "arm_hard_register_operand" "")) 576 (match_operand:SI 2 "low_register_operand" ""))
565 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 577 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
566 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 578 (match_operand:SI 3 "low_register_operand" ""))])]
567 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" 579 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
568 "stm%(ia%)\t%4!, {%1, %2, %3}" 580 "stmia\t%4!, {%1, %2, %3}"
569 [(set_attr "type" "store3")]) 581 [(set_attr "type" "store_12")])
570 582
571 (define_insn "*ldm3_ib" 583 (define_insn "*ldm3_ib"
572 [(match_parallel 0 "load_multiple_operation" 584 [(match_parallel 0 "load_multiple_operation"
573 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 585 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
574 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 586 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
575 (const_int 4)))) 587 (const_int 4))))
576 (set (match_operand:SI 2 "arm_hard_register_operand" "") 588 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
577 (mem:SI (plus:SI (match_dup 4) 589 (mem:SI (plus:SI (match_dup 4)
578 (const_int 8)))) 590 (const_int 8))))
579 (set (match_operand:SI 3 "arm_hard_register_operand" "") 591 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
580 (mem:SI (plus:SI (match_dup 4) 592 (mem:SI (plus:SI (match_dup 4)
581 (const_int 12))))])] 593 (const_int 12))))])]
582 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 594 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
583 "ldm%(ib%)\t%4, {%1, %2, %3}" 595 "ldmib%?\t%4, {%1, %2, %3}"
584 [(set_attr "type" "load3") 596 [(set_attr "type" "load_12")
585 (set_attr "predicable" "yes")]) 597 (set_attr "predicable" "yes")])
586 598
587 (define_insn "*ldm3_ib_update" 599 (define_insn "*ldm3_ib_update"
588 [(match_parallel 0 "load_multiple_operation" 600 [(match_parallel 0 "load_multiple_operation"
589 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 601 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
590 (plus:SI (match_dup 4) (const_int 12))) 602 (plus:SI (match_dup 4) (const_int 12)))
591 (set (match_operand:SI 1 "arm_hard_register_operand" "") 603 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
592 (mem:SI (plus:SI (match_dup 4) 604 (mem:SI (plus:SI (match_dup 4)
593 (const_int 4)))) 605 (const_int 4))))
594 (set (match_operand:SI 2 "arm_hard_register_operand" "") 606 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
595 (mem:SI (plus:SI (match_dup 4) 607 (mem:SI (plus:SI (match_dup 4)
596 (const_int 8)))) 608 (const_int 8))))
597 (set (match_operand:SI 3 "arm_hard_register_operand" "") 609 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
598 (mem:SI (plus:SI (match_dup 4) 610 (mem:SI (plus:SI (match_dup 4)
599 (const_int 12))))])] 611 (const_int 12))))])]
600 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 612 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
601 "ldm%(ib%)\t%4!, {%1, %2, %3}" 613 "ldmib%?\t%4!, {%1, %2, %3}"
602 [(set_attr "type" "load3") 614 [(set_attr "type" "load_12")
603 (set_attr "predicable" "yes")]) 615 (set_attr "predicable" "yes")])
604 616
605 (define_insn "*stm3_ib" 617 (define_insn "*stm3_ib"
606 [(match_parallel 0 "store_multiple_operation" 618 [(match_parallel 0 "store_multiple_operation"
607 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) 619 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))
608 (match_operand:SI 1 "arm_hard_register_operand" "")) 620 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
609 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 621 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
610 (match_operand:SI 2 "arm_hard_register_operand" "")) 622 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
611 (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) 623 (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
612 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 624 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
613 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 625 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
614 "stm%(ib%)\t%4, {%1, %2, %3}" 626 "stmib%?\t%4, {%1, %2, %3}"
615 [(set_attr "type" "store3") 627 [(set_attr "type" "store_12")
616 (set_attr "predicable" "yes")]) 628 (set_attr "predicable" "yes")])
617 629
618 (define_insn "*stm3_ib_update" 630 (define_insn "*stm3_ib_update"
619 [(match_parallel 0 "store_multiple_operation" 631 [(match_parallel 0 "store_multiple_operation"
620 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 632 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
621 (plus:SI (match_dup 4) (const_int 12))) 633 (plus:SI (match_dup 4) (const_int 12)))
622 (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) 634 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
623 (match_operand:SI 1 "arm_hard_register_operand" "")) 635 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
624 (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) 636 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
625 (match_operand:SI 2 "arm_hard_register_operand" "")) 637 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
626 (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) 638 (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
627 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 639 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
628 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 640 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
629 "stm%(ib%)\t%4!, {%1, %2, %3}" 641 "stmib%?\t%4!, {%1, %2, %3}"
630 [(set_attr "type" "store3") 642 [(set_attr "type" "store_12")
631 (set_attr "predicable" "yes")]) 643 (set_attr "predicable" "yes")])
632 644
633 (define_insn "*ldm3_da" 645 (define_insn "*ldm3_da"
634 [(match_parallel 0 "load_multiple_operation" 646 [(match_parallel 0 "load_multiple_operation"
635 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 647 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
636 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 648 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
637 (const_int -8)))) 649 (const_int -8))))
638 (set (match_operand:SI 2 "arm_hard_register_operand" "") 650 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
639 (mem:SI (plus:SI (match_dup 4) 651 (mem:SI (plus:SI (match_dup 4)
640 (const_int -4)))) 652 (const_int -4))))
641 (set (match_operand:SI 3 "arm_hard_register_operand" "") 653 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
642 (mem:SI (match_dup 4)))])] 654 (mem:SI (match_dup 4)))])]
643 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 655 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
644 "ldm%(da%)\t%4, {%1, %2, %3}" 656 "ldmda%?\t%4, {%1, %2, %3}"
645 [(set_attr "type" "load3") 657 [(set_attr "type" "load_12")
646 (set_attr "predicable" "yes")]) 658 (set_attr "predicable" "yes")])
647 659
648 (define_insn "*ldm3_da_update" 660 (define_insn "*ldm3_da_update"
649 [(match_parallel 0 "load_multiple_operation" 661 [(match_parallel 0 "load_multiple_operation"
650 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 662 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
651 (plus:SI (match_dup 4) (const_int -12))) 663 (plus:SI (match_dup 4) (const_int -12)))
652 (set (match_operand:SI 1 "arm_hard_register_operand" "") 664 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
653 (mem:SI (plus:SI (match_dup 4) 665 (mem:SI (plus:SI (match_dup 4)
654 (const_int -8)))) 666 (const_int -8))))
655 (set (match_operand:SI 2 "arm_hard_register_operand" "") 667 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
656 (mem:SI (plus:SI (match_dup 4) 668 (mem:SI (plus:SI (match_dup 4)
657 (const_int -4)))) 669 (const_int -4))))
658 (set (match_operand:SI 3 "arm_hard_register_operand" "") 670 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
659 (mem:SI (match_dup 4)))])] 671 (mem:SI (match_dup 4)))])]
660 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 672 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
661 "ldm%(da%)\t%4!, {%1, %2, %3}" 673 "ldmda%?\t%4!, {%1, %2, %3}"
662 [(set_attr "type" "load3") 674 [(set_attr "type" "load_12")
663 (set_attr "predicable" "yes")]) 675 (set_attr "predicable" "yes")])
664 676
665 (define_insn "*stm3_da" 677 (define_insn "*stm3_da"
666 [(match_parallel 0 "store_multiple_operation" 678 [(match_parallel 0 "store_multiple_operation"
667 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) 679 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))
668 (match_operand:SI 1 "arm_hard_register_operand" "")) 680 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
669 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 681 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
670 (match_operand:SI 2 "arm_hard_register_operand" "")) 682 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
671 (set (mem:SI (match_dup 4)) 683 (set (mem:SI (match_dup 4))
672 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 684 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
673 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 685 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
674 "stm%(da%)\t%4, {%1, %2, %3}" 686 "stmda%?\t%4, {%1, %2, %3}"
675 [(set_attr "type" "store3") 687 [(set_attr "type" "store_12")
676 (set_attr "predicable" "yes")]) 688 (set_attr "predicable" "yes")])
677 689
678 (define_insn "*stm3_da_update" 690 (define_insn "*stm3_da_update"
679 [(match_parallel 0 "store_multiple_operation" 691 [(match_parallel 0 "store_multiple_operation"
680 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 692 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
681 (plus:SI (match_dup 4) (const_int -12))) 693 (plus:SI (match_dup 4) (const_int -12)))
682 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 694 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
683 (match_operand:SI 1 "arm_hard_register_operand" "")) 695 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
684 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 696 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
685 (match_operand:SI 2 "arm_hard_register_operand" "")) 697 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
686 (set (mem:SI (match_dup 4)) 698 (set (mem:SI (match_dup 4))
687 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 699 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
688 "TARGET_ARM && XVECLEN (operands[0], 0) == 4" 700 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
689 "stm%(da%)\t%4!, {%1, %2, %3}" 701 "stmda%?\t%4!, {%1, %2, %3}"
690 [(set_attr "type" "store3") 702 [(set_attr "type" "store_12")
691 (set_attr "predicable" "yes")]) 703 (set_attr "predicable" "yes")])
692 704
693 (define_insn "*ldm3_db" 705 (define_insn "*ldm3_db"
694 [(match_parallel 0 "load_multiple_operation" 706 [(match_parallel 0 "load_multiple_operation"
695 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 707 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
696 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") 708 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
697 (const_int -12)))) 709 (const_int -12))))
698 (set (match_operand:SI 2 "arm_hard_register_operand" "") 710 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
699 (mem:SI (plus:SI (match_dup 4) 711 (mem:SI (plus:SI (match_dup 4)
700 (const_int -8)))) 712 (const_int -8))))
701 (set (match_operand:SI 3 "arm_hard_register_operand" "") 713 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
702 (mem:SI (plus:SI (match_dup 4) 714 (mem:SI (plus:SI (match_dup 4)
703 (const_int -4))))])] 715 (const_int -4))))])]
704 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 716 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
705 "ldm%(db%)\t%4, {%1, %2, %3}" 717 "ldmdb%?\t%4, {%1, %2, %3}"
706 [(set_attr "type" "load3") 718 [(set_attr "type" "load_12")
707 (set_attr "predicable" "yes")]) 719 (set_attr "predicable" "yes")
720 (set_attr "predicable_short_it" "no")])
708 721
709 (define_insn "*ldm3_db_update" 722 (define_insn "*ldm3_db_update"
710 [(match_parallel 0 "load_multiple_operation" 723 [(match_parallel 0 "load_multiple_operation"
711 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 724 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
712 (plus:SI (match_dup 4) (const_int -12))) 725 (plus:SI (match_dup 4) (const_int -12)))
713 (set (match_operand:SI 1 "arm_hard_register_operand" "") 726 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
714 (mem:SI (plus:SI (match_dup 4) 727 (mem:SI (plus:SI (match_dup 4)
715 (const_int -12)))) 728 (const_int -12))))
716 (set (match_operand:SI 2 "arm_hard_register_operand" "") 729 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
717 (mem:SI (plus:SI (match_dup 4) 730 (mem:SI (plus:SI (match_dup 4)
718 (const_int -8)))) 731 (const_int -8))))
719 (set (match_operand:SI 3 "arm_hard_register_operand" "") 732 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
720 (mem:SI (plus:SI (match_dup 4) 733 (mem:SI (plus:SI (match_dup 4)
721 (const_int -4))))])] 734 (const_int -4))))])]
722 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 735 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
723 "ldm%(db%)\t%4!, {%1, %2, %3}" 736 "ldmdb%?\t%4!, {%1, %2, %3}"
724 [(set_attr "type" "load3") 737 [(set_attr "type" "load_12")
725 (set_attr "predicable" "yes")]) 738 (set_attr "predicable" "yes")
739 (set_attr "predicable_short_it" "no")])
726 740
727 (define_insn "*stm3_db" 741 (define_insn "*stm3_db"
728 [(match_parallel 0 "store_multiple_operation" 742 [(match_parallel 0 "store_multiple_operation"
729 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) 743 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))
730 (match_operand:SI 1 "arm_hard_register_operand" "")) 744 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
731 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 745 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
732 (match_operand:SI 2 "arm_hard_register_operand" "")) 746 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
733 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 747 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
734 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 748 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
735 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 749 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
736 "stm%(db%)\t%4, {%1, %2, %3}" 750 "stmdb%?\t%4, {%1, %2, %3}"
737 [(set_attr "type" "store3") 751 [(set_attr "type" "store_12")
738 (set_attr "predicable" "yes")]) 752 (set_attr "predicable" "yes")
753 (set_attr "predicable_short_it" "no")])
739 754
740 (define_insn "*stm3_db_update" 755 (define_insn "*stm3_db_update"
741 [(match_parallel 0 "store_multiple_operation" 756 [(match_parallel 0 "store_multiple_operation"
742 [(set (match_operand:SI 4 "s_register_operand" "+&rk") 757 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
743 (plus:SI (match_dup 4) (const_int -12))) 758 (plus:SI (match_dup 4) (const_int -12)))
744 (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) 759 (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
745 (match_operand:SI 1 "arm_hard_register_operand" "")) 760 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
746 (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) 761 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
747 (match_operand:SI 2 "arm_hard_register_operand" "")) 762 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
748 (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) 763 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
749 (match_operand:SI 3 "arm_hard_register_operand" ""))])] 764 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
750 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" 765 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
751 "stm%(db%)\t%4!, {%1, %2, %3}" 766 "stmdb%?\t%4!, {%1, %2, %3}"
752 [(set_attr "type" "store3") 767 [(set_attr "type" "store_12")
753 (set_attr "predicable" "yes")]) 768 (set_attr "predicable" "yes")
769 (set_attr "predicable_short_it" "no")])
754 770
755 (define_peephole2 771 (define_peephole2
756 [(set (match_operand:SI 0 "s_register_operand" "") 772 [(set (match_operand:SI 0 "s_register_operand" "")
757 (match_operand:SI 3 "memory_operand" "")) 773 (match_operand:SI 3 "memory_operand" ""))
758 (set (match_operand:SI 1 "s_register_operand" "") 774 (set (match_operand:SI 1 "s_register_operand" "")
843 DONE; 859 DONE;
844 else 860 else
845 FAIL; 861 FAIL;
846 }) 862 })
847 863
848 (define_insn "*ldm2_ia" 864 (define_insn "*ldm2_"
849 [(match_parallel 0 "load_multiple_operation" 865 [(match_parallel 0 "load_multiple_operation"
850 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 866 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
851 (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) 867 (mem:SI (match_operand:SI 3 "s_register_operand" "rk")))
852 (set (match_operand:SI 2 "arm_hard_register_operand" "") 868 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
853 (mem:SI (plus:SI (match_dup 3) 869 (mem:SI (plus:SI (match_dup 3)
854 (const_int 4))))])] 870 (const_int 4))))])]
855 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 871 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
856 "ldm%(ia%)\t%3, {%1, %2}" 872 "ldm%?\t%3, {%1, %2}"
857 [(set_attr "type" "load2") 873 [(set_attr "type" "load_8")
858 (set_attr "predicable" "yes")]) 874 (set_attr "predicable" "yes")
875 (set_attr "predicable_short_it" "no")])
859 876
860 (define_insn "*thumb_ldm2_ia" 877 (define_insn "*thumb_ldm2_ia"
861 [(match_parallel 0 "load_multiple_operation" 878 [(match_parallel 0 "load_multiple_operation"
862 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 879 [(set (match_operand:SI 1 "low_register_operand" "")
863 (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) 880 (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
864 (set (match_operand:SI 2 "arm_hard_register_operand" "") 881 (set (match_operand:SI 2 "low_register_operand" "")
865 (mem:SI (plus:SI (match_dup 3) 882 (mem:SI (plus:SI (match_dup 3)
866 (const_int 4))))])] 883 (const_int 4))))])]
867 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" 884 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
868 "ldm%(ia%)\t%3, {%1, %2}" 885 "ldmia\t%3, {%1, %2}"
869 [(set_attr "type" "load2")]) 886 [(set_attr "type" "load_8")])
870 887
871 (define_insn "*ldm2_ia_update" 888 (define_insn "*ldm2_ia_update"
872 [(match_parallel 0 "load_multiple_operation" 889 [(match_parallel 0 "load_multiple_operation"
873 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 890 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
874 (plus:SI (match_dup 3) (const_int 8))) 891 (plus:SI (match_dup 3) (const_int 8)))
875 (set (match_operand:SI 1 "arm_hard_register_operand" "") 892 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
876 (mem:SI (match_dup 3))) 893 (mem:SI (match_dup 3)))
877 (set (match_operand:SI 2 "arm_hard_register_operand" "") 894 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
878 (mem:SI (plus:SI (match_dup 3) 895 (mem:SI (plus:SI (match_dup 3)
879 (const_int 4))))])] 896 (const_int 4))))])]
880 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 897 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
881 "ldm%(ia%)\t%3!, {%1, %2}" 898 "ldmia%?\t%3!, {%1, %2}"
882 [(set_attr "type" "load2") 899 [(set_attr "type" "load_8")
883 (set_attr "predicable" "yes")]) 900 (set_attr "predicable" "yes")
901 (set_attr "predicable_short_it" "no")])
884 902
885 (define_insn "*thumb_ldm2_ia_update" 903 (define_insn "*thumb_ldm2_ia_update"
886 [(match_parallel 0 "load_multiple_operation" 904 [(match_parallel 0 "load_multiple_operation"
887 [(set (match_operand:SI 3 "s_register_operand" "+&l") 905 [(set (match_operand:SI 3 "s_register_operand" "+&l")
888 (plus:SI (match_dup 3) (const_int 8))) 906 (plus:SI (match_dup 3) (const_int 8)))
889 (set (match_operand:SI 1 "arm_hard_register_operand" "") 907 (set (match_operand:SI 1 "low_register_operand" "")
890 (mem:SI (match_dup 3))) 908 (mem:SI (match_dup 3)))
891 (set (match_operand:SI 2 "arm_hard_register_operand" "") 909 (set (match_operand:SI 2 "low_register_operand" "")
892 (mem:SI (plus:SI (match_dup 3) 910 (mem:SI (plus:SI (match_dup 3)
893 (const_int 4))))])] 911 (const_int 4))))])]
894 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 912 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
895 "ldm%(ia%)\t%3!, {%1, %2}" 913 "ldmia\t%3!, {%1, %2}"
896 [(set_attr "type" "load2")]) 914 [(set_attr "type" "load_8")])
897 915
898 (define_insn "*stm2_ia" 916 (define_insn "*stm2_"
899 [(match_parallel 0 "store_multiple_operation" 917 [(match_parallel 0 "store_multiple_operation"
900 [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) 918 [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))
901 (match_operand:SI 1 "arm_hard_register_operand" "")) 919 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
902 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 920 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
903 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 921 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
904 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 922 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
905 "stm%(ia%)\t%3, {%1, %2}" 923 "stm%?\t%3, {%1, %2}"
906 [(set_attr "type" "store2") 924 [(set_attr "type" "store_8")
907 (set_attr "predicable" "yes")]) 925 (set_attr "predicable" "yes")
926 (set_attr "predicable_short_it" "no")])
908 927
909 (define_insn "*stm2_ia_update" 928 (define_insn "*stm2_ia_update"
910 [(match_parallel 0 "store_multiple_operation" 929 [(match_parallel 0 "store_multiple_operation"
911 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 930 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
912 (plus:SI (match_dup 3) (const_int 8))) 931 (plus:SI (match_dup 3) (const_int 8)))
913 (set (mem:SI (match_dup 3)) 932 (set (mem:SI (match_dup 3))
914 (match_operand:SI 1 "arm_hard_register_operand" "")) 933 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
915 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 934 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
916 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 935 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
917 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 936 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
918 "stm%(ia%)\t%3!, {%1, %2}" 937 "stmia%?\t%3!, {%1, %2}"
919 [(set_attr "type" "store2") 938 [(set_attr "type" "store_8")
920 (set_attr "predicable" "yes")]) 939 (set_attr "predicable" "yes")
940 (set_attr "predicable_short_it" "no")])
921 941
922 (define_insn "*thumb_stm2_ia_update" 942 (define_insn "*thumb_stm2_ia_update"
923 [(match_parallel 0 "store_multiple_operation" 943 [(match_parallel 0 "store_multiple_operation"
924 [(set (match_operand:SI 3 "s_register_operand" "+&l") 944 [(set (match_operand:SI 3 "s_register_operand" "+&l")
925 (plus:SI (match_dup 3) (const_int 8))) 945 (plus:SI (match_dup 3) (const_int 8)))
926 (set (mem:SI (match_dup 3)) 946 (set (mem:SI (match_dup 3))
927 (match_operand:SI 1 "arm_hard_register_operand" "")) 947 (match_operand:SI 1 "low_register_operand" ""))
928 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 948 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
929 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 949 (match_operand:SI 2 "low_register_operand" ""))])]
930 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" 950 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
931 "stm%(ia%)\t%3!, {%1, %2}" 951 "stmia\t%3!, {%1, %2}"
932 [(set_attr "type" "store2")]) 952 [(set_attr "type" "store_8")])
933 953
934 (define_insn "*ldm2_ib" 954 (define_insn "*ldm2_ib"
935 [(match_parallel 0 "load_multiple_operation" 955 [(match_parallel 0 "load_multiple_operation"
936 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 956 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
937 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 957 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
938 (const_int 4)))) 958 (const_int 4))))
939 (set (match_operand:SI 2 "arm_hard_register_operand" "") 959 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
940 (mem:SI (plus:SI (match_dup 3) 960 (mem:SI (plus:SI (match_dup 3)
941 (const_int 8))))])] 961 (const_int 8))))])]
942 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 962 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
943 "ldm%(ib%)\t%3, {%1, %2}" 963 "ldmib%?\t%3, {%1, %2}"
944 [(set_attr "type" "load2") 964 [(set_attr "type" "load_8")
945 (set_attr "predicable" "yes")]) 965 (set_attr "predicable" "yes")])
946 966
947 (define_insn "*ldm2_ib_update" 967 (define_insn "*ldm2_ib_update"
948 [(match_parallel 0 "load_multiple_operation" 968 [(match_parallel 0 "load_multiple_operation"
949 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 969 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
950 (plus:SI (match_dup 3) (const_int 8))) 970 (plus:SI (match_dup 3) (const_int 8)))
951 (set (match_operand:SI 1 "arm_hard_register_operand" "") 971 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
952 (mem:SI (plus:SI (match_dup 3) 972 (mem:SI (plus:SI (match_dup 3)
953 (const_int 4)))) 973 (const_int 4))))
954 (set (match_operand:SI 2 "arm_hard_register_operand" "") 974 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
955 (mem:SI (plus:SI (match_dup 3) 975 (mem:SI (plus:SI (match_dup 3)
956 (const_int 8))))])] 976 (const_int 8))))])]
957 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 977 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
958 "ldm%(ib%)\t%3!, {%1, %2}" 978 "ldmib%?\t%3!, {%1, %2}"
959 [(set_attr "type" "load2") 979 [(set_attr "type" "load_8")
960 (set_attr "predicable" "yes")]) 980 (set_attr "predicable" "yes")])
961 981
962 (define_insn "*stm2_ib" 982 (define_insn "*stm2_ib"
963 [(match_parallel 0 "store_multiple_operation" 983 [(match_parallel 0 "store_multiple_operation"
964 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) 984 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))
965 (match_operand:SI 1 "arm_hard_register_operand" "")) 985 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
966 (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) 986 (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
967 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 987 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
968 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 988 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
969 "stm%(ib%)\t%3, {%1, %2}" 989 "stmib%?\t%3, {%1, %2}"
970 [(set_attr "type" "store2") 990 [(set_attr "type" "store_8")
971 (set_attr "predicable" "yes")]) 991 (set_attr "predicable" "yes")])
972 992
973 (define_insn "*stm2_ib_update" 993 (define_insn "*stm2_ib_update"
974 [(match_parallel 0 "store_multiple_operation" 994 [(match_parallel 0 "store_multiple_operation"
975 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 995 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
976 (plus:SI (match_dup 3) (const_int 8))) 996 (plus:SI (match_dup 3) (const_int 8)))
977 (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) 997 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
978 (match_operand:SI 1 "arm_hard_register_operand" "")) 998 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
979 (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) 999 (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
980 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 1000 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
981 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 1001 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
982 "stm%(ib%)\t%3!, {%1, %2}" 1002 "stmib%?\t%3!, {%1, %2}"
983 [(set_attr "type" "store2") 1003 [(set_attr "type" "store_8")
984 (set_attr "predicable" "yes")]) 1004 (set_attr "predicable" "yes")])
985 1005
986 (define_insn "*ldm2_da" 1006 (define_insn "*ldm2_da"
987 [(match_parallel 0 "load_multiple_operation" 1007 [(match_parallel 0 "load_multiple_operation"
988 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 1008 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
989 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 1009 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
990 (const_int -4)))) 1010 (const_int -4))))
991 (set (match_operand:SI 2 "arm_hard_register_operand" "") 1011 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
992 (mem:SI (match_dup 3)))])] 1012 (mem:SI (match_dup 3)))])]
993 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 1013 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
994 "ldm%(da%)\t%3, {%1, %2}" 1014 "ldmda%?\t%3, {%1, %2}"
995 [(set_attr "type" "load2") 1015 [(set_attr "type" "load_8")
996 (set_attr "predicable" "yes")]) 1016 (set_attr "predicable" "yes")])
997 1017
998 (define_insn "*ldm2_da_update" 1018 (define_insn "*ldm2_da_update"
999 [(match_parallel 0 "load_multiple_operation" 1019 [(match_parallel 0 "load_multiple_operation"
1000 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1020 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1001 (plus:SI (match_dup 3) (const_int -8))) 1021 (plus:SI (match_dup 3) (const_int -8)))
1002 (set (match_operand:SI 1 "arm_hard_register_operand" "") 1022 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1003 (mem:SI (plus:SI (match_dup 3) 1023 (mem:SI (plus:SI (match_dup 3)
1004 (const_int -4)))) 1024 (const_int -4))))
1005 (set (match_operand:SI 2 "arm_hard_register_operand" "") 1025 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1006 (mem:SI (match_dup 3)))])] 1026 (mem:SI (match_dup 3)))])]
1007 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 1027 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
1008 "ldm%(da%)\t%3!, {%1, %2}" 1028 "ldmda%?\t%3!, {%1, %2}"
1009 [(set_attr "type" "load2") 1029 [(set_attr "type" "load_8")
1010 (set_attr "predicable" "yes")]) 1030 (set_attr "predicable" "yes")])
1011 1031
1012 (define_insn "*stm2_da" 1032 (define_insn "*stm2_da"
1013 [(match_parallel 0 "store_multiple_operation" 1033 [(match_parallel 0 "store_multiple_operation"
1014 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) 1034 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))
1015 (match_operand:SI 1 "arm_hard_register_operand" "")) 1035 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1016 (set (mem:SI (match_dup 3)) 1036 (set (mem:SI (match_dup 3))
1017 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 1037 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1018 "TARGET_ARM && XVECLEN (operands[0], 0) == 2" 1038 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
1019 "stm%(da%)\t%3, {%1, %2}" 1039 "stmda%?\t%3, {%1, %2}"
1020 [(set_attr "type" "store2") 1040 [(set_attr "type" "store_8")
1021 (set_attr "predicable" "yes")]) 1041 (set_attr "predicable" "yes")])
1022 1042
1023 (define_insn "*stm2_da_update" 1043 (define_insn "*stm2_da_update"
1024 [(match_parallel 0 "store_multiple_operation" 1044 [(match_parallel 0 "store_multiple_operation"
1025 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1045 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1026 (plus:SI (match_dup 3) (const_int -8))) 1046 (plus:SI (match_dup 3) (const_int -8)))
1027 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1047 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1028 (match_operand:SI 1 "arm_hard_register_operand" "")) 1048 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1029 (set (mem:SI (match_dup 3)) 1049 (set (mem:SI (match_dup 3))
1030 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 1050 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1031 "TARGET_ARM && XVECLEN (operands[0], 0) == 3" 1051 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
1032 "stm%(da%)\t%3!, {%1, %2}" 1052 "stmda%?\t%3!, {%1, %2}"
1033 [(set_attr "type" "store2") 1053 [(set_attr "type" "store_8")
1034 (set_attr "predicable" "yes")]) 1054 (set_attr "predicable" "yes")])
1035 1055
1036 (define_insn "*ldm2_db" 1056 (define_insn "*ldm2_db"
1037 [(match_parallel 0 "load_multiple_operation" 1057 [(match_parallel 0 "load_multiple_operation"
1038 [(set (match_operand:SI 1 "arm_hard_register_operand" "") 1058 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1039 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") 1059 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
1040 (const_int -8)))) 1060 (const_int -8))))
1041 (set (match_operand:SI 2 "arm_hard_register_operand" "") 1061 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1042 (mem:SI (plus:SI (match_dup 3) 1062 (mem:SI (plus:SI (match_dup 3)
1043 (const_int -4))))])] 1063 (const_int -4))))])]
1044 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 1064 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
1045 "ldm%(db%)\t%3, {%1, %2}" 1065 "ldmdb%?\t%3, {%1, %2}"
1046 [(set_attr "type" "load2") 1066 [(set_attr "type" "load_8")
1047 (set_attr "predicable" "yes")]) 1067 (set_attr "predicable" "yes")
1068 (set_attr "predicable_short_it" "no")])
1048 1069
1049 (define_insn "*ldm2_db_update" 1070 (define_insn "*ldm2_db_update"
1050 [(match_parallel 0 "load_multiple_operation" 1071 [(match_parallel 0 "load_multiple_operation"
1051 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1072 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1052 (plus:SI (match_dup 3) (const_int -8))) 1073 (plus:SI (match_dup 3) (const_int -8)))
1053 (set (match_operand:SI 1 "arm_hard_register_operand" "") 1074 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
1054 (mem:SI (plus:SI (match_dup 3) 1075 (mem:SI (plus:SI (match_dup 3)
1055 (const_int -8)))) 1076 (const_int -8))))
1056 (set (match_operand:SI 2 "arm_hard_register_operand" "") 1077 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
1057 (mem:SI (plus:SI (match_dup 3) 1078 (mem:SI (plus:SI (match_dup 3)
1058 (const_int -4))))])] 1079 (const_int -4))))])]
1059 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 1080 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
1060 "ldm%(db%)\t%3!, {%1, %2}" 1081 "ldmdb%?\t%3!, {%1, %2}"
1061 [(set_attr "type" "load2") 1082 [(set_attr "type" "load_8")
1062 (set_attr "predicable" "yes")]) 1083 (set_attr "predicable" "yes")
1084 (set_attr "predicable_short_it" "no")])
1063 1085
1064 (define_insn "*stm2_db" 1086 (define_insn "*stm2_db"
1065 [(match_parallel 0 "store_multiple_operation" 1087 [(match_parallel 0 "store_multiple_operation"
1066 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) 1088 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))
1067 (match_operand:SI 1 "arm_hard_register_operand" "")) 1089 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1068 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1090 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1069 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 1091 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1070 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" 1092 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
1071 "stm%(db%)\t%3, {%1, %2}" 1093 "stmdb%?\t%3, {%1, %2}"
1072 [(set_attr "type" "store2") 1094 [(set_attr "type" "store_8")
1073 (set_attr "predicable" "yes")]) 1095 (set_attr "predicable" "yes")
1096 (set_attr "predicable_short_it" "no")])
1074 1097
1075 (define_insn "*stm2_db_update" 1098 (define_insn "*stm2_db_update"
1076 [(match_parallel 0 "store_multiple_operation" 1099 [(match_parallel 0 "store_multiple_operation"
1077 [(set (match_operand:SI 3 "s_register_operand" "+&rk") 1100 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
1078 (plus:SI (match_dup 3) (const_int -8))) 1101 (plus:SI (match_dup 3) (const_int -8)))
1079 (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) 1102 (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
1080 (match_operand:SI 1 "arm_hard_register_operand" "")) 1103 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
1081 (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) 1104 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
1082 (match_operand:SI 2 "arm_hard_register_operand" ""))])] 1105 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
1083 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" 1106 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
1084 "stm%(db%)\t%3!, {%1, %2}" 1107 "stmdb%?\t%3!, {%1, %2}"
1085 [(set_attr "type" "store2") 1108 [(set_attr "type" "store_8")
1086 (set_attr "predicable" "yes")]) 1109 (set_attr "predicable" "yes")
1110 (set_attr "predicable_short_it" "no")])
1087 1111
1088 (define_peephole2 1112 (define_peephole2
1089 [(set (match_operand:SI 0 "s_register_operand" "") 1113 [(set (match_operand:SI 0 "s_register_operand" "")
1090 (match_operand:SI 2 "memory_operand" "")) 1114 (match_operand:SI 2 "memory_operand" ""))
1091 (set (match_operand:SI 1 "s_register_operand" "") 1115 (set (match_operand:SI 1 "s_register_operand" "")
1158 [(set (match_operand:SI 4 "s_register_operand" "") 1182 [(set (match_operand:SI 4 "s_register_operand" "")
1159 (match_operator:SI 5 "commutative_binary_operator" 1183 (match_operator:SI 5 "commutative_binary_operator"
1160 [(match_operand:SI 6 "s_register_operand" "") 1184 [(match_operand:SI 6 "s_register_operand" "")
1161 (match_operand:SI 7 "s_register_operand" "")])) 1185 (match_operand:SI 7 "s_register_operand" "")]))
1162 (clobber (reg:CC CC_REGNUM))])] 1186 (clobber (reg:CC CC_REGNUM))])]
1163 "(((operands[6] == operands[0] && operands[7] == operands[1]) 1187 "((((REGNO (operands[6]) == REGNO (operands[0]))
1164 || (operands[7] == operands[0] && operands[6] == operands[1])) 1188 && (REGNO (operands[7]) == REGNO (operands[1])))
1165 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" 1189 || ((REGNO (operands[7]) == REGNO (operands[0]))
1190 && (REGNO (operands[6]) == REGNO (operands[1]))))
1191 && (peep2_regno_dead_p (3, REGNO (operands[0]))
1192 || (REGNO (operands[0]) == REGNO (operands[4])))
1193 && (peep2_regno_dead_p (3, REGNO (operands[1]))
1194 || (REGNO (operands[1]) == REGNO (operands[4]))))"
1166 [(parallel 1195 [(parallel
1167 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) 1196 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))
1168 (clobber (reg:CC CC_REGNUM))])] 1197 (clobber (reg:CC CC_REGNUM))])]
1169 { 1198 {
1170 if (!gen_ldm_seq (operands, 2, true)) 1199 if (!gen_ldm_seq (operands, 2, true))
1178 (match_operand:SI 3 "memory_operand" "")) 1207 (match_operand:SI 3 "memory_operand" ""))
1179 (set (match_operand:SI 4 "s_register_operand" "") 1208 (set (match_operand:SI 4 "s_register_operand" "")
1180 (match_operator:SI 5 "commutative_binary_operator" 1209 (match_operator:SI 5 "commutative_binary_operator"
1181 [(match_operand:SI 6 "s_register_operand" "") 1210 [(match_operand:SI 6 "s_register_operand" "")
1182 (match_operand:SI 7 "s_register_operand" "")]))] 1211 (match_operand:SI 7 "s_register_operand" "")]))]
1183 "(((operands[6] == operands[0] && operands[7] == operands[1]) 1212 "((((REGNO (operands[6]) == REGNO (operands[0]))
1184 || (operands[7] == operands[0] && operands[6] == operands[1])) 1213 && (REGNO (operands[7]) == REGNO (operands[1])))
1185 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" 1214 || ((REGNO (operands[7]) == REGNO (operands[0]))
1215 && (REGNO (operands[6]) == REGNO (operands[1]))))
1216 && (peep2_regno_dead_p (3, REGNO (operands[0]))
1217 || (REGNO (operands[0]) == REGNO (operands[4])))
1218 && (peep2_regno_dead_p (3, REGNO (operands[1]))
1219 || (REGNO (operands[1]) == REGNO (operands[4]))))"
1186 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] 1220 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))]
1187 { 1221 {
1188 if (!gen_ldm_seq (operands, 2, true)) 1222 if (!gen_ldm_seq (operands, 2, true))
1189 FAIL; 1223 FAIL;
1190 }) 1224 })