CbC/CbC_gcc: gcc/config/arm/ldmstm.md annotate

annotate gcc/config/arm/ldmstm.md @ 111:04ced10e8804

gcc 7

author	kono
date	Fri, 27 Oct 2017 22:46:09 +0900
parents	561a7518be6b
children	84e7813d76e9

rev	line source
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1 /* ARM ldm/stm instruction patterns. This file was automatically generated
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	2 using arm-ldmstm.ml. Please do not edit manually.
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	3
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	4 Copyright (C) 2010-2017 Free Software Foundation, Inc.
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	5 Contributed by CodeSourcery.
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	6
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	7 This file is part of GCC.
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	8
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	9 GCC is free software; you can redistribute it and/or modify it
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	10 under the terms of the GNU General Public License as published
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	11 by the Free Software Foundation; either version 3, or (at your
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	12 option) any later version.
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	13
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	14 GCC is distributed in the hope that it will be useful, but WITHOUT
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	17 License for more details.
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	18
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	19 You should have received a copy of the GNU General Public License and
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	20 a copy of the GCC Runtime Library Exception along with this program;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	22 <http://www.gnu.org/licenses/>. */
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	23
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	24 (define_insn "*ldm4_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	25 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	26 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	27 (mem:SI (match_operand:SI 5 "s_register_operand" "rk")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	28 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	29 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	30 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	31 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	32 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	33 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	34 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	35 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	36 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	37 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	38 "ldm%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	39 [(set_attr "type" "load_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	40 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	41 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	42
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	43 (define_insn "*thumb_ldm4_ia"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	44 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	45 [(set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	46 (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	47 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	48 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	49 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	50 (set (match_operand:SI 3 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	51 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	52 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	53 (set (match_operand:SI 4 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	54 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	55 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	56 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	57 "ldmia\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	58 [(set_attr "type" "load_16")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	59
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	60 (define_insn "*ldm4_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	61 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	62 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	63 (plus:SI (match_dup 5) (const_int 16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	64 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	65 (mem:SI (match_dup 5)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	66 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	67 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	68 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	69 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	70 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	71 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	72 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	73 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	74 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	75 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	76 "ldmia%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	77 [(set_attr "type" "load_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	78 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	79 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	80
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	81 (define_insn "*thumb_ldm4_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	82 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	83 [(set (match_operand:SI 5 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	84 (plus:SI (match_dup 5) (const_int 16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	85 (set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	86 (mem:SI (match_dup 5)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	87 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	88 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	89 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	90 (set (match_operand:SI 3 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	91 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	92 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	93 (set (match_operand:SI 4 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	94 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	95 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	96 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	97 "ldmia\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	98 [(set_attr "type" "load_16")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	99
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	100 (define_insn "*stm4_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	101 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	102 [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	103 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	104 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	105 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	106 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	107 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	108 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	109 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	110 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	111 "stm%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	112 [(set_attr "type" "store_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	113 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	114 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	115
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	116 (define_insn "*stm4_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	117 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	118 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	119 (plus:SI (match_dup 5) (const_int 16)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	120 (set (mem:SI (match_dup 5))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	121 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	122 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	123 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	124 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	125 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	126 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	127 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	128 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	129 "stmia%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	130 [(set_attr "type" "store_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	131 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	132 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	133
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	134 (define_insn "*thumb_stm4_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	135 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	136 [(set (match_operand:SI 5 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	137 (plus:SI (match_dup 5) (const_int 16)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	138 (set (mem:SI (match_dup 5))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	139 (match_operand:SI 1 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	140 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	141 (match_operand:SI 2 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	142 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	143 (match_operand:SI 3 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	144 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	145 (match_operand:SI 4 "low_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	146 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	147 "stmia\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	148 [(set_attr "type" "store_16")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	149
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	150 (define_insn "*ldm4_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	151 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	152 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	153 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	154 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	155 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	156 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	157 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	158 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	159 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	160 (const_int 12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	161 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	162 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	163 (const_int 16))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	164 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	165 "ldmib%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	166 [(set_attr "type" "load_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	167 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	168
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	169 (define_insn "*ldm4_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	170 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	171 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	172 (plus:SI (match_dup 5) (const_int 16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	173 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	174 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	175 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	176 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	177 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	178 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	179 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	180 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	181 (const_int 12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	182 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	183 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	184 (const_int 16))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	185 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	186 "ldmib%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	187 [(set_attr "type" "load_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	188 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	189
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	190 (define_insn "*stm4_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	191 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	192 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	193 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	194 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	195 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	196 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	197 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	198 (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	199 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	200 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	201 "stmib%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	202 [(set_attr "type" "store_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	203 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	204
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	205 (define_insn "*stm4_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	206 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	207 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	208 (plus:SI (match_dup 5) (const_int 16)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	209 (set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	210 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	211 (set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	212 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	213 (set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	214 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	215 (set (mem:SI (plus:SI (match_dup 5) (const_int 16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	216 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	217 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	218 "stmib%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	219 [(set_attr "type" "store_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	220 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	221
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	222 (define_insn "*ldm4_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	223 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	224 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	225 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	226 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	227 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	228 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	229 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	230 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	231 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	232 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	233 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	234 (mem:SI (match_dup 5)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	235 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	236 "ldmda%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	237 [(set_attr "type" "load_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	238 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	239
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	240 (define_insn "*ldm4_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	241 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	242 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	243 (plus:SI (match_dup 5) (const_int -16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	244 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	245 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	246 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	247 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	248 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	249 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	250 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	251 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	252 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	253 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	254 (mem:SI (match_dup 5)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	255 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	256 "ldmda%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	257 [(set_attr "type" "load_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	258 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	259
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	260 (define_insn "*stm4_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	261 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	262 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	263 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	264 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	265 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	266 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	267 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	268 (set (mem:SI (match_dup 5))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	269 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	270 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	271 "stmda%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	272 [(set_attr "type" "store_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	273 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	274
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	275 (define_insn "*stm4_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	276 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	277 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	278 (plus:SI (match_dup 5) (const_int -16)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	279 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	280 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	281 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	282 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	283 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	284 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	285 (set (mem:SI (match_dup 5))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	286 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	287 "TARGET_ARM && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	288 "stmda%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	289 [(set_attr "type" "store_16")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	290 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	291
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	292 (define_insn "*ldm4_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	293 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	294 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	295 (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	296 (const_int -16))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	297 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	298 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	299 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	300 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	301 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	302 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	303 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	304 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	305 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	306 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	307 "ldmdb%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	308 [(set_attr "type" "load_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	309 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	310 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	311
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	312 (define_insn "*ldm4_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	313 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	314 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	315 (plus:SI (match_dup 5) (const_int -16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	316 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	317 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	318 (const_int -16))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	319 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	320 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	321 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	322 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	323 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	324 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	325 (set (match_operand:SI 4 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	326 (mem:SI (plus:SI (match_dup 5)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	327 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	328 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	329 "ldmdb%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	330 [(set_attr "type" "load_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	331 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	332 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	333
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	334 (define_insn "*stm4_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	335 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	336 [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	337 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	338 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	339 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	340 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	341 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	342 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	343 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	344 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	345 "stmdb%?\t%5, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	346 [(set_attr "type" "store_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	347 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	348 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	349
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	350 (define_insn "*stm4_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	351 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	352 [(set (match_operand:SI 5 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	353 (plus:SI (match_dup 5) (const_int -16)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	354 (set (mem:SI (plus:SI (match_dup 5) (const_int -16)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	355 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	356 (set (mem:SI (plus:SI (match_dup 5) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	357 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	358 (set (mem:SI (plus:SI (match_dup 5) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	359 (match_operand:SI 3 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	360 (set (mem:SI (plus:SI (match_dup 5) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	361 (match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	362 "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	363 "stmdb%?\t%5!, {%1, %2, %3, %4}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	364 [(set_attr "type" "store_16")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	365 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	366 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	367
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	368 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	369 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	370 (match_operand:SI 4 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	371 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	372 (match_operand:SI 5 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	373 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	374 (match_operand:SI 6 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	375 (set (match_operand:SI 3 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	376 (match_operand:SI 7 "memory_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	377 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	378 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	379 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	380 if (gen_ldm_seq (operands, 4, false))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	381 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	382 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	383 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	384 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	385
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	386 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	387 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	388 (match_operand:SI 4 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	389 (parallel
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	390 [(set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	391 (match_operand:SI 5 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	392 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	393 (match_operand:SI 6 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	394 (set (match_operand:SI 3 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	395 (match_operand:SI 7 "memory_operand" ""))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	396 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	397 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	398 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	399 if (gen_ldm_seq (operands, 4, false))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	400 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	401 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	402 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	403 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	404
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	405 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	406 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	407 (match_operand:SI 8 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	408 (set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	409 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	410 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	411 (match_operand:SI 9 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	412 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	413 (match_dup 1))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	414 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	415 (match_operand:SI 10 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	416 (set (match_operand:SI 6 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	417 (match_dup 2))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	418 (set (match_operand:SI 3 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	419 (match_operand:SI 11 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	420 (set (match_operand:SI 7 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	421 (match_dup 3))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	422 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	423 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	424 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	425 if (gen_const_stm_seq (operands, 4))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	426 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	427 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	428 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	429 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	430
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	431 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	432 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	433 (match_operand:SI 8 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	434 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	435 (match_operand:SI 9 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	436 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	437 (match_operand:SI 10 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	438 (set (match_operand:SI 3 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	439 (match_operand:SI 11 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	440 (set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	441 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	442 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	443 (match_dup 1))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	444 (set (match_operand:SI 6 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	445 (match_dup 2))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	446 (set (match_operand:SI 7 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	447 (match_dup 3))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	448 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	449 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	450 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	451 if (gen_const_stm_seq (operands, 4))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	452 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	453 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	454 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	455 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	456
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	457 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	458 [(set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	459 (match_operand:SI 0 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	460 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	461 (match_operand:SI 1 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	462 (set (match_operand:SI 6 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	463 (match_operand:SI 2 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	464 (set (match_operand:SI 7 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	465 (match_operand:SI 3 "s_register_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	466 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	467 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	468 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	469 if (gen_stm_seq (operands, 4))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	470 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	471 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	472 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	473 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	474
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	475 (define_insn "*ldm3_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	476 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	477 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	478 (mem:SI (match_operand:SI 4 "s_register_operand" "rk")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	479 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	480 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	481 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	482 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	483 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	484 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	485 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	486 "ldm%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	487 [(set_attr "type" "load_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	488 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	489 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	490
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	491 (define_insn "*thumb_ldm3_ia"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	492 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	493 [(set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	494 (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	495 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	496 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	497 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	498 (set (match_operand:SI 3 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	499 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	500 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	501 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	502 "ldmia\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	503 [(set_attr "type" "load_12")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	504
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	505 (define_insn "*ldm3_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	506 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	507 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	508 (plus:SI (match_dup 4) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	509 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	510 (mem:SI (match_dup 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	511 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	512 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	513 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	514 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	515 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	516 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	517 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	518 "ldmia%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	519 [(set_attr "type" "load_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	520 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	521 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	522
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	523 (define_insn "*thumb_ldm3_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	524 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	525 [(set (match_operand:SI 4 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	526 (plus:SI (match_dup 4) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	527 (set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	528 (mem:SI (match_dup 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	529 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	530 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	531 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	532 (set (match_operand:SI 3 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	533 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	534 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	535 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	536 "ldmia\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	537 [(set_attr "type" "load_12")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	538
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	539 (define_insn "*stm3_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	540 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	541 [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	542 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	543 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	544 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	545 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	546 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	547 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	548 "stm%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	549 [(set_attr "type" "store_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	550 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	551 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	552
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	553 (define_insn "*stm3_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	554 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	555 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	556 (plus:SI (match_dup 4) (const_int 12)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	557 (set (mem:SI (match_dup 4))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	558 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	559 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	560 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	561 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	562 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	563 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	564 "stmia%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	565 [(set_attr "type" "store_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	566 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	567 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	568
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	569 (define_insn "*thumb_stm3_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	570 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	571 [(set (match_operand:SI 4 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	572 (plus:SI (match_dup 4) (const_int 12)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	573 (set (mem:SI (match_dup 4))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	574 (match_operand:SI 1 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	575 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	576 (match_operand:SI 2 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	577 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	578 (match_operand:SI 3 "low_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	579 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	580 "stmia\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	581 [(set_attr "type" "store_12")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	582
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	583 (define_insn "*ldm3_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	584 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	585 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	586 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	587 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	588 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	589 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	590 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	591 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	592 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	593 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	594 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	595 "ldmib%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	596 [(set_attr "type" "load_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	597 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	598
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	599 (define_insn "*ldm3_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	600 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	601 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	602 (plus:SI (match_dup 4) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	603 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	604 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	605 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	606 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	607 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	608 (const_int 8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	609 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	610 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	611 (const_int 12))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	612 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	613 "ldmib%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	614 [(set_attr "type" "load_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	615 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	616
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	617 (define_insn "*stm3_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	618 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	619 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	620 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	621 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	622 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	623 (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	624 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	625 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	626 "stmib%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	627 [(set_attr "type" "store_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	628 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	629
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	630 (define_insn "*stm3_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	631 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	632 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	633 (plus:SI (match_dup 4) (const_int 12)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	634 (set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	635 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	636 (set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	637 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	638 (set (mem:SI (plus:SI (match_dup 4) (const_int 12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	639 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	640 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	641 "stmib%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	642 [(set_attr "type" "store_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	643 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	644
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	645 (define_insn "*ldm3_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	646 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	647 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	648 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	649 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	650 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	651 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	652 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	653 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	654 (mem:SI (match_dup 4)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	655 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	656 "ldmda%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	657 [(set_attr "type" "load_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	658 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	659
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	660 (define_insn "*ldm3_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	661 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	662 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	663 (plus:SI (match_dup 4) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	664 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	665 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	666 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	667 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	668 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	669 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	670 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	671 (mem:SI (match_dup 4)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	672 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	673 "ldmda%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	674 [(set_attr "type" "load_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	675 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	676
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	677 (define_insn "*stm3_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	678 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	679 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	680 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	681 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	682 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	683 (set (mem:SI (match_dup 4))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	684 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	685 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	686 "stmda%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	687 [(set_attr "type" "store_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	688 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	689
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	690 (define_insn "*stm3_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	691 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	692 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	693 (plus:SI (match_dup 4) (const_int -12)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	694 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	695 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	696 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	697 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	698 (set (mem:SI (match_dup 4))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	699 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	700 "TARGET_ARM && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	701 "stmda%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	702 [(set_attr "type" "store_12")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	703 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	704
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	705 (define_insn "*ldm3_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	706 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	707 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	708 (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	709 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	710 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	711 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	712 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	713 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	714 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	715 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	716 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	717 "ldmdb%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	718 [(set_attr "type" "load_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	719 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	720 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	721
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	722 (define_insn "*ldm3_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	723 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	724 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	725 (plus:SI (match_dup 4) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	726 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	727 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	728 (const_int -12))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	729 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	730 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	731 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	732 (set (match_operand:SI 3 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	733 (mem:SI (plus:SI (match_dup 4)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	734 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	735 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	736 "ldmdb%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	737 [(set_attr "type" "load_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	738 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	739 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	740
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	741 (define_insn "*stm3_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	742 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	743 [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	744 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	745 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	746 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	747 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	748 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	749 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	750 "stmdb%?\t%4, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	751 [(set_attr "type" "store_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	752 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	753 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	754
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	755 (define_insn "*stm3_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	756 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	757 [(set (match_operand:SI 4 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	758 (plus:SI (match_dup 4) (const_int -12)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	759 (set (mem:SI (plus:SI (match_dup 4) (const_int -12)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	760 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	761 (set (mem:SI (plus:SI (match_dup 4) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	762 (match_operand:SI 2 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	763 (set (mem:SI (plus:SI (match_dup 4) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	764 (match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	765 "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	766 "stmdb%?\t%4!, {%1, %2, %3}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	767 [(set_attr "type" "store_12")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	768 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	769 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	770
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	771 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	772 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	773 (match_operand:SI 3 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	774 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	775 (match_operand:SI 4 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	776 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	777 (match_operand:SI 5 "memory_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	778 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	779 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	780 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	781 if (gen_ldm_seq (operands, 3, false))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	782 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	783 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	784 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	785 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	786
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	787 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	788 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	789 (match_operand:SI 3 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	790 (parallel
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	791 [(set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	792 (match_operand:SI 4 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	793 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	794 (match_operand:SI 5 "memory_operand" ""))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	795 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	796 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	797 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	798 if (gen_ldm_seq (operands, 3, false))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	799 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	800 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	801 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	802 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	803
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	804 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	805 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	806 (match_operand:SI 6 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	807 (set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	808 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	809 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	810 (match_operand:SI 7 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	811 (set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	812 (match_dup 1))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	813 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	814 (match_operand:SI 8 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	815 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	816 (match_dup 2))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	817 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	818 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	819 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	820 if (gen_const_stm_seq (operands, 3))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	821 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	822 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	823 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	824 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	825
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	826 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	827 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	828 (match_operand:SI 6 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	829 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	830 (match_operand:SI 7 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	831 (set (match_operand:SI 2 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	832 (match_operand:SI 8 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	833 (set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	834 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	835 (set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	836 (match_dup 1))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	837 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	838 (match_dup 2))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	839 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	840 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	841 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	842 if (gen_const_stm_seq (operands, 3))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	843 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	844 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	845 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	846 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	847
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	848 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	849 [(set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	850 (match_operand:SI 0 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	851 (set (match_operand:SI 4 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	852 (match_operand:SI 1 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	853 (set (match_operand:SI 5 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	854 (match_operand:SI 2 "s_register_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	855 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	856 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	857 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	858 if (gen_stm_seq (operands, 3))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	859 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	860 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	861 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	862 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	863
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	864 (define_insn "*ldm2_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	865 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	866 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	867 (mem:SI (match_operand:SI 3 "s_register_operand" "rk")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	868 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	869 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	870 (const_int 4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	871 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	872 "ldm%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	873 [(set_attr "type" "load_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	874 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	875 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	876
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	877 (define_insn "*thumb_ldm2_ia"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	878 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	879 [(set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	880 (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	881 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	882 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	883 (const_int 4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	884 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	885 "ldmia\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	886 [(set_attr "type" "load_8")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	887
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	888 (define_insn "*ldm2_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	889 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	890 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	891 (plus:SI (match_dup 3) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	892 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	893 (mem:SI (match_dup 3)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	894 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	895 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	896 (const_int 4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	897 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	898 "ldmia%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	899 [(set_attr "type" "load_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	900 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	901 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	902
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	903 (define_insn "*thumb_ldm2_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	904 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	905 [(set (match_operand:SI 3 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	906 (plus:SI (match_dup 3) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	907 (set (match_operand:SI 1 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	908 (mem:SI (match_dup 3)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	909 (set (match_operand:SI 2 "low_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	910 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	911 (const_int 4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	912 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	913 "ldmia\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	914 [(set_attr "type" "load_8")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	915
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	916 (define_insn "*stm2_"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	917 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	918 [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	919 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	920 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	921 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	922 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	923 "stm%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	924 [(set_attr "type" "store_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	925 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	926 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	927
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	928 (define_insn "*stm2_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	929 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	930 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	931 (plus:SI (match_dup 3) (const_int 8)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	932 (set (mem:SI (match_dup 3))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	933 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	934 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	935 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	936 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	937 "stmia%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	938 [(set_attr "type" "store_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	939 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	940 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	941
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	942 (define_insn "*thumb_stm2_ia_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	943 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	944 [(set (match_operand:SI 3 "s_register_operand" "+&l")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	945 (plus:SI (match_dup 3) (const_int 8)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	946 (set (mem:SI (match_dup 3))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	947 (match_operand:SI 1 "low_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	948 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	949 (match_operand:SI 2 "low_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	950 "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	951 "stmia\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	952 [(set_attr "type" "store_8")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	953
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	954 (define_insn "*ldm2_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	955 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	956 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	957 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	958 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	959 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	960 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	961 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	962 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	963 "ldmib%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	964 [(set_attr "type" "load_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	965 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	966
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	967 (define_insn "*ldm2_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	968 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	969 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	970 (plus:SI (match_dup 3) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	971 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	972 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	973 (const_int 4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	974 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	975 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	976 (const_int 8))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	977 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	978 "ldmib%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	979 [(set_attr "type" "load_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	980 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	981
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	982 (define_insn "*stm2_ib"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	983 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	984 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	985 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	986 (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	987 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	988 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	989 "stmib%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	990 [(set_attr "type" "store_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	991 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	992
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	993 (define_insn "*stm2_ib_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	994 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	995 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	996 (plus:SI (match_dup 3) (const_int 8)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	997 (set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	998 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	999 (set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1000 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1001 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1002 "stmib%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1003 [(set_attr "type" "store_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1004 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1005
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1006 (define_insn "*ldm2_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1007 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1008 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1009 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1010 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1011 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1012 (mem:SI (match_dup 3)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1013 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1014 "ldmda%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1015 [(set_attr "type" "load_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1016 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1017
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1018 (define_insn "*ldm2_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1019 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1020 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1021 (plus:SI (match_dup 3) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1022 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1023 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1024 (const_int -4))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1025 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1026 (mem:SI (match_dup 3)))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1027 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1028 "ldmda%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1029 [(set_attr "type" "load_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1030 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1031
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1032 (define_insn "*stm2_da"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1033 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1034 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1035 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1036 (set (mem:SI (match_dup 3))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1037 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1038 "TARGET_ARM && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1039 "stmda%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1040 [(set_attr "type" "store_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1041 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1042
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1043 (define_insn "*stm2_da_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1044 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1045 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1046 (plus:SI (match_dup 3) (const_int -8)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1047 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1048 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1049 (set (mem:SI (match_dup 3))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1050 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1051 "TARGET_ARM && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1052 "stmda%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1053 [(set_attr "type" "store_8")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1054 (set_attr "predicable" "yes")])
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1055
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1056 (define_insn "*ldm2_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1057 [(match_parallel 0 "load_multiple_operation"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1058 [(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1059 (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1060 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1061 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1062 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1063 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1064 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1065 "ldmdb%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1066 [(set_attr "type" "load_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1067 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1068 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1069
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1070 (define_insn "*ldm2_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1071 [(match_parallel 0 "load_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1072 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1073 (plus:SI (match_dup 3) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1074 (set (match_operand:SI 1 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1075 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1076 (const_int -8))))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1077 (set (match_operand:SI 2 "arm_hard_general_register_operand" "")
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1078 (mem:SI (plus:SI (match_dup 3)
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1079 (const_int -4))))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1080 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1081 "ldmdb%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1082 [(set_attr "type" "load_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1083 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1084 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1085
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1086 (define_insn "*stm2_db"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1087 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1088 [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1089 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1090 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1091 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1092 "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1093 "stmdb%?\t%3, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1094 [(set_attr "type" "store_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1095 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1096 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1097
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1098 (define_insn "*stm2_db_update"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1099 [(match_parallel 0 "store_multiple_operation"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1100 [(set (match_operand:SI 3 "s_register_operand" "+&rk")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1101 (plus:SI (match_dup 3) (const_int -8)))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1102 (set (mem:SI (plus:SI (match_dup 3) (const_int -8)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1103 (match_operand:SI 1 "arm_hard_general_register_operand" ""))
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1104 (set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1105 (match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1106 "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1107 "stmdb%?\t%3!, {%1, %2}"
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1108 [(set_attr "type" "store_8")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1109 (set_attr "predicable" "yes")
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1110 (set_attr "predicable_short_it" "no")])
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1111
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1112 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1113 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1114 (match_operand:SI 2 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1115 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1116 (match_operand:SI 3 "memory_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1117 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1118 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1119 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1120 if (gen_ldm_seq (operands, 2, false))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1121 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1122 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1123 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1124 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1125
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1126 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1127 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1128 (match_operand:SI 4 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1129 (set (match_operand:SI 2 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1130 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1131 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1132 (match_operand:SI 5 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1133 (set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1134 (match_dup 1))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1135 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1136 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1137 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1138 if (gen_const_stm_seq (operands, 2))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1139 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1140 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1141 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1142 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1143
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1144 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1145 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1146 (match_operand:SI 4 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1147 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1148 (match_operand:SI 5 "const_int_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1149 (set (match_operand:SI 2 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1150 (match_dup 0))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1151 (set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1152 (match_dup 1))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1153 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1154 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1155 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1156 if (gen_const_stm_seq (operands, 2))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1157 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1158 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1159 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1160 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1161
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1162 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1163 [(set (match_operand:SI 2 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1164 (match_operand:SI 0 "s_register_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1165 (set (match_operand:SI 3 "memory_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1166 (match_operand:SI 1 "s_register_operand" ""))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1167 ""
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1168 [(const_int 0)]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1169 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1170 if (gen_stm_seq (operands, 2))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1171 DONE;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1172 else
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1173 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1174 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1175
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1176 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1177 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1178 (match_operand:SI 2 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1179 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1180 (match_operand:SI 3 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1181 (parallel
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1182 [(set (match_operand:SI 4 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1183 (match_operator:SI 5 "commutative_binary_operator"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1184 [(match_operand:SI 6 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1185 (match_operand:SI 7 "s_register_operand" "")]))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1186 (clobber (reg:CC CC_REGNUM))])]
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1187 "((((REGNO (operands[6]) == REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1188 && (REGNO (operands[7]) == REGNO (operands[1])))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1189 \|\| ((REGNO (operands[7]) == REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1190 && (REGNO (operands[6]) == REGNO (operands[1]))))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1191 && (peep2_regno_dead_p (3, REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1192 \|\| (REGNO (operands[0]) == REGNO (operands[4])))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1193 && (peep2_regno_dead_p (3, REGNO (operands[1]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1194 \|\| (REGNO (operands[1]) == REGNO (operands[4]))))"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1195 [(parallel
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1196 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1197 (clobber (reg:CC CC_REGNUM))])]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1198 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1199 if (!gen_ldm_seq (operands, 2, true))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1200 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1201 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1202
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1203 (define_peephole2
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1204 [(set (match_operand:SI 0 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1205 (match_operand:SI 2 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1206 (set (match_operand:SI 1 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1207 (match_operand:SI 3 "memory_operand" ""))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1208 (set (match_operand:SI 4 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1209 (match_operator:SI 5 "commutative_binary_operator"
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1210 [(match_operand:SI 6 "s_register_operand" "")
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1211 (match_operand:SI 7 "s_register_operand" "")]))]
111 04ced10e8804 gcc 7 kono parents: 68 diff changeset	1212 "((((REGNO (operands[6]) == REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1213 && (REGNO (operands[7]) == REGNO (operands[1])))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1214 \|\| ((REGNO (operands[7]) == REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1215 && (REGNO (operands[6]) == REGNO (operands[1]))))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1216 && (peep2_regno_dead_p (3, REGNO (operands[0]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1217 \|\| (REGNO (operands[0]) == REGNO (operands[4])))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1218 && (peep2_regno_dead_p (3, REGNO (operands[1]))
04ced10e8804 gcc 7 kono parents: 68 diff changeset	1219 \|\| (REGNO (operands[1]) == REGNO (operands[4]))))"
68 561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1220 [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))]
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1221 {
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1222 if (!gen_ldm_seq (operands, 2, true))
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1223 FAIL;
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1224 })
561a7518be6b update gcc-4.6 Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> parents: diff changeset	1225

Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/arm/ldmstm.md @ 111:04ced10e8804