CbC/CbC_gcc: gcc/config/i386/constraints.md comparison

comparison gcc/config/i386/constraints.md @ 111:04ced10e8804

gcc 7

author	kono
date	Fri, 27 Oct 2017 22:46:09 +0900
parents	58ad6c70ea60
children	84e7813d76e9

comparison

equal deleted inserted replaced

-:561a7518be6b
+:04ced10e8804
 ;; Constraint definitions for IA-32 and x86-64.
-;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
+;; Copyright (C) 2006-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 ;; You should have received a copy of the GNU General Public License
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 ;;; Unused letters:
-;;;     B     H           T  W
+;;;           H
-;;;           h jk          vw  z
+;;;           h j               z
 ;; Integer register constraints.
 ;; It is not necessary to define 'r' here.
 (define_register_constraint "R" "LEGACY_REGS"
 "Legacy register---the eight integer registers available on all
 (define_register_constraint "u"
 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
+(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS"
+"@internal Any mask register that can be used as predicate, i.e. k1-k7.")
+(define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
+"@internal Any mask register.")
 ;; Vector registers (also used for plain floating point nowadays).
 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
 "Any MMX register.")
 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
 "Any SSE register.")
+(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
+"Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
+(define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
+"@internal Any bound register.")
 ;; We use the Y prefix to denote any number of conditional register sets:
 ;;  z	First SSE register.
-;;  2	SSE2 enabled
+;;  c	SSE inter-unit conversions enabled
-;;  i	SSE2 inter-unit moves enabled
+;;  i	SSE2 inter-unit moves to SSE register enabled
-;;  m	MMX inter-unit moves enabled
+;;  j	SSE2 inter-unit moves from SSE register enabled
+;;  d	any EVEX encodable SSE register for AVX512BW target or any SSE register
+;;	for SSE4_1 target, when inter-unit moves to SSE register are enabled
+;;  e	any EVEX encodable SSE register for AVX512BW target or any SSE register
+;;	for SSE4_1 target, when inter-unit moves from SSE register are enabled
+;;  m	MMX inter-unit moves to MMX register enabled
+;;  n	MMX inter-unit moves from MMX register enabled
+;;  p	Integer register when TARGET_PARTIAL_REG_STALL is disabled
+;;  a	Integer register when zero extensions with AND are disabled
+;;  b	Any register that can be used as the GOT base when calling
+;;	___tls_get_addr: that is, any general register except EAX
+;;	and ESP, for -fno-plt if linker supports it.  Otherwise,
+;;	EBX.
+;;  f	x87 register when 80387 floating point arithmetic is enabled
+;;  r	SSE regs not requiring REX prefix when prefixes avoidance is enabled
+;;	and all SSE regs otherwise
+;;  v	any EVEX encodable SSE register for AVX512VL target,
+;;	otherwise any SSE register
+;;  h	EVEX encodable SSE register with number factor of four
 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
 "First SSE register (@code{%xmm0}).")
-(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
+(define_register_constraint "Yc"
-"@internal Any SSE register, when SSE2 is enabled.")
+"TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
+"@internal Any SSE register, when SSE and inter-unit conversions are enabled.")
 (define_register_constraint "Yi"
-"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
+"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
-"@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
+"@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
+(define_register_constraint "Yj"
+"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
+"@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
+(define_register_constraint "Yd"
+"TARGET_INTER_UNIT_MOVES_TO_VEC
+? (TARGET_AVX512DQ
+? ALL_SSE_REGS
+: (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
+: NO_REGS"
+"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.")
+(define_register_constraint "Ye"
+"TARGET_INTER_UNIT_MOVES_FROM_VEC
+? (TARGET_AVX512DQ
+? ALL_SSE_REGS
+: (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
+: NO_REGS"
+"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.")
 (define_register_constraint "Ym"
-"TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
+"TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS"
-"@internal Any MMX register, when inter-unit moves are enabled.")
+"@internal Any MMX register, when inter-unit moves to vector registers are enabled.")
+(define_register_constraint "Yn"
+"TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS"
+"@internal Any MMX register, when inter-unit moves from vector registers are enabled.")
+(define_register_constraint "Yp"
+"TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
+"@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
+(define_register_constraint "Ya"
+"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
+? NO_REGS : GENERAL_REGS"
+"@internal Any integer register when zero extensions with AND are disabled.")
+(define_register_constraint "Yb"
+"(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
+"@internal Any register that can be used as the GOT base when calling
+___tls_get_addr: that is, any general register except @code{a} and
+@code{sp} registers, for -fno-plt if linker supports it.  Otherwise,
+@code{b} register.")
+(define_register_constraint "Yf"
+"(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
+"@internal Any x87 register when 80387 FP arithmetic is enabled.")
+(define_register_constraint "Yr"
+"TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
+"@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
+(define_register_constraint "Yv"
+"TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
+"@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
+(define_register_constraint "Yh" "TARGET_AVX512F ? MOD4_SSE_REGS : NO_REGS"
+"@internal Any EVEX encodable SSE register, which has number factor of four.")
+;; We use the B prefix to denote any number of internal operands:
+;;  f  FLAGS_REG
+;;  g  GOT memory operand.
+;;  m  Vector memory operand
+;;  c  Constant memory operand
+;;  n  Memory operand without REX prefix
+;;  s  Sibcall memory operand, not valid for TARGET_X32
+;;  w  Call memory operand, not valid for TARGET_X32
+;;  z  Constant call address operand.
+;;  C  SSE constant operand.
+(define_constraint "Bf"
+"@internal Flags register operand."
+(match_operand 0 "flags_reg_operand"))
+(define_constraint "Bg"
+"@internal GOT memory operand."
+(match_operand 0 "GOT_memory_operand"))
+(define_special_memory_constraint "Bm"
+"@internal Vector memory operand."
+(match_operand 0 "vector_memory_operand"))
+(define_special_memory_constraint "Bc"
+"@internal Constant memory operand."
+(and (match_operand 0 "memory_operand")
+(match_test "constant_address_p (XEXP (op, 0))")))
+(define_special_memory_constraint "Bn"
+"@internal Memory operand without REX prefix."
+(match_operand 0 "norex_memory_operand"))
+(define_constraint "Bs"
+"@internal Sibcall memory operand."
+(ior (and (not (match_test "TARGET_X32"))
+	    (match_operand 0 "sibcall_memory_operand"))
+(and (match_test "TARGET_X32 && Pmode == DImode")
+	    (match_operand 0 "GOT_memory_operand"))))
+(define_constraint "Bw"
+"@internal Call memory operand."
+(ior (and (not (match_test "TARGET_X32"))
+	    (match_operand 0 "memory_operand"))
+(and (match_test "TARGET_X32 && Pmode == DImode")
+	    (match_operand 0 "GOT_memory_operand"))))
+(define_constraint "Bz"
+"@internal Constant call address operand."
+(match_operand 0 "constant_call_address_operand"))
+(define_constraint "BC"
+"@internal SSE constant -1 operand."
+(and (match_test "TARGET_SSE")
+(ior (match_test "op == constm1_rtx")
+	    (match_operand 0 "vector_all_ones_operand"))))
 ;; Integer constant constraints.
 (define_constraint "I"
 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
 (and (match_code "const_int")
 "Signed 8-bit integer constant."
 (and (match_code "const_int")
 (match_test "IN_RANGE (ival, -128, 127)")))
 (define_constraint "L"
-"@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move."
+"@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
-(and (match_code "const_int")
+for AND as a zero-extending move."
-(match_test "ival == 0xFF || ival == 0xFFFF")))
+(and (match_code "const_int")
+(match_test "ival == 0xff || ival == 0xffff
+		    || ival == (HOST_WIDE_INT) 0xffffffff")))
 (define_constraint "M"
 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
 (and (match_code "const_int")
 (match_test "IN_RANGE (ival, 0, 3)")))
 ;; stack register converter may need to load 0.0 into the function
 ;; value register (top of stack).
 (define_constraint "G"
 "Standard 80387 floating point constant."
 (and (match_code "const_double")
-(match_test "standard_80387_constant_p (op)")))
+(match_test "standard_80387_constant_p (op) > 0")))
 ;; This can theoretically be any mode's CONST0_RTX.
 (define_constraint "C"
-"Standard SSE floating point constant."
+"SSE constant zero operand."
-(match_test "standard_sse_constant_p (op)"))
+(and (match_test "TARGET_SSE")
+(ior (match_test "op == const0_rtx")
+	    (match_operand 0 "const0_operand"))))
 ;; Constant-or-symbol-reference constraints.
 (define_constraint "e"
 "32-bit signed integer constant, or a symbolic reference known
 to fit that range (for immediate operands in sign-extending x86-64
 instructions)."
 (match_operand 0 "x86_64_immediate_operand"))
+;; We use W prefix to denote any number of
+;; constant-or-symbol-reference constraints
+(define_constraint "We"
+"32-bit signed integer constant, or a symbolic reference known
+to fit that range (for sign-extending conversion operations that
+require non-VOIDmode immediate operands)."
+(and (match_operand 0 "x86_64_immediate_operand")
+(match_test "GET_MODE (op) != VOIDmode")))
+(define_constraint "Wz"
+"32-bit unsigned integer constant, or a symbolic reference known
+to fit that range (for zero-extending conversion operations that
+require non-VOIDmode immediate operands)."
+(and (match_operand 0 "x86_64_zext_immediate_operand")
+(match_test "GET_MODE (op) != VOIDmode")))
+(define_constraint "Wd"
+"128-bit integer constant where both the high and low 64-bit word
+of it satisfies the e constraint."
+(match_operand 0 "x86_64_hilo_int_operand"))
+(define_constraint "Wf"
+"32-bit signed integer constant zero extended from word size
+to double word size."
+(match_operand 0 "x86_64_dwzext_immediate_operand"))
 (define_constraint "Z"
 "32-bit unsigned integer constant, or a symbolic reference known
 to fit that range (for immediate operands in zero-extending x86-64
 instructions)."
 (match_operand 0 "x86_64_zext_immediate_operand"))
+;; T prefix is used for different address constraints
+;;   v - VSIB address
+;;   s - address with no segment register
+;;   i - address with no index and no rip
+;;   b - address with no base and no rip
+(define_address_constraint "Tv"
+"VSIB address operand"
+(match_operand 0 "vsib_address_operand"))
+(define_address_constraint "Ts"
+"Address operand without segment register"
+(match_operand 0 "address_no_seg_operand"))
+(define_address_constraint "Ti"
+"MPX address operand without index"
+(match_operand 0 "address_mpx_no_index_operand"))
+(define_address_constraint "Tb"
+"MPX address operand without base"
+(match_operand 0 "address_mpx_no_base_operand"))

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comparison gcc/config/i386/constraints.md @ 111:04ced10e8804