Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/constraints.md @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | 58ad6c70ea60 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 ;; Constraint definitions for IA-32 and x86-64. |
| 111 | 2 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc. |
| 0 | 3 ;; |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 ;;; Unused letters: | |
| 111 | 21 ;;; H |
| 22 ;;; h j z | |
| 0 | 23 |
| 24 ;; Integer register constraints. | |
| 25 ;; It is not necessary to define 'r' here. | |
| 26 (define_register_constraint "R" "LEGACY_REGS" | |
| 27 "Legacy register---the eight integer registers available on all | |
| 28 i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
| 29 @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
| 30 | |
| 31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
| 32 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
| 33 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
| 34 | |
| 35 (define_register_constraint "Q" "Q_REGS" | |
| 36 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
| 37 @code{c}, and @code{d}.") | |
| 38 | |
| 39 (define_register_constraint "l" "INDEX_REGS" | |
| 40 "@internal Any register that can be used as the index in a base+index | |
| 41 memory access: that is, any general register except the stack pointer.") | |
| 42 | |
| 43 (define_register_constraint "a" "AREG" | |
| 44 "The @code{a} register.") | |
| 45 | |
| 46 (define_register_constraint "b" "BREG" | |
| 47 "The @code{b} register.") | |
| 48 | |
| 49 (define_register_constraint "c" "CREG" | |
| 50 "The @code{c} register.") | |
| 51 | |
| 52 (define_register_constraint "d" "DREG" | |
| 53 "The @code{d} register.") | |
| 54 | |
| 55 (define_register_constraint "S" "SIREG" | |
| 56 "The @code{si} register.") | |
| 57 | |
| 58 (define_register_constraint "D" "DIREG" | |
| 59 "The @code{di} register.") | |
| 60 | |
| 61 (define_register_constraint "A" "AD_REGS" | |
| 62 "The @code{a} and @code{d} registers, as a pair (for instructions | |
| 63 that return half the result in one and half in the other).") | |
| 64 | |
|
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58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
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changeset
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65 (define_register_constraint "U" "CLOBBERED_REGS" |
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58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
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66 "The call-clobbered integer registers.") |
|
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
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67 |
| 0 | 68 ;; Floating-point register constraints. |
| 69 (define_register_constraint "f" | |
| 70 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
| 71 "Any 80387 floating-point (stack) register.") | |
| 72 | |
| 73 (define_register_constraint "t" | |
| 74 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
| 75 "Top of 80387 floating-point stack (@code{%st(0)}).") | |
| 76 | |
| 77 (define_register_constraint "u" | |
| 78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
| 79 "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
| 80 | |
| 111 | 81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" |
| 82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.") | |
| 83 | |
| 84 (define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS" | |
| 85 "@internal Any mask register.") | |
| 86 | |
| 0 | 87 ;; Vector registers (also used for plain floating point nowadays). |
| 88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
| 89 "Any MMX register.") | |
| 90 | |
| 91 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
| 92 "Any SSE register.") | |
| 93 | |
| 111 | 94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" |
| 95 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") | |
| 96 | |
| 97 (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS" | |
| 98 "@internal Any bound register.") | |
| 99 | |
| 0 | 100 ;; We use the Y prefix to denote any number of conditional register sets: |
| 101 ;; z First SSE register. | |
| 111 | 102 ;; c SSE inter-unit conversions enabled |
| 103 ;; i SSE2 inter-unit moves to SSE register enabled | |
| 104 ;; j SSE2 inter-unit moves from SSE register enabled | |
| 105 ;; d any EVEX encodable SSE register for AVX512BW target or any SSE register | |
| 106 ;; for SSE4_1 target, when inter-unit moves to SSE register are enabled | |
| 107 ;; e any EVEX encodable SSE register for AVX512BW target or any SSE register | |
| 108 ;; for SSE4_1 target, when inter-unit moves from SSE register are enabled | |
| 109 ;; m MMX inter-unit moves to MMX register enabled | |
| 110 ;; n MMX inter-unit moves from MMX register enabled | |
| 111 ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled | |
| 112 ;; a Integer register when zero extensions with AND are disabled | |
| 113 ;; b Any register that can be used as the GOT base when calling | |
| 114 ;; ___tls_get_addr: that is, any general register except EAX | |
| 115 ;; and ESP, for -fno-plt if linker supports it. Otherwise, | |
| 116 ;; EBX. | |
| 117 ;; f x87 register when 80387 floating point arithmetic is enabled | |
| 118 ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled | |
| 119 ;; and all SSE regs otherwise | |
| 120 ;; v any EVEX encodable SSE register for AVX512VL target, | |
| 121 ;; otherwise any SSE register | |
| 122 ;; h EVEX encodable SSE register with number factor of four | |
| 0 | 123 |
| 124 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" | |
| 125 "First SSE register (@code{%xmm0}).") | |
| 126 | |
| 111 | 127 (define_register_constraint "Yc" |
| 128 "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS" | |
| 129 "@internal Any SSE register, when SSE and inter-unit conversions are enabled.") | |
| 0 | 130 |
| 131 (define_register_constraint "Yi" | |
| 111 | 132 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" |
| 133 "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") | |
| 134 | |
| 135 (define_register_constraint "Yj" | |
| 136 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" | |
| 137 "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") | |
| 138 | |
| 139 (define_register_constraint "Yd" | |
| 140 "TARGET_INTER_UNIT_MOVES_TO_VEC | |
| 141 ? (TARGET_AVX512DQ | |
| 142 ? ALL_SSE_REGS | |
| 143 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) | |
| 144 : NO_REGS" | |
| 145 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") | |
| 146 | |
| 147 (define_register_constraint "Ye" | |
| 148 "TARGET_INTER_UNIT_MOVES_FROM_VEC | |
| 149 ? (TARGET_AVX512DQ | |
| 150 ? ALL_SSE_REGS | |
| 151 : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) | |
| 152 : NO_REGS" | |
| 153 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") | |
| 0 | 154 |
| 155 (define_register_constraint "Ym" | |
| 111 | 156 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" |
| 157 "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") | |
| 158 | |
| 159 (define_register_constraint "Yn" | |
| 160 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS" | |
| 161 "@internal Any MMX register, when inter-unit moves from vector registers are enabled.") | |
| 162 | |
| 163 (define_register_constraint "Yp" | |
| 164 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" | |
| 165 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") | |
| 166 | |
| 167 (define_register_constraint "Ya" | |
| 168 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) | |
| 169 ? NO_REGS : GENERAL_REGS" | |
| 170 "@internal Any integer register when zero extensions with AND are disabled.") | |
| 171 | |
| 172 (define_register_constraint "Yb" | |
| 173 "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG" | |
| 174 "@internal Any register that can be used as the GOT base when calling | |
| 175 ___tls_get_addr: that is, any general register except @code{a} and | |
| 176 @code{sp} registers, for -fno-plt if linker supports it. Otherwise, | |
| 177 @code{b} register.") | |
| 178 | |
| 179 (define_register_constraint "Yf" | |
| 180 "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" | |
| 181 "@internal Any x87 register when 80387 FP arithmetic is enabled.") | |
| 182 | |
| 183 (define_register_constraint "Yr" | |
| 184 "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS" | |
| 185 "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") | |
| 186 | |
| 187 (define_register_constraint "Yv" | |
| 188 "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" | |
| 189 "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") | |
| 190 | |
| 191 (define_register_constraint "Yh" "TARGET_AVX512F ? MOD4_SSE_REGS : NO_REGS" | |
| 192 "@internal Any EVEX encodable SSE register, which has number factor of four.") | |
| 193 | |
| 194 ;; We use the B prefix to denote any number of internal operands: | |
| 195 ;; f FLAGS_REG | |
| 196 ;; g GOT memory operand. | |
| 197 ;; m Vector memory operand | |
| 198 ;; c Constant memory operand | |
| 199 ;; n Memory operand without REX prefix | |
| 200 ;; s Sibcall memory operand, not valid for TARGET_X32 | |
| 201 ;; w Call memory operand, not valid for TARGET_X32 | |
| 202 ;; z Constant call address operand. | |
| 203 ;; C SSE constant operand. | |
| 204 | |
| 205 (define_constraint "Bf" | |
| 206 "@internal Flags register operand." | |
| 207 (match_operand 0 "flags_reg_operand")) | |
| 208 | |
| 209 (define_constraint "Bg" | |
| 210 "@internal GOT memory operand." | |
| 211 (match_operand 0 "GOT_memory_operand")) | |
| 212 | |
| 213 (define_special_memory_constraint "Bm" | |
| 214 "@internal Vector memory operand." | |
| 215 (match_operand 0 "vector_memory_operand")) | |
| 216 | |
| 217 (define_special_memory_constraint "Bc" | |
| 218 "@internal Constant memory operand." | |
| 219 (and (match_operand 0 "memory_operand") | |
| 220 (match_test "constant_address_p (XEXP (op, 0))"))) | |
| 221 | |
| 222 (define_special_memory_constraint "Bn" | |
| 223 "@internal Memory operand without REX prefix." | |
| 224 (match_operand 0 "norex_memory_operand")) | |
| 225 | |
| 226 (define_constraint "Bs" | |
| 227 "@internal Sibcall memory operand." | |
| 228 (ior (and (not (match_test "TARGET_X32")) | |
| 229 (match_operand 0 "sibcall_memory_operand")) | |
| 230 (and (match_test "TARGET_X32 && Pmode == DImode") | |
| 231 (match_operand 0 "GOT_memory_operand")))) | |
| 232 | |
| 233 (define_constraint "Bw" | |
| 234 "@internal Call memory operand." | |
| 235 (ior (and (not (match_test "TARGET_X32")) | |
| 236 (match_operand 0 "memory_operand")) | |
| 237 (and (match_test "TARGET_X32 && Pmode == DImode") | |
| 238 (match_operand 0 "GOT_memory_operand")))) | |
| 239 | |
| 240 (define_constraint "Bz" | |
| 241 "@internal Constant call address operand." | |
| 242 (match_operand 0 "constant_call_address_operand")) | |
| 243 | |
| 244 (define_constraint "BC" | |
| 245 "@internal SSE constant -1 operand." | |
| 246 (and (match_test "TARGET_SSE") | |
| 247 (ior (match_test "op == constm1_rtx") | |
| 248 (match_operand 0 "vector_all_ones_operand")))) | |
| 0 | 249 |
| 250 ;; Integer constant constraints. | |
| 251 (define_constraint "I" | |
| 252 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
| 253 (and (match_code "const_int") | |
| 254 (match_test "IN_RANGE (ival, 0, 31)"))) | |
| 255 | |
| 256 (define_constraint "J" | |
| 257 "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
| 258 (and (match_code "const_int") | |
| 259 (match_test "IN_RANGE (ival, 0, 63)"))) | |
| 260 | |
| 261 (define_constraint "K" | |
| 262 "Signed 8-bit integer constant." | |
| 263 (and (match_code "const_int") | |
| 264 (match_test "IN_RANGE (ival, -128, 127)"))) | |
| 265 | |
| 266 (define_constraint "L" | |
| 111 | 267 "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} |
| 268 for AND as a zero-extending move." | |
| 0 | 269 (and (match_code "const_int") |
| 111 | 270 (match_test "ival == 0xff || ival == 0xffff |
| 271 || ival == (HOST_WIDE_INT) 0xffffffff"))) | |
| 0 | 272 |
| 273 (define_constraint "M" | |
| 274 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
| 275 (and (match_code "const_int") | |
| 276 (match_test "IN_RANGE (ival, 0, 3)"))) | |
| 277 | |
| 278 (define_constraint "N" | |
| 279 "Unsigned 8-bit integer constant (for @code{in} and @code{out} | |
| 280 instructions)." | |
| 281 (and (match_code "const_int") | |
| 282 (match_test "IN_RANGE (ival, 0, 255)"))) | |
| 283 | |
| 284 (define_constraint "O" | |
| 285 "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
| 286 (and (match_code "const_int") | |
| 287 (match_test "IN_RANGE (ival, 0, 127)"))) | |
| 288 | |
| 289 ;; Floating-point constant constraints. | |
| 290 ;; We allow constants even if TARGET_80387 isn't set, because the | |
| 291 ;; stack register converter may need to load 0.0 into the function | |
| 292 ;; value register (top of stack). | |
| 293 (define_constraint "G" | |
| 294 "Standard 80387 floating point constant." | |
| 295 (and (match_code "const_double") | |
| 111 | 296 (match_test "standard_80387_constant_p (op) > 0"))) |
| 0 | 297 |
| 298 ;; This can theoretically be any mode's CONST0_RTX. | |
| 299 (define_constraint "C" | |
| 111 | 300 "SSE constant zero operand." |
| 301 (and (match_test "TARGET_SSE") | |
| 302 (ior (match_test "op == const0_rtx") | |
| 303 (match_operand 0 "const0_operand")))) | |
| 0 | 304 |
| 305 ;; Constant-or-symbol-reference constraints. | |
| 306 | |
| 307 (define_constraint "e" | |
| 308 "32-bit signed integer constant, or a symbolic reference known | |
| 309 to fit that range (for immediate operands in sign-extending x86-64 | |
| 310 instructions)." | |
| 311 (match_operand 0 "x86_64_immediate_operand")) | |
| 312 | |
| 111 | 313 ;; We use W prefix to denote any number of |
| 314 ;; constant-or-symbol-reference constraints | |
| 315 | |
| 316 (define_constraint "We" | |
| 317 "32-bit signed integer constant, or a symbolic reference known | |
| 318 to fit that range (for sign-extending conversion operations that | |
| 319 require non-VOIDmode immediate operands)." | |
| 320 (and (match_operand 0 "x86_64_immediate_operand") | |
| 321 (match_test "GET_MODE (op) != VOIDmode"))) | |
| 322 | |
| 323 (define_constraint "Wz" | |
| 324 "32-bit unsigned integer constant, or a symbolic reference known | |
| 325 to fit that range (for zero-extending conversion operations that | |
| 326 require non-VOIDmode immediate operands)." | |
| 327 (and (match_operand 0 "x86_64_zext_immediate_operand") | |
| 328 (match_test "GET_MODE (op) != VOIDmode"))) | |
| 329 | |
| 330 (define_constraint "Wd" | |
| 331 "128-bit integer constant where both the high and low 64-bit word | |
| 332 of it satisfies the e constraint." | |
| 333 (match_operand 0 "x86_64_hilo_int_operand")) | |
| 334 | |
| 335 (define_constraint "Wf" | |
| 336 "32-bit signed integer constant zero extended from word size | |
| 337 to double word size." | |
| 338 (match_operand 0 "x86_64_dwzext_immediate_operand")) | |
| 339 | |
| 0 | 340 (define_constraint "Z" |
| 341 "32-bit unsigned integer constant, or a symbolic reference known | |
| 342 to fit that range (for immediate operands in zero-extending x86-64 | |
| 343 instructions)." | |
| 344 (match_operand 0 "x86_64_zext_immediate_operand")) | |
| 111 | 345 |
| 346 ;; T prefix is used for different address constraints | |
| 347 ;; v - VSIB address | |
| 348 ;; s - address with no segment register | |
| 349 ;; i - address with no index and no rip | |
| 350 ;; b - address with no base and no rip | |
| 351 | |
| 352 (define_address_constraint "Tv" | |
| 353 "VSIB address operand" | |
| 354 (match_operand 0 "vsib_address_operand")) | |
| 355 | |
| 356 (define_address_constraint "Ts" | |
| 357 "Address operand without segment register" | |
| 358 (match_operand 0 "address_no_seg_operand")) | |
| 359 | |
| 360 (define_address_constraint "Ti" | |
| 361 "MPX address operand without index" | |
| 362 (match_operand 0 "address_mpx_no_index_operand")) | |
| 363 | |
| 364 (define_address_constraint "Tb" | |
| 365 "MPX address operand without base" | |
| 366 (match_operand 0 "address_mpx_no_base_operand")) |