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comparison gcc/config/ia64/vect.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 ;; IA-64 machine description for vector operations. 1 ;; IA-64 machine description for vector operations.
2 ;; Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
18 ;; <http://www.gnu.org/licenses/>. 18 ;; <http://www.gnu.org/licenses/>.
19 19
20 20
21 ;; Integer vector operations 21 ;; Integer vector operations
22 22
23 (define_mode_iterator VEC [V8QI V4HI V2SI V2SF])
23 (define_mode_iterator VECINT [V8QI V4HI V2SI]) 24 (define_mode_iterator VECINT [V8QI V4HI V2SI])
24 (define_mode_iterator VECINT12 [V8QI V4HI]) 25 (define_mode_iterator VECINT12 [V8QI V4HI])
25 (define_mode_iterator VECINT24 [V4HI V2SI]) 26 (define_mode_iterator VECINT24 [V4HI V2SI])
26 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")]) 27 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
27 (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")]) 28 (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")])
29 (define_mode_attr vecint
30 [(V8QI "V8QI") (V4HI "V4HI") (V2SI "V2SI") (V2SF "V2SI")])
28 31
29 (define_expand "mov<mode>" 32 (define_expand "mov<mode>"
30 [(set (match_operand:VECINT 0 "general_operand" "") 33 [(set (match_operand:VECINT 0 "general_operand" "")
31 (match_operand:VECINT 1 "general_operand" ""))] 34 (match_operand:VECINT 1 "general_operand" ""))]
32 "" 35 ""
273 (match_operand:SI 3 "pmpyshr_operand" "n"))))] 276 (match_operand:SI 3 "pmpyshr_operand" "n"))))]
274 "" 277 ""
275 "pmpyshr2.u %0 = %1, %2, %3" 278 "pmpyshr2.u %0 = %1, %2, %3"
276 [(set_attr "itanium_class" "mmmul")]) 279 [(set_attr "itanium_class" "mmmul")])
277 280
278 (define_insn "pmpy2_even" 281 (define_expand "smulv4hi3_highpart"
282 [(match_operand:V4HI 0 "gr_register_operand")
283 (match_operand:V4HI 1 "gr_register_operand")
284 (match_operand:V4HI 2 "gr_register_operand")]
285 ""
286 {
287 emit_insn (gen_pmpyshr2 (operands[0], operands[1],
288 operands[2], GEN_INT (16)));
289 DONE;
290 })
291
292 (define_expand "umulv4hi3_highpart"
293 [(match_operand:V4HI 0 "gr_register_operand")
294 (match_operand:V4HI 1 "gr_register_operand")
295 (match_operand:V4HI 2 "gr_register_operand")]
296 ""
297 {
298 emit_insn (gen_pmpyshr2_u (operands[0], operands[1],
299 operands[2], GEN_INT (16)));
300 DONE;
301 })
302
303 (define_insn "vec_widen_smult_even_v4hi"
279 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 304 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
280 (mult:V2SI 305 (mult:V2SI
281 (vec_select:V2SI 306 (vec_select:V2SI
282 (sign_extend:V4SI 307 (sign_extend:V4SI
283 (match_operand:V4HI 1 "gr_register_operand" "r")) 308 (match_operand:V4HI 1 "gr_register_operand" "r"))
294 else 319 else
295 return "%,pmpy2.r %0 = %1, %2"; 320 return "%,pmpy2.r %0 = %1, %2";
296 } 321 }
297 [(set_attr "itanium_class" "mmshf")]) 322 [(set_attr "itanium_class" "mmshf")])
298 323
299 (define_insn "pmpy2_odd" 324 (define_insn "vec_widen_smult_odd_v4hi"
300 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 325 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
301 (mult:V2SI 326 (mult:V2SI
302 (vec_select:V2SI 327 (vec_select:V2SI
303 (sign_extend:V4SI 328 (sign_extend:V4SI
304 (match_operand:V4HI 1 "gr_register_operand" "r")) 329 (match_operand:V4HI 1 "gr_register_operand" "r"))
398 423
399 /* T0 = CDBA. */ 424 /* T0 = CDBA. */
400 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx, 425 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx,
401 GEN_INT (3), const2_rtx)); 426 GEN_INT (3), const2_rtx));
402 x = gen_rtx_VEC_SELECT (V4HImode, op1h, x); 427 x = gen_rtx_VEC_SELECT (V4HImode, op1h, x);
403 emit_insn (gen_rtx_SET (VOIDmode, t0, x)); 428 emit_insn (gen_rtx_SET (t0, x));
404 429
405 /* T1 = DZ.l, CY.l, BX.l, AW.l. */ 430 /* T1 = DZ.l, CY.l, BX.l, AW.l. */
406 emit_insn (gen_mulv4hi3 (t1, op1h, op2h)); 431 emit_insn (gen_mulv4hi3 (t1, op1h, op2h));
407 432
408 /* T2 = DZ.h, CY.h, BX.h, AW.h. */ 433 /* T2 = DZ.h, CY.h, BX.h, AW.h. */
597 { 622 {
598 ia64_expand_widen_sum (operands, false); 623 ia64_expand_widen_sum (operands, false);
599 DONE; 624 DONE;
600 }) 625 })
601 626
602 (define_expand "udot_prodv8qi" 627 (define_expand "vcond<mode><mode>"
603 [(match_operand:V2SI 0 "gr_register_operand" "")
604 (match_operand:V8QI 1 "gr_register_operand" "")
605 (match_operand:V8QI 2 "gr_register_operand" "")
606 (match_operand:V2SI 3 "gr_register_operand" "")]
607 ""
608 {
609 ia64_expand_dot_prod_v8qi (operands, true);
610 DONE;
611 })
612
613 (define_expand "sdot_prodv8qi"
614 [(match_operand:V2SI 0 "gr_register_operand" "")
615 (match_operand:V8QI 1 "gr_register_operand" "")
616 (match_operand:V8QI 2 "gr_register_operand" "")
617 (match_operand:V2SI 3 "gr_register_operand" "")]
618 ""
619 {
620 ia64_expand_dot_prod_v8qi (operands, false);
621 DONE;
622 })
623
624 (define_expand "sdot_prodv4hi"
625 [(match_operand:V2SI 0 "gr_register_operand" "")
626 (match_operand:V4HI 1 "gr_register_operand" "")
627 (match_operand:V4HI 2 "gr_register_operand" "")
628 (match_operand:V2SI 3 "gr_register_operand" "")]
629 ""
630 {
631 rtx e, o, t;
632
633 e = gen_reg_rtx (V2SImode);
634 o = gen_reg_rtx (V2SImode);
635 t = gen_reg_rtx (V2SImode);
636
637 emit_insn (gen_pmpy2_even (e, operands[1], operands[2]));
638 emit_insn (gen_pmpy2_odd (o, operands[1], operands[2]));
639 emit_insn (gen_addv2si3 (t, e, operands[3]));
640 emit_insn (gen_addv2si3 (operands[0], t, o));
641 DONE;
642 })
643
644 (define_expand "udot_prodv4hi"
645 [(match_operand:V2SI 0 "gr_register_operand" "")
646 (match_operand:V4HI 1 "gr_register_operand" "")
647 (match_operand:V4HI 2 "gr_register_operand" "")
648 (match_operand:V2SI 3 "gr_register_operand" "")]
649 ""
650 {
651 rtx l, h, t;
652
653 l = gen_reg_rtx (V2SImode);
654 h = gen_reg_rtx (V2SImode);
655 t = gen_reg_rtx (V2SImode);
656
657 emit_insn (gen_vec_widen_umult_lo_v4hi (l, operands[1], operands[2]));
658 emit_insn (gen_vec_widen_umult_hi_v4hi (h, operands[1], operands[2]));
659 emit_insn (gen_addv2si3 (t, l, operands[3]));
660 emit_insn (gen_addv2si3 (operands[0], t, h));
661 DONE;
662 })
663
664 (define_expand "vcond<mode>"
665 [(set (match_operand:VECINT 0 "gr_register_operand" "") 628 [(set (match_operand:VECINT 0 "gr_register_operand" "")
666 (if_then_else:VECINT 629 (if_then_else:VECINT
667 (match_operator 3 "" 630 (match_operator 3 ""
668 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") 631 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
669 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) 632 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
673 { 636 {
674 ia64_expand_vecint_cmov (operands); 637 ia64_expand_vecint_cmov (operands);
675 DONE; 638 DONE;
676 }) 639 })
677 640
678 (define_expand "vcondu<mode>" 641 (define_expand "vcondu<mode><mode>"
679 [(set (match_operand:VECINT 0 "gr_register_operand" "") 642 [(set (match_operand:VECINT 0 "gr_register_operand" "")
680 (if_then_else:VECINT 643 (if_then_else:VECINT
681 (match_operator 3 "" 644 (match_operator 3 ""
682 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") 645 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
683 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) 646 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
754 else 717 else
755 return "%,pack4.sss %0 = %r1, %r2"; 718 return "%,pack4.sss %0 = %r1, %r2";
756 } 719 }
757 [(set_attr "itanium_class" "mmshf")]) 720 [(set_attr "itanium_class" "mmshf")])
758 721
759 (define_insn "vec_interleave_lowv8qi" 722 (define_insn "*vec_interleave_lowv8qi"
760 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 723 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
761 (vec_select:V8QI 724 (vec_select:V8QI
762 (vec_concat:V16QI 725 (vec_concat:V16QI
763 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 726 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
764 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 727 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
774 else 737 else
775 return "%,unpack1.l %0 = %r2, %r1"; 738 return "%,unpack1.l %0 = %r2, %r1";
776 } 739 }
777 [(set_attr "itanium_class" "mmshf")]) 740 [(set_attr "itanium_class" "mmshf")])
778 741
779 (define_insn "vec_interleave_highv8qi" 742 (define_insn "*vec_interleave_highv8qi"
780 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 743 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
781 (vec_select:V8QI 744 (vec_select:V8QI
782 (vec_concat:V16QI 745 (vec_concat:V16QI
783 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 746 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
784 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 747 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
794 else 757 else
795 return "%,unpack1.h %0 = %r2, %r1"; 758 return "%,unpack1.h %0 = %r2, %r1";
796 } 759 }
797 [(set_attr "itanium_class" "mmshf")]) 760 [(set_attr "itanium_class" "mmshf")])
798 761
799 (define_insn "mix1_even" 762 (define_insn "*mix1_even"
800 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 763 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
801 (vec_select:V8QI 764 (vec_select:V8QI
802 (vec_concat:V16QI 765 (vec_concat:V16QI
803 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 766 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
804 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 767 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
814 else 777 else
815 return "%,mix1.r %0 = %r2, %r1"; 778 return "%,mix1.r %0 = %r2, %r1";
816 } 779 }
817 [(set_attr "itanium_class" "mmshf")]) 780 [(set_attr "itanium_class" "mmshf")])
818 781
819 (define_insn "mix1_odd" 782 (define_insn "*mix1_odd"
820 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 783 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
821 (vec_select:V8QI 784 (vec_select:V8QI
822 (vec_concat:V16QI 785 (vec_concat:V16QI
823 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 786 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
824 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 787 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
870 (const_int 3) (const_int 7)])))] 833 (const_int 3) (const_int 7)])))]
871 "" 834 ""
872 "mux1 %0 = %1, @shuf" 835 "mux1 %0 = %1, @shuf"
873 [(set_attr "itanium_class" "mmshf")]) 836 [(set_attr "itanium_class" "mmshf")])
874 837
875 (define_insn "mux1_alt" 838 (define_insn "*mux1_alt"
876 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 839 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
877 (vec_select:V8QI 840 (vec_select:V8QI
878 (match_operand:V8QI 1 "gr_register_operand" "r") 841 (match_operand:V8QI 1 "gr_register_operand" "r")
879 (parallel [(const_int 0) (const_int 2) 842 (parallel [(const_int 0) (const_int 2)
880 (const_int 4) (const_int 6) 843 (const_int 4) (const_int 6)
898 (match_dup 2)])))] 861 (match_dup 2)])))]
899 "" 862 ""
900 "mux1 %0 = %1, @brcst" 863 "mux1 %0 = %1, @brcst"
901 [(set_attr "itanium_class" "mmshf")]) 864 [(set_attr "itanium_class" "mmshf")])
902 865
903 (define_insn "*mux1_brcst_qi" 866 (define_insn "mux1_brcst_qi"
904 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 867 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
905 (vec_duplicate:V8QI 868 (vec_duplicate:V8QI
906 (match_operand:QI 1 "gr_register_operand" "r")))] 869 (match_operand:QI 1 "gr_register_operand" "r")))]
907 "" 870 ""
908 "mux1 %0 = %1, @brcst" 871 "mux1 %0 = %1, @brcst"
909 [(set_attr "itanium_class" "mmshf")]) 872 [(set_attr "itanium_class" "mmshf")])
910 873
911 (define_expand "vec_extract_evenv8qi" 874 (define_insn "*vec_interleave_lowv4hi"
912 [(match_operand:V8QI 0 "gr_register_operand" "")
913 (match_operand:V8QI 1 "gr_register_operand" "")
914 (match_operand:V8QI 2 "gr_register_operand" "")]
915 ""
916 {
917 rtx temp = gen_reg_rtx (V8QImode);
918 emit_insn (gen_mix1_even (temp, operands[1], operands[2]));
919 emit_insn (gen_mux1_alt (operands[0], temp));
920 DONE;
921 })
922
923 (define_expand "vec_extract_oddv8qi"
924 [(match_operand:V8QI 0 "gr_register_operand" "")
925 (match_operand:V8QI 1 "gr_register_operand" "")
926 (match_operand:V8QI 2 "gr_register_operand" "")]
927 ""
928 {
929 rtx temp = gen_reg_rtx (V8QImode);
930 emit_insn (gen_mix1_odd (temp, operands[1], operands[2]));
931 emit_insn (gen_mux1_alt (operands[0], temp));
932 DONE;
933 })
934
935 (define_insn "vec_interleave_lowv4hi"
936 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 875 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
937 (vec_select:V4HI 876 (vec_select:V4HI
938 (vec_concat:V8HI 877 (vec_concat:V8HI
939 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 878 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
940 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 879 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
948 else 887 else
949 return "%,unpack2.l %0 = %r2, %r1"; 888 return "%,unpack2.l %0 = %r2, %r1";
950 } 889 }
951 [(set_attr "itanium_class" "mmshf")]) 890 [(set_attr "itanium_class" "mmshf")])
952 891
953 (define_insn "vec_interleave_highv4hi" 892 (define_insn "*vec_interleave_highv4hi"
954 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 893 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
955 (vec_select:V4HI 894 (vec_select:V4HI
956 (vec_concat:V8HI 895 (vec_concat:V8HI
957 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 896 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
958 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 897 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
1032 operands[2] = GEN_INT (mask); 971 operands[2] = GEN_INT (mask);
1033 return "%,mux2 %0 = %1, %2"; 972 return "%,mux2 %0 = %1, %2";
1034 } 973 }
1035 [(set_attr "itanium_class" "mmshf")]) 974 [(set_attr "itanium_class" "mmshf")])
1036 975
1037 (define_expand "vec_extract_evenodd_helper"
1038 [(set (match_operand:V4HI 0 "gr_register_operand" "")
1039 (vec_select:V4HI
1040 (match_operand:V4HI 1 "gr_register_operand" "")
1041 (parallel [(const_int 0) (const_int 2)
1042 (const_int 1) (const_int 3)])))]
1043 "")
1044
1045 (define_expand "vec_extract_evenv4hi"
1046 [(match_operand:V4HI 0 "gr_register_operand")
1047 (match_operand:V4HI 1 "gr_reg_or_0_operand")
1048 (match_operand:V4HI 2 "gr_reg_or_0_operand")]
1049 ""
1050 {
1051 rtx temp = gen_reg_rtx (V4HImode);
1052 emit_insn (gen_mix2_even (temp, operands[1], operands[2]));
1053 emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
1054 DONE;
1055 })
1056
1057 (define_expand "vec_extract_oddv4hi"
1058 [(match_operand:V4HI 0 "gr_register_operand")
1059 (match_operand:V4HI 1 "gr_reg_or_0_operand")
1060 (match_operand:V4HI 2 "gr_reg_or_0_operand")]
1061 ""
1062 {
1063 rtx temp = gen_reg_rtx (V4HImode);
1064 emit_insn (gen_mix2_odd (temp, operands[1], operands[2]));
1065 emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
1066 DONE;
1067 })
1068
1069 (define_insn "*mux2_brcst_hi" 976 (define_insn "*mux2_brcst_hi"
1070 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 977 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
1071 (vec_duplicate:V4HI 978 (vec_duplicate:V4HI
1072 (match_operand:HI 1 "gr_register_operand" "r")))] 979 (match_operand:HI 1 "gr_register_operand" "r")))]
1073 "" 980 ""
1074 "mux2 %0 = %1, 0" 981 "mux2 %0 = %1, 0"
1075 [(set_attr "itanium_class" "mmshf")]) 982 [(set_attr "itanium_class" "mmshf")])
1076 983
1077 (define_insn "vec_interleave_lowv2si" 984 (define_insn "*vec_interleave_lowv2si"
1078 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 985 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1079 (vec_select:V2SI 986 (vec_select:V2SI
1080 (vec_concat:V4SI 987 (vec_concat:V4SI
1081 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") 988 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1082 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) 989 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1089 else 996 else
1090 return "%,unpack4.l %0 = %r2, %r1"; 997 return "%,unpack4.l %0 = %r2, %r1";
1091 } 998 }
1092 [(set_attr "itanium_class" "mmshf")]) 999 [(set_attr "itanium_class" "mmshf")])
1093 1000
1094 (define_insn "vec_interleave_highv2si" 1001 (define_insn "*vec_interleave_highv2si"
1095 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 1002 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1096 (vec_select:V2SI 1003 (vec_select:V2SI
1097 (vec_concat:V4SI 1004 (vec_concat:V4SI
1098 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") 1005 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1099 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) 1006 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1106 else 1013 else
1107 return "%,unpack4.h %0 = %r2, %r1"; 1014 return "%,unpack4.h %0 = %r2, %r1";
1108 } 1015 }
1109 [(set_attr "itanium_class" "mmshf")]) 1016 [(set_attr "itanium_class" "mmshf")])
1110 1017
1111 (define_expand "vec_extract_evenv2si" 1018 (define_expand "vec_initv2sisi"
1112 [(match_operand:V2SI 0 "gr_register_operand" "")
1113 (match_operand:V2SI 1 "gr_register_operand" "")
1114 (match_operand:V2SI 2 "gr_register_operand" "")]
1115 ""
1116 {
1117 if (TARGET_BIG_ENDIAN)
1118 emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
1119 operands[2]));
1120 else
1121 emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
1122 operands[2]));
1123 DONE;
1124 })
1125
1126 (define_expand "vec_extract_oddv2si"
1127 [(match_operand:V2SI 0 "gr_register_operand" "")
1128 (match_operand:V2SI 1 "gr_register_operand" "")
1129 (match_operand:V2SI 2 "gr_register_operand" "")]
1130 ""
1131 {
1132 if (TARGET_BIG_ENDIAN)
1133 emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
1134 operands[2]));
1135 else
1136 emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
1137 operands[2]));
1138 DONE;
1139 })
1140
1141 (define_expand "vec_initv2si"
1142 [(match_operand:V2SI 0 "gr_register_operand" "") 1019 [(match_operand:V2SI 0 "gr_register_operand" "")
1143 (match_operand 1 "" "")] 1020 (match_operand 1 "" "")]
1144 "" 1021 ""
1145 { 1022 {
1146 rtx op1 = XVECEXP (operands[1], 0, 0); 1023 rtx op1 = XVECEXP (operands[1], 0, 0);
1158 op1 = force_reg (SImode, op1); 1035 op1 = force_reg (SImode, op1);
1159 if (!gr_reg_or_0_operand (op2, SImode)) 1036 if (!gr_reg_or_0_operand (op2, SImode))
1160 op2 = force_reg (SImode, op2); 1037 op2 = force_reg (SImode, op2);
1161 1038
1162 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2); 1039 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
1163 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); 1040 emit_insn (gen_rtx_SET (operands[0], x));
1164 DONE; 1041 DONE;
1165 }) 1042 })
1166 1043
1167 (define_insn "*vecinit_v2si" 1044 (define_insn "*vecinit_v2si"
1168 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 1045 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1380 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); 1257 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1381 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp)); 1258 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp));
1382 DONE; 1259 DONE;
1383 }) 1260 })
1384 1261
1385 (define_expand "vcondv2sf" 1262 (define_expand "vcondv2sfv2sf"
1386 [(set (match_operand:V2SF 0 "fr_register_operand" "") 1263 [(set (match_operand:V2SF 0 "fr_register_operand" "")
1387 (if_then_else:V2SF 1264 (if_then_else:V2SF
1388 (match_operator 3 "" 1265 (match_operator 3 ""
1389 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "") 1266 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "")
1390 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")]) 1267 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")])
1394 { 1271 {
1395 rtx x, cmp; 1272 rtx x, cmp;
1396 1273
1397 cmp = gen_reg_rtx (V2SFmode); 1274 cmp = gen_reg_rtx (V2SFmode);
1398 PUT_MODE (operands[3], V2SFmode); 1275 PUT_MODE (operands[3], V2SFmode);
1399 emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3])); 1276 emit_insn (gen_rtx_SET (cmp, operands[3]));
1400 1277
1401 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]); 1278 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
1402 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); 1279 emit_insn (gen_rtx_SET (operands[0], x));
1403 DONE; 1280 DONE;
1404 }) 1281 })
1405 1282
1406 (define_insn "*fpcmp" 1283 (define_insn "*fpcmp"
1407 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1284 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1420 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))] 1297 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))]
1421 "" 1298 ""
1422 "fselect %0 = %F2, %F3, %1" 1299 "fselect %0 = %F2, %F3, %1"
1423 [(set_attr "itanium_class" "fmisc")]) 1300 [(set_attr "itanium_class" "fmisc")])
1424 1301
1425 (define_expand "vec_initv2sf" 1302 (define_expand "vec_initv2sfsf"
1426 [(match_operand:V2SF 0 "fr_register_operand" "") 1303 [(match_operand:V2SF 0 "fr_register_operand" "")
1427 (match_operand 1 "" "")] 1304 (match_operand 1 "" "")]
1428 "" 1305 ""
1429 { 1306 {
1430 rtx op1 = XVECEXP (operands[1], 0, 0); 1307 rtx op1 = XVECEXP (operands[1], 0, 0);
1477 else 1354 else
1478 return "%,fswap %0 = %F1, %F2"; 1355 return "%,fswap %0 = %F1, %F2";
1479 } 1356 }
1480 [(set_attr "itanium_class" "fmisc")]) 1357 [(set_attr "itanium_class" "fmisc")])
1481 1358
1482 (define_insn "vec_interleave_highv2sf" 1359 (define_insn "*vec_interleave_highv2sf"
1483 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1360 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1484 (vec_select:V2SF 1361 (vec_select:V2SF
1485 (vec_concat:V4SF 1362 (vec_concat:V4SF
1486 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1363 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1487 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1364 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1494 else 1371 else
1495 return "%,fmix.l %0 = %F2, %F1"; 1372 return "%,fmix.l %0 = %F2, %F1";
1496 } 1373 }
1497 [(set_attr "itanium_class" "fmisc")]) 1374 [(set_attr "itanium_class" "fmisc")])
1498 1375
1499 (define_insn "vec_interleave_lowv2sf" 1376 (define_insn "*vec_interleave_lowv2sf"
1500 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1377 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1501 (vec_select:V2SF 1378 (vec_select:V2SF
1502 (vec_concat:V4SF 1379 (vec_concat:V4SF
1503 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1380 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1504 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1381 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1528 else 1405 else
1529 return "%,fmix.lr %0 = %F2, %F1"; 1406 return "%,fmix.lr %0 = %F2, %F1";
1530 } 1407 }
1531 [(set_attr "itanium_class" "fmisc")]) 1408 [(set_attr "itanium_class" "fmisc")])
1532 1409
1533 (define_expand "vec_extract_evenv2sf"
1534 [(match_operand:V2SF 0 "gr_register_operand" "")
1535 (match_operand:V2SF 1 "gr_register_operand" "")
1536 (match_operand:V2SF 2 "gr_register_operand" "")]
1537 ""
1538 {
1539 if (TARGET_BIG_ENDIAN)
1540 emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
1541 operands[2]));
1542 else
1543 emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
1544 operands[2]));
1545 DONE;
1546 })
1547
1548 (define_expand "vec_extract_oddv2sf"
1549 [(match_operand:V2SF 0 "gr_register_operand" "")
1550 (match_operand:V2SF 1 "gr_register_operand" "")
1551 (match_operand:V2SF 2 "gr_register_operand" "")]
1552 ""
1553 {
1554 if (TARGET_BIG_ENDIAN)
1555 emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
1556 operands[2]));
1557 else
1558 emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
1559 operands[2]));
1560 DONE;
1561 })
1562
1563 (define_expand "vec_setv2sf" 1410 (define_expand "vec_setv2sf"
1564 [(match_operand:V2SF 0 "fr_register_operand" "") 1411 [(match_operand:V2SF 0 "fr_register_operand" "")
1565 (match_operand:SF 1 "fr_register_operand" "") 1412 (match_operand:SF 1 "fr_register_operand" "")
1566 (match_operand 2 "const_int_operand" "")] 1413 (match_operand 2 "const_int_operand" "")]
1567 "" 1414 ""
1568 { 1415 {
1569 rtx op0 = operands[0]; 1416 ia64_expand_vec_setv2sf (operands);
1570 rtx tmp = gen_reg_rtx (V2SFmode);
1571
1572 emit_insn (gen_fpack (tmp, operands[1], CONST0_RTX (SFmode)));
1573
1574 switch (INTVAL (operands[2]))
1575 {
1576 case 0:
1577 emit_insn (gen_fmix_lr (op0, tmp, op0));
1578 break;
1579 case 1:
1580 emit_insn (gen_vec_interleave_lowv2sf (op0, op0, tmp));
1581 break;
1582 default:
1583 gcc_unreachable ();
1584 }
1585 DONE; 1417 DONE;
1586 }) 1418 })
1587 1419
1588 (define_insn_and_split "*vec_extractv2sf_0_le" 1420 (define_insn_and_split "*vec_extractv2sf_0_le"
1589 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m") 1421 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m")
1649 [(set (match_dup 0) (match_dup 1))] 1481 [(set (match_dup 0) (match_dup 1))]
1650 { 1482 {
1651 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); 1483 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1652 }) 1484 })
1653 1485
1654 (define_expand "vec_extractv2sf" 1486 (define_expand "vec_extractv2sfsf"
1655 [(set (match_operand:SF 0 "register_operand" "") 1487 [(set (match_operand:SF 0 "register_operand" "")
1656 (unspec:SF [(match_operand:V2SF 1 "register_operand" "") 1488 (unspec:SF [(match_operand:V2SF 1 "register_operand" "")
1657 (match_operand:DI 2 "const_int_operand" "")] 1489 (match_operand:DI 2 "const_int_operand" "")]
1658 UNSPEC_VECT_EXTR))] 1490 UNSPEC_VECT_EXTR))]
1659 "" 1491 ""
1701 (match_operand:V4HI 2 "gr_register_operand" "")] 1533 (match_operand:V4HI 2 "gr_register_operand" "")]
1702 "" 1534 ""
1703 { 1535 {
1704 rtx op1 = gen_lowpart (V8QImode, operands[1]); 1536 rtx op1 = gen_lowpart (V8QImode, operands[1]);
1705 rtx op2 = gen_lowpart (V8QImode, operands[2]); 1537 rtx op2 = gen_lowpart (V8QImode, operands[2]);
1706 if (TARGET_BIG_ENDIAN) 1538 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
1707 emit_insn (gen_vec_extract_oddv8qi (operands[0], op1, op2));
1708 else
1709 emit_insn (gen_vec_extract_evenv8qi (operands[0], op1, op2));
1710 DONE; 1539 DONE;
1711 }) 1540 })
1712 1541
1713 (define_expand "vec_pack_trunc_v2si" 1542 (define_expand "vec_pack_trunc_v2si"
1714 [(match_operand:V4HI 0 "gr_register_operand" "") 1543 [(match_operand:V4HI 0 "gr_register_operand" "")
1716 (match_operand:V2SI 2 "gr_register_operand" "")] 1545 (match_operand:V2SI 2 "gr_register_operand" "")]
1717 "" 1546 ""
1718 { 1547 {
1719 rtx op1 = gen_lowpart (V4HImode, operands[1]); 1548 rtx op1 = gen_lowpart (V4HImode, operands[1]);
1720 rtx op2 = gen_lowpart (V4HImode, operands[2]); 1549 rtx op2 = gen_lowpart (V4HImode, operands[2]);
1721 if (TARGET_BIG_ENDIAN) 1550 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
1722 emit_insn (gen_vec_extract_oddv4hi (operands[0], op1, op2)); 1551 DONE;
1723 else 1552 })
1724 emit_insn (gen_vec_extract_evenv4hi (operands[0], op1, op2)); 1553
1725 DONE; 1554 (define_expand "vec_perm_const<mode>"
1555 [(match_operand:VEC 0 "register_operand" "")
1556 (match_operand:VEC 1 "register_operand" "")
1557 (match_operand:VEC 2 "register_operand" "")
1558 (match_operand:<vecint> 3 "" "")]
1559 ""
1560 {
1561 if (ia64_expand_vec_perm_const (operands))
1562 DONE;
1563 else
1564 FAIL;
1726 }) 1565 })
1727 1566
1728 ;; Missing operations 1567 ;; Missing operations
1729 ;; fprcpa 1568 ;; fprcpa
1730 ;; fpsqrta 1569 ;; fpsqrta