--- a/gcc/config/ia64/vect.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/ia64/vect.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; IA-64 machine description for vector operations.
-;; Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -20,11 +20,14 @@
 
 ;; Integer vector operations
 
+(define_mode_iterator VEC [V8QI V4HI V2SI V2SF])
 (define_mode_iterator VECINT [V8QI V4HI V2SI])
 (define_mode_iterator VECINT12 [V8QI V4HI])
 (define_mode_iterator VECINT24 [V4HI V2SI])
 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
 (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")])
+(define_mode_attr vecint
+  [(V8QI "V8QI") (V4HI "V4HI") (V2SI "V2SI") (V2SF "V2SI")])
 
 (define_expand "mov<mode>"
   [(set (match_operand:VECINT 0 "general_operand" "")
@@ -275,7 +278,29 @@
   "pmpyshr2.u %0 = %1, %2, %3"
   [(set_attr "itanium_class" "mmmul")])
 
-(define_insn "pmpy2_even"
+(define_expand "smulv4hi3_highpart"
+  [(match_operand:V4HI 0 "gr_register_operand")
+   (match_operand:V4HI 1 "gr_register_operand")
+   (match_operand:V4HI 2 "gr_register_operand")]
+  ""
+{
+  emit_insn (gen_pmpyshr2 (operands[0], operands[1],
+			   operands[2], GEN_INT (16)));
+  DONE;
+})
+
+(define_expand "umulv4hi3_highpart"
+  [(match_operand:V4HI 0 "gr_register_operand")
+   (match_operand:V4HI 1 "gr_register_operand")
+   (match_operand:V4HI 2 "gr_register_operand")]
+  ""
+{
+  emit_insn (gen_pmpyshr2_u (operands[0], operands[1],
+			     operands[2], GEN_INT (16)));
+  DONE;
+})
+
+(define_insn "vec_widen_smult_even_v4hi"
   [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
 	(mult:V2SI
 	  (vec_select:V2SI
@@ -296,7 +321,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "pmpy2_odd"
+(define_insn "vec_widen_smult_odd_v4hi"
   [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
 	(mult:V2SI
 	  (vec_select:V2SI
@@ -400,7 +425,7 @@
   x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx,
 					     GEN_INT (3), const2_rtx));
   x = gen_rtx_VEC_SELECT (V4HImode, op1h, x);
-  emit_insn (gen_rtx_SET (VOIDmode, t0, x));
+  emit_insn (gen_rtx_SET (t0, x));
 
   /* T1 = DZ.l, CY.l, BX.l, AW.l.  */
   emit_insn (gen_mulv4hi3 (t1, op1h, op2h));
@@ -599,69 +624,7 @@
   DONE;
 })
 
-(define_expand "udot_prodv8qi"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V8QI 1 "gr_register_operand" "")
-   (match_operand:V8QI 2 "gr_register_operand" "")
-   (match_operand:V2SI 3 "gr_register_operand" "")]
-  ""
-{
-  ia64_expand_dot_prod_v8qi (operands, true);
-  DONE;
-})
-
-(define_expand "sdot_prodv8qi"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V8QI 1 "gr_register_operand" "")
-   (match_operand:V8QI 2 "gr_register_operand" "")
-   (match_operand:V2SI 3 "gr_register_operand" "")]
-  ""
-{
-  ia64_expand_dot_prod_v8qi (operands, false);
-  DONE;
-})
-
-(define_expand "sdot_prodv4hi"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V4HI 1 "gr_register_operand" "")
-   (match_operand:V4HI 2 "gr_register_operand" "")
-   (match_operand:V2SI 3 "gr_register_operand" "")]
-  ""
-{
-  rtx e, o, t;
-
-  e = gen_reg_rtx (V2SImode);
-  o = gen_reg_rtx (V2SImode);
-  t = gen_reg_rtx (V2SImode);
-
-  emit_insn (gen_pmpy2_even (e, operands[1], operands[2]));
-  emit_insn (gen_pmpy2_odd (o, operands[1], operands[2]));
-  emit_insn (gen_addv2si3 (t, e, operands[3]));
-  emit_insn (gen_addv2si3 (operands[0], t, o));
-  DONE;
-})
-
-(define_expand "udot_prodv4hi"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V4HI 1 "gr_register_operand" "")
-   (match_operand:V4HI 2 "gr_register_operand" "")
-   (match_operand:V2SI 3 "gr_register_operand" "")]
-  ""
-{
-  rtx l, h, t;
-
-  l = gen_reg_rtx (V2SImode);
-  h = gen_reg_rtx (V2SImode);
-  t = gen_reg_rtx (V2SImode);
-
-  emit_insn (gen_vec_widen_umult_lo_v4hi (l, operands[1], operands[2]));
-  emit_insn (gen_vec_widen_umult_hi_v4hi (h, operands[1], operands[2]));
-  emit_insn (gen_addv2si3 (t, l, operands[3]));
-  emit_insn (gen_addv2si3 (operands[0], t, h));
-  DONE;
-})
-
-(define_expand "vcond<mode>"
+(define_expand "vcond<mode><mode>"
   [(set (match_operand:VECINT 0 "gr_register_operand" "")
 	(if_then_else:VECINT
 	  (match_operator 3 "" 
@@ -675,7 +638,7 @@
   DONE;
 })
 
-(define_expand "vcondu<mode>"
+(define_expand "vcondu<mode><mode>"
   [(set (match_operand:VECINT 0 "gr_register_operand" "")
 	(if_then_else:VECINT
 	  (match_operator 3 "" 
@@ -756,7 +719,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "vec_interleave_lowv8qi"
+(define_insn "*vec_interleave_lowv8qi"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_select:V8QI
 	  (vec_concat:V16QI
@@ -776,7 +739,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "vec_interleave_highv8qi"
+(define_insn "*vec_interleave_highv8qi"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_select:V8QI
 	  (vec_concat:V16QI
@@ -796,7 +759,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "mix1_even"
+(define_insn "*mix1_even"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_select:V8QI
 	  (vec_concat:V16QI
@@ -816,7 +779,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "mix1_odd"
+(define_insn "*mix1_odd"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_select:V8QI
 	  (vec_concat:V16QI
@@ -872,7 +835,7 @@
   "mux1 %0 = %1, @shuf"
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "mux1_alt"
+(define_insn "*mux1_alt"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_select:V8QI
 	  (match_operand:V8QI 1 "gr_register_operand" "r")
@@ -900,7 +863,7 @@
   "mux1 %0 = %1, @brcst"
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "*mux1_brcst_qi"
+(define_insn "mux1_brcst_qi"
   [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
 	(vec_duplicate:V8QI
 	  (match_operand:QI 1 "gr_register_operand" "r")))]
@@ -908,31 +871,7 @@
   "mux1 %0 = %1, @brcst"
   [(set_attr "itanium_class" "mmshf")])
 
-(define_expand "vec_extract_evenv8qi"
-  [(match_operand:V8QI 0 "gr_register_operand" "")
-   (match_operand:V8QI 1 "gr_register_operand" "")
-   (match_operand:V8QI 2 "gr_register_operand" "")]
-  ""
-{
-  rtx temp = gen_reg_rtx (V8QImode);
-  emit_insn (gen_mix1_even (temp, operands[1], operands[2]));
-  emit_insn (gen_mux1_alt (operands[0], temp));
-  DONE;
-})
-
-(define_expand "vec_extract_oddv8qi"
-  [(match_operand:V8QI 0 "gr_register_operand" "")
-   (match_operand:V8QI 1 "gr_register_operand" "")
-   (match_operand:V8QI 2 "gr_register_operand" "")]
-  ""
-{
-  rtx temp = gen_reg_rtx (V8QImode);
-  emit_insn (gen_mix1_odd (temp, operands[1], operands[2]));
-  emit_insn (gen_mux1_alt (operands[0], temp));
-  DONE;
-})
-
-(define_insn "vec_interleave_lowv4hi"
+(define_insn "*vec_interleave_lowv4hi"
   [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
 	(vec_select:V4HI
 	  (vec_concat:V8HI
@@ -950,7 +889,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "vec_interleave_highv4hi"
+(define_insn "*vec_interleave_highv4hi"
   [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
 	(vec_select:V4HI
 	  (vec_concat:V8HI
@@ -1034,38 +973,6 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_expand "vec_extract_evenodd_helper"
-  [(set (match_operand:V4HI 0 "gr_register_operand" "")
-	(vec_select:V4HI
-	  (match_operand:V4HI 1 "gr_register_operand" "")
-	  (parallel [(const_int 0) (const_int 2)
-		     (const_int 1) (const_int 3)])))]
-  "")
-
-(define_expand "vec_extract_evenv4hi"
-  [(match_operand:V4HI 0 "gr_register_operand")
-   (match_operand:V4HI 1 "gr_reg_or_0_operand")
-   (match_operand:V4HI 2 "gr_reg_or_0_operand")]
-  ""
-{
-  rtx temp = gen_reg_rtx (V4HImode);
-  emit_insn (gen_mix2_even (temp, operands[1], operands[2]));
-  emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
-  DONE;
-})
-
-(define_expand "vec_extract_oddv4hi"
-  [(match_operand:V4HI 0 "gr_register_operand")
-   (match_operand:V4HI 1 "gr_reg_or_0_operand")
-   (match_operand:V4HI 2 "gr_reg_or_0_operand")]
-  ""
-{
-  rtx temp = gen_reg_rtx (V4HImode);
-  emit_insn (gen_mix2_odd (temp, operands[1], operands[2]));
-  emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
-  DONE;
-})
-
 (define_insn "*mux2_brcst_hi"
   [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
 	(vec_duplicate:V4HI
@@ -1074,7 +981,7 @@
   "mux2 %0 = %1, 0"
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "vec_interleave_lowv2si"
+(define_insn "*vec_interleave_lowv2si"
   [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
 	(vec_select:V2SI
 	  (vec_concat:V4SI
@@ -1091,7 +998,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_insn "vec_interleave_highv2si"
+(define_insn "*vec_interleave_highv2si"
   [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
 	(vec_select:V2SI
 	  (vec_concat:V4SI
@@ -1108,37 +1015,7 @@
 }
   [(set_attr "itanium_class" "mmshf")])
 
-(define_expand "vec_extract_evenv2si"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V2SI 1 "gr_register_operand" "")
-   (match_operand:V2SI 2 "gr_register_operand" "")]
-  ""
-{
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
-					    operands[2]));
-  else
-    emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
-					   operands[2]));
-  DONE;
-})
-
-(define_expand "vec_extract_oddv2si"
-  [(match_operand:V2SI 0 "gr_register_operand" "")
-   (match_operand:V2SI 1 "gr_register_operand" "")
-   (match_operand:V2SI 2 "gr_register_operand" "")]
-  ""
-{
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
-					   operands[2]));
-  else
-    emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
-					    operands[2]));
-  DONE;
-})
-
-(define_expand "vec_initv2si"
+(define_expand "vec_initv2sisi"
   [(match_operand:V2SI 0 "gr_register_operand" "")
    (match_operand 1 "" "")]
   ""
@@ -1160,7 +1037,7 @@
     op2 = force_reg (SImode, op2);
 
   x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  emit_insn (gen_rtx_SET (operands[0], x));
   DONE;
 })
 
@@ -1382,7 +1259,7 @@
   DONE;
 })
 
-(define_expand "vcondv2sf"
+(define_expand "vcondv2sfv2sf"
   [(set (match_operand:V2SF 0 "fr_register_operand" "")
 	(if_then_else:V2SF
 	  (match_operator 3 "" 
@@ -1396,10 +1273,10 @@
 
   cmp = gen_reg_rtx (V2SFmode);
   PUT_MODE (operands[3], V2SFmode);
-  emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3]));
+  emit_insn (gen_rtx_SET (cmp, operands[3]));
 
   x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  emit_insn (gen_rtx_SET (operands[0], x));
   DONE;
 })
 
@@ -1422,7 +1299,7 @@
   "fselect %0 = %F2, %F3, %1"
   [(set_attr "itanium_class" "fmisc")])
 
-(define_expand "vec_initv2sf"
+(define_expand "vec_initv2sfsf"
   [(match_operand:V2SF 0 "fr_register_operand" "")
    (match_operand 1 "" "")]
   ""
@@ -1479,7 +1356,7 @@
 }
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "vec_interleave_highv2sf"
+(define_insn "*vec_interleave_highv2sf"
   [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
 	(vec_select:V2SF
 	  (vec_concat:V4SF
@@ -1496,7 +1373,7 @@
 }
   [(set_attr "itanium_class" "fmisc")])
 
-(define_insn "vec_interleave_lowv2sf"
+(define_insn "*vec_interleave_lowv2sf"
   [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
 	(vec_select:V2SF
 	  (vec_concat:V4SF
@@ -1530,58 +1407,13 @@
 }
   [(set_attr "itanium_class" "fmisc")])
 
-(define_expand "vec_extract_evenv2sf"
-  [(match_operand:V2SF 0 "gr_register_operand" "")
-   (match_operand:V2SF 1 "gr_register_operand" "")
-   (match_operand:V2SF 2 "gr_register_operand" "")]
-  ""
-{
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
-					    operands[2]));
-  else
-    emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
-					   operands[2]));
-  DONE;
-})
-
-(define_expand "vec_extract_oddv2sf"
-  [(match_operand:V2SF 0 "gr_register_operand" "")
-   (match_operand:V2SF 1 "gr_register_operand" "")
-   (match_operand:V2SF 2 "gr_register_operand" "")]
-  ""
-{
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
-					   operands[2]));
-  else
-    emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
-					    operands[2]));
-  DONE;
-})
-
 (define_expand "vec_setv2sf"
   [(match_operand:V2SF 0 "fr_register_operand" "")
    (match_operand:SF 1 "fr_register_operand" "")
    (match_operand 2 "const_int_operand" "")]
   ""
 {
-  rtx op0 = operands[0];
-  rtx tmp = gen_reg_rtx (V2SFmode);
-
-  emit_insn (gen_fpack (tmp, operands[1], CONST0_RTX (SFmode)));
-
-  switch (INTVAL (operands[2]))
-    {
-    case 0:
-      emit_insn (gen_fmix_lr (op0, tmp, op0));
-      break;
-    case 1:
-      emit_insn (gen_vec_interleave_lowv2sf (op0, op0, tmp));
-      break;
-    default:
-      gcc_unreachable ();
-    }
+  ia64_expand_vec_setv2sf (operands);
   DONE;
 })
 
@@ -1651,7 +1483,7 @@
   operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
 })
 
-(define_expand "vec_extractv2sf"
+(define_expand "vec_extractv2sfsf"
   [(set (match_operand:SF 0 "register_operand" "")
 	(unspec:SF [(match_operand:V2SF 1 "register_operand" "")
 		    (match_operand:DI 2 "const_int_operand" "")]
@@ -1703,10 +1535,7 @@
 {
   rtx op1 = gen_lowpart (V8QImode, operands[1]);
   rtx op2 = gen_lowpart (V8QImode, operands[2]);
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_extract_oddv8qi (operands[0], op1, op2));
-  else
-    emit_insn (gen_vec_extract_evenv8qi (operands[0], op1, op2));
+  ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
   DONE;
 })
 
@@ -1718,11 +1547,21 @@
 {
   rtx op1 = gen_lowpart (V4HImode, operands[1]);
   rtx op2 = gen_lowpart (V4HImode, operands[2]);
-  if (TARGET_BIG_ENDIAN)
-    emit_insn (gen_vec_extract_oddv4hi (operands[0], op1, op2));
+  ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
+  DONE;
+})
+
+(define_expand "vec_perm_const<mode>"
+  [(match_operand:VEC 0 "register_operand" "")
+   (match_operand:VEC 1 "register_operand" "")
+   (match_operand:VEC 2 "register_operand" "")
+   (match_operand:<vecint> 3 "" "")]
+  ""
+{
+  if (ia64_expand_vec_perm_const (operands))
+    DONE;
   else
-    emit_insn (gen_vec_extract_evenv4hi (operands[0], op1, op2));
-  DONE;
+    FAIL;
 })
 
 ;; Missing operations