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comparison gcc/config/mips/10000.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; DFA-based pipeline description for the VR1x000. 1 ;; DFA-based pipeline description for the VR1x000.
2 ;; Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc. 2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 5
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published 7 ;; under the terms of the GNU General Public License as published
66 66
67 ;; Integer add/sub + logic ops, and mt hi/lo can be done by alu1 or alu2. 67 ;; Integer add/sub + logic ops, and mt hi/lo can be done by alu1 or alu2.
68 ;; Miscellaneous arith goes here too (this is a guess). 68 ;; Miscellaneous arith goes here too (this is a guess).
69 (define_insn_reservation "r10k_arith" 1 69 (define_insn_reservation "r10k_arith" 1
70 (and (eq_attr "cpu" "r10000") 70 (and (eq_attr "cpu" "r10000")
71 (eq_attr "type" "arith,mthilo,slt,clz,const,nop,trap,logical")) 71 (eq_attr "type" "arith,mthi,mtlo,slt,clz,const,nop,trap,logical"))
72 "r10k_alu1 | r10k_alu2") 72 "r10k_alu1 | r10k_alu2")
73 73
74 ;; We treat mfhilo differently, because we need to know when 74 ;; We treat mfhilo differently, because we need to know when
75 ;; it's HI and when it's LO. 75 ;; it's HI and when it's LO.
76 (define_insn_reservation "r10k_mfhi" 1 76 (define_insn_reservation "r10k_mfhi" 1
77 (and (eq_attr "cpu" "r10000") 77 (and (eq_attr "cpu" "r10000")
78 (and (eq_attr "type" "mfhilo") 78 (eq_attr "type" "mfhi"))
79 (not (match_operand 1 "lo_operand"))))
80 "r10k_alu1 | r10k_alu2") 79 "r10k_alu1 | r10k_alu2")
81 80
82 (define_insn_reservation "r10k_mflo" 1 81 (define_insn_reservation "r10k_mflo" 1
83 (and (eq_attr "cpu" "r10000") 82 (and (eq_attr "cpu" "r10000")
84 (and (eq_attr "type" "mfhilo") 83 (eq_attr "type" "mflo"))
85 (match_operand 1 "lo_operand")))
86 "r10k_alu1 | r10k_alu2") 84 "r10k_alu1 | r10k_alu2")
87 85
88 86
89 ;; ALU1 handles shifts, branch eval, and condmove. 87 ;; ALU1 handles shifts, branch eval, and condmove.
90 ;; 88 ;;
247 245
248 246
249 ;; Handle unknown/multi insns here (this is a guess). 247 ;; Handle unknown/multi insns here (this is a guess).
250 (define_insn_reservation "r10k_unknown" 1 248 (define_insn_reservation "r10k_unknown" 1
251 (and (eq_attr "cpu" "r10000") 249 (and (eq_attr "cpu" "r10000")
252 (eq_attr "type" "unknown,multi")) 250 (eq_attr "type" "unknown,multi,atomic,syncloop"))
253 "r10k_alu1 + r10k_alu2") 251 "r10k_alu1 + r10k_alu2")