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comparison gcc/config/mips/mips-fixed.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Copyright (C) 2007 Free Software Foundation, Inc. 1 ;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify 5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by 6 ;; it under the terms of the GNU General Public License as published by
50 "<d>addu\t%0,%1,%2" 50 "<d>addu\t%0,%1,%2"
51 [(set_attr "type" "arith") 51 [(set_attr "type" "arith")
52 (set_attr "mode" "<IMODE>")]) 52 (set_attr "mode" "<IMODE>")])
53 53
54 (define_insn "usadd<mode>3" 54 (define_insn "usadd<mode>3"
55 [(parallel 55 [(set (match_operand:UADDSUB 0 "register_operand" "=d")
56 [(set (match_operand:UADDSUB 0 "register_operand" "=d") 56 (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
57 (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") 57 (match_operand:UADDSUB 2 "register_operand" "d")))
58 (match_operand:UADDSUB 2 "register_operand" "d"))) 58 (set (reg:CCDSP CCDSP_OU_REGNUM)
59 (set (reg:CCDSP CCDSP_OU_REGNUM) 59 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
60 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
61 "" 60 ""
62 "addu_s.<uaddsubfmt>\t%0,%1,%2" 61 "addu_s.<uaddsubfmt>\t%0,%1,%2"
63 [(set_attr "type" "arith") 62 [(set_attr "type" "arith")
64 (set_attr "mode" "<IMODE>")]) 63 (set_attr "mode" "<IMODE>")])
65 64
66 (define_insn "ssadd<mode>3" 65 (define_insn "ssadd<mode>3"
67 [(parallel 66 [(set (match_operand:ADDSUB 0 "register_operand" "=d")
68 [(set (match_operand:ADDSUB 0 "register_operand" "=d") 67 (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
69 (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") 68 (match_operand:ADDSUB 2 "register_operand" "d")))
70 (match_operand:ADDSUB 2 "register_operand" "d"))) 69 (set (reg:CCDSP CCDSP_OU_REGNUM)
71 (set (reg:CCDSP CCDSP_OU_REGNUM) 70 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
72 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
73 "ISA_HAS_DSP" 71 "ISA_HAS_DSP"
74 "addq_s.<addsubfmt>\t%0,%1,%2" 72 "addq_s.<addsubfmt>\t%0,%1,%2"
75 [(set_attr "type" "arith") 73 [(set_attr "type" "arith")
76 (set_attr "mode" "<IMODE>")]) 74 (set_attr "mode" "<IMODE>")])
77 75
83 "<d>subu\t%0,%1,%2" 81 "<d>subu\t%0,%1,%2"
84 [(set_attr "type" "arith") 82 [(set_attr "type" "arith")
85 (set_attr "mode" "<IMODE>")]) 83 (set_attr "mode" "<IMODE>")])
86 84
87 (define_insn "ussub<mode>3" 85 (define_insn "ussub<mode>3"
88 [(parallel 86 [(set (match_operand:UADDSUB 0 "register_operand" "=d")
89 [(set (match_operand:UADDSUB 0 "register_operand" "=d") 87 (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
90 (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") 88 (match_operand:UADDSUB 2 "register_operand" "d")))
91 (match_operand:UADDSUB 2 "register_operand" "d"))) 89 (set (reg:CCDSP CCDSP_OU_REGNUM)
92 (set (reg:CCDSP CCDSP_OU_REGNUM) 90 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
93 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
94 "" 91 ""
95 "subu_s.<uaddsubfmt>\t%0,%1,%2" 92 "subu_s.<uaddsubfmt>\t%0,%1,%2"
96 [(set_attr "type" "arith") 93 [(set_attr "type" "arith")
97 (set_attr "mode" "<IMODE>")]) 94 (set_attr "mode" "<IMODE>")])
98 95
99 (define_insn "sssub<mode>3" 96 (define_insn "sssub<mode>3"
100 [(parallel 97 [(set (match_operand:ADDSUB 0 "register_operand" "=d")
101 [(set (match_operand:ADDSUB 0 "register_operand" "=d") 98 (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
102 (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") 99 (match_operand:ADDSUB 2 "register_operand" "d")))
103 (match_operand:ADDSUB 2 "register_operand" "d"))) 100 (set (reg:CCDSP CCDSP_OU_REGNUM)
104 (set (reg:CCDSP CCDSP_OU_REGNUM) 101 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
105 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
106 "ISA_HAS_DSP" 102 "ISA_HAS_DSP"
107 "subq_s.<addsubfmt>\t%0,%1,%2" 103 "subq_s.<addsubfmt>\t%0,%1,%2"
108 [(set_attr "type" "arith") 104 [(set_attr "type" "arith")
109 (set_attr "mode" "<IMODE>")]) 105 (set_attr "mode" "<IMODE>")])
110 106
111 (define_insn "ssmul<mode>3" 107 (define_insn "ssmul<mode>3"
112 [(parallel 108 [(set (match_operand:MULQ 0 "register_operand" "=d")
113 [(set (match_operand:MULQ 0 "register_operand" "=d") 109 (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
114 (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") 110 (match_operand:MULQ 2 "register_operand" "d")))
115 (match_operand:MULQ 2 "register_operand" "d"))) 111 (set (reg:CCDSP CCDSP_OU_REGNUM)
116 (set (reg:CCDSP CCDSP_OU_REGNUM) 112 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
117 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 113 (clobber (match_scratch:DI 3 "=x"))]
118 (clobber (match_scratch:DI 3 "=x"))])]
119 "" 114 ""
120 "mulq_rs.<mulqfmt>\t%0,%1,%2" 115 "mulq_rs.<mulqfmt>\t%0,%1,%2"
121 [(set_attr "type" "imul3") 116 [(set_attr "type" "imul3")
122 (set_attr "mode" "<IMODE>")]) 117 (set_attr "mode" "<IMODE>")])
123 118
124 (define_insn "ssmaddsqdq4" 119 (define_insn "ssmaddsqdq4"
125 [(parallel 120 [(set (match_operand:DQ 0 "register_operand" "=a")
126 [(set (match_operand:DQ 0 "register_operand" "=a") 121 (ss_plus:DQ
127 (ss_plus:DQ 122 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
128 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 123 "register_operand" "d"))
129 "register_operand" "d")) 124 (sat_fract:DQ (match_operand:SQ 2
130 (sat_fract:DQ (match_operand:SQ 2 125 "register_operand" "d")))
131 "register_operand" "d"))) 126 (match_operand:DQ 3 "register_operand" "0")))
132 (match_operand:DQ 3 "register_operand" "0"))) 127 (set (reg:CCDSP CCDSP_OU_REGNUM)
133 (set (reg:CCDSP CCDSP_OU_REGNUM) 128 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
134 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 129 UNSPEC_DPAQ_SA_L_W))]
135 UNSPEC_DPAQ_SA_L_W))])]
136 "ISA_HAS_DSP && !TARGET_64BIT" 130 "ISA_HAS_DSP && !TARGET_64BIT"
137 "dpaq_sa.l.w\t%q0,%1,%2" 131 "dpaq_sa.l.w\t%q0,%1,%2"
138 [(set_attr "type" "imadd") 132 [(set_attr "type" "imadd")
139 (set_attr "mode" "SI")]) 133 (set_attr "mode" "SI")])
140 134
141 (define_insn "ssmsubsqdq4" 135 (define_insn "ssmsubsqdq4"
142 [(parallel 136 [(set (match_operand:DQ 0 "register_operand" "=a")
143 [(set (match_operand:DQ 0 "register_operand" "=a") 137 (ss_minus:DQ
144 (ss_minus:DQ 138 (match_operand:DQ 3 "register_operand" "0")
145 (match_operand:DQ 3 "register_operand" "0") 139 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
146 (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 140 "register_operand" "d"))
147 "register_operand" "d")) 141 (sat_fract:DQ (match_operand:SQ 2
148 (sat_fract:DQ (match_operand:SQ 2 142 "register_operand" "d")))))
149 "register_operand" "d"))))) 143 (set (reg:CCDSP CCDSP_OU_REGNUM)
150 (set (reg:CCDSP CCDSP_OU_REGNUM) 144 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
151 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 145 UNSPEC_DPSQ_SA_L_W))]
152 UNSPEC_DPSQ_SA_L_W))])]
153 "ISA_HAS_DSP && !TARGET_64BIT" 146 "ISA_HAS_DSP && !TARGET_64BIT"
154 "dpsq_sa.l.w\t%q0,%1,%2" 147 "dpsq_sa.l.w\t%q0,%1,%2"
155 [(set_attr "type" "imadd") 148 [(set_attr "type" "imadd")
156 (set_attr "mode" "SI")]) 149 (set_attr "mode" "SI")])