Mercurial > hg > CbC > CbC_gcc
diff gcc/config/mips/mips-fixed.md @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | 77e2b8dfacca |
| children | 84e7813d76e9 |
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--- a/gcc/config/mips/mips-fixed.md Sun Aug 21 07:07:55 2011 +0900 +++ b/gcc/config/mips/mips-fixed.md Fri Oct 27 22:46:09 2017 +0900 @@ -1,4 +1,4 @@ -;; Copyright (C) 2007 Free Software Foundation, Inc. +;; Copyright (C) 2007-2017 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -52,24 +52,22 @@ (set_attr "mode" "<IMODE>")]) (define_insn "usadd<mode>3" - [(parallel - [(set (match_operand:UADDSUB 0 "register_operand" "=d") - (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") - (match_operand:UADDSUB 2 "register_operand" "d"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] + [(set (match_operand:UADDSUB 0 "register_operand" "=d") + (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") + (match_operand:UADDSUB 2 "register_operand" "d"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))] "" "addu_s.<uaddsubfmt>\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "<IMODE>")]) (define_insn "ssadd<mode>3" - [(parallel - [(set (match_operand:ADDSUB 0 "register_operand" "=d") - (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") - (match_operand:ADDSUB 2 "register_operand" "d"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] + [(set (match_operand:ADDSUB 0 "register_operand" "=d") + (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") + (match_operand:ADDSUB 2 "register_operand" "d"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))] "ISA_HAS_DSP" "addq_s.<addsubfmt>\t%0,%1,%2" [(set_attr "type" "arith") @@ -85,71 +83,66 @@ (set_attr "mode" "<IMODE>")]) (define_insn "ussub<mode>3" - [(parallel - [(set (match_operand:UADDSUB 0 "register_operand" "=d") - (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") - (match_operand:UADDSUB 2 "register_operand" "d"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] + [(set (match_operand:UADDSUB 0 "register_operand" "=d") + (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d") + (match_operand:UADDSUB 2 "register_operand" "d"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))] "" "subu_s.<uaddsubfmt>\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "<IMODE>")]) (define_insn "sssub<mode>3" - [(parallel - [(set (match_operand:ADDSUB 0 "register_operand" "=d") - (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") - (match_operand:ADDSUB 2 "register_operand" "d"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] + [(set (match_operand:ADDSUB 0 "register_operand" "=d") + (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d") + (match_operand:ADDSUB 2 "register_operand" "d"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))] "ISA_HAS_DSP" "subq_s.<addsubfmt>\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "<IMODE>")]) (define_insn "ssmul<mode>3" - [(parallel - [(set (match_operand:MULQ 0 "register_operand" "=d") - (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") - (match_operand:MULQ 2 "register_operand" "d"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) - (clobber (match_scratch:DI 3 "=x"))])] + [(set (match_operand:MULQ 0 "register_operand" "=d") + (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d") + (match_operand:MULQ 2 "register_operand" "d"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) + (clobber (match_scratch:DI 3 "=x"))] "" "mulq_rs.<mulqfmt>\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "<IMODE>")]) (define_insn "ssmaddsqdq4" - [(parallel - [(set (match_operand:DQ 0 "register_operand" "=a") - (ss_plus:DQ - (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 - "register_operand" "d")) - (sat_fract:DQ (match_operand:SQ 2 - "register_operand" "d"))) - (match_operand:DQ 3 "register_operand" "0"))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] - UNSPEC_DPAQ_SA_L_W))])] + [(set (match_operand:DQ 0 "register_operand" "=a") + (ss_plus:DQ + (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 + "register_operand" "d")) + (sat_fract:DQ (match_operand:SQ 2 + "register_operand" "d"))) + (match_operand:DQ 3 "register_operand" "0"))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] + UNSPEC_DPAQ_SA_L_W))] "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_sa.l.w\t%q0,%1,%2" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) (define_insn "ssmsubsqdq4" - [(parallel - [(set (match_operand:DQ 0 "register_operand" "=a") - (ss_minus:DQ - (match_operand:DQ 3 "register_operand" "0") - (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 - "register_operand" "d")) - (sat_fract:DQ (match_operand:SQ 2 - "register_operand" "d"))))) - (set (reg:CCDSP CCDSP_OU_REGNUM) - (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] - UNSPEC_DPSQ_SA_L_W))])] + [(set (match_operand:DQ 0 "register_operand" "=a") + (ss_minus:DQ + (match_operand:DQ 3 "register_operand" "0") + (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1 + "register_operand" "d")) + (sat_fract:DQ (match_operand:SQ 2 + "register_operand" "d"))))) + (set (reg:CCDSP CCDSP_OU_REGNUM) + (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] + UNSPEC_DPSQ_SA_L_W))] "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_sa.l.w\t%q0,%1,%2" [(set_attr "type" "imadd")