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comparison gcc/config/powerpcspe/7450.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling description for Motorola PowerPC 7450 processor.
2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
10
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
15
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 (define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
21 (define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
22 (define_cpu_unit "mciu_7450" "ppc7450mciu")
23 (define_cpu_unit "fpu_7450" "ppc7450fp")
24 (define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
25 (define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
26 (define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
27 (define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
28
29
30 ;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
31 ;; IU1,IU2,IU3 can perform all integer operations
32 ;; MCIU performs imul and idiv, cr logical, SPR moves
33 ;; LSU 2 stage pipelined
34 ;; FPU 3 stage pipelined
35 ;; It also has 4 vector units, one for each type of vector instruction.
36 ;; However, we can only dispatch 2 instructions per cycle.
37 ;; Max issue 3 insns/clock cycle (includes 1 branch)
38 ;; In-order execution
39
40 ;; Branches go straight to the BPU. All other insns are handled
41 ;; by a dispatch unit which can issue a max of 3 insns per cycle.
42 (define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
43 (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
44
45 (define_insn_reservation "ppc7450-load" 3
46 (and (eq_attr "type" "load,vecload")
47 (eq_attr "cpu" "ppc7450"))
48 "ppc7450_du,lsu_7450")
49
50 (define_insn_reservation "ppc7450-store" 3
51 (and (eq_attr "type" "store,vecstore")
52 (eq_attr "cpu" "ppc7450"))
53 "ppc7450_du,lsu_7450")
54
55 (define_insn_reservation "ppc7450-fpload" 4
56 (and (eq_attr "type" "fpload")
57 (eq_attr "cpu" "ppc7450"))
58 "ppc7450_du,lsu_7450")
59
60 (define_insn_reservation "ppc7450-fpstore" 3
61 (and (eq_attr "type" "fpstore")
62 (eq_attr "cpu" "ppc7450"))
63 "ppc7450_du,lsu_7450*3")
64
65 (define_insn_reservation "ppc7450-llsc" 3
66 (and (eq_attr "type" "load_l,store_c")
67 (eq_attr "cpu" "ppc7450"))
68 "ppc7450_du,lsu_7450")
69
70 (define_insn_reservation "ppc7450-sync" 35
71 (and (eq_attr "type" "sync")
72 (eq_attr "cpu" "ppc7450"))
73 "ppc7450_du,lsu_7450")
74
75 (define_insn_reservation "ppc7450-integer" 1
76 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
77 (and (eq_attr "type" "add,logical,shift,exts")
78 (eq_attr "dot" "no")))
79 (eq_attr "cpu" "ppc7450"))
80 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
81
82 (define_insn_reservation "ppc7450-two" 1
83 (and (eq_attr "type" "two")
84 (eq_attr "cpu" "ppc7450"))
85 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
86
87 (define_insn_reservation "ppc7450-three" 1
88 (and (eq_attr "type" "three")
89 (eq_attr "cpu" "ppc7450"))
90 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
91 iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
92
93 (define_insn_reservation "ppc7450-imul" 4
94 (and (eq_attr "type" "mul")
95 (eq_attr "size" "32")
96 (eq_attr "cpu" "ppc7450"))
97 "ppc7450_du,mciu_7450*2")
98
99 (define_insn_reservation "ppc7450-imul2" 3
100 (and (eq_attr "type" "mul")
101 (eq_attr "size" "8,16")
102 (eq_attr "cpu" "ppc7450"))
103 "ppc7450_du,mciu_7450")
104
105 (define_insn_reservation "ppc7450-idiv" 23
106 (and (eq_attr "type" "div")
107 (eq_attr "cpu" "ppc7450"))
108 "ppc7450_du,mciu_7450*23")
109
110 (define_insn_reservation "ppc7450-compare" 2
111 (and (ior (eq_attr "type" "cmp")
112 (and (eq_attr "type" "add,logical,shift,exts")
113 (eq_attr "dot" "yes")))
114 (eq_attr "cpu" "ppc7450"))
115 "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
116
117 (define_insn_reservation "ppc7450-fpcompare" 5
118 (and (eq_attr "type" "fpcompare")
119 (eq_attr "cpu" "ppc7450"))
120 "ppc7450_du,fpu_7450")
121
122 (define_insn_reservation "ppc7450-fp" 5
123 (and (eq_attr "type" "fp,fpsimple,dmul")
124 (eq_attr "cpu" "ppc7450"))
125 "ppc7450_du,fpu_7450")
126
127 ; Divides are not pipelined
128 (define_insn_reservation "ppc7450-sdiv" 21
129 (and (eq_attr "type" "sdiv")
130 (eq_attr "cpu" "ppc7450"))
131 "ppc7450_du,fpu_7450*21")
132
133 (define_insn_reservation "ppc7450-ddiv" 35
134 (and (eq_attr "type" "ddiv")
135 (eq_attr "cpu" "ppc7450"))
136 "ppc7450_du,fpu_7450*35")
137
138 (define_insn_reservation "ppc7450-mfcr" 2
139 (and (eq_attr "type" "mfcr,mtcr")
140 (eq_attr "cpu" "ppc7450"))
141 "ppc7450_du,mciu_7450")
142
143 (define_insn_reservation "ppc7450-crlogical" 1
144 (and (eq_attr "type" "cr_logical,delayed_cr")
145 (eq_attr "cpu" "ppc7450"))
146 "ppc7450_du,mciu_7450")
147
148 (define_insn_reservation "ppc7450-mtjmpr" 2
149 (and (eq_attr "type" "mtjmpr")
150 (eq_attr "cpu" "ppc7450"))
151 "nothing,mciu_7450*2")
152
153 (define_insn_reservation "ppc7450-mfjmpr" 3
154 (and (eq_attr "type" "mfjmpr")
155 (eq_attr "cpu" "ppc7450"))
156 "nothing,mciu_7450*2")
157
158 (define_insn_reservation "ppc7450-jmpreg" 1
159 (and (eq_attr "type" "jmpreg,branch,isync")
160 (eq_attr "cpu" "ppc7450"))
161 "nothing,bpu_7450")
162
163 ;; Altivec
164 (define_insn_reservation "ppc7450-vecsimple" 1
165 (and (eq_attr "type" "vecsimple,veclogical,vecmove")
166 (eq_attr "cpu" "ppc7450"))
167 "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
168
169 (define_insn_reservation "ppc7450-veccomplex" 4
170 (and (eq_attr "type" "veccomplex")
171 (eq_attr "cpu" "ppc7450"))
172 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
173
174 (define_insn_reservation "ppc7450-veccmp" 2
175 (and (eq_attr "type" "veccmp,veccmpfx")
176 (eq_attr "cpu" "ppc7450"))
177 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
178
179 (define_insn_reservation "ppc7450-vecfloat" 4
180 (and (eq_attr "type" "vecfloat")
181 (eq_attr "cpu" "ppc7450"))
182 "ppc7450_du,ppc7450_vec_du,vecflt_7450")
183
184 (define_insn_reservation "ppc7450-vecperm" 2
185 (and (eq_attr "type" "vecperm")
186 (eq_attr "cpu" "ppc7450"))
187 "ppc7450_du,ppc7450_vec_du,vecperm_7450")
188