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1 ;; Scheduling description for Motorola PowerPC 7450 processor.
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2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
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21 (define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
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22 (define_cpu_unit "mciu_7450" "ppc7450mciu")
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23 (define_cpu_unit "fpu_7450" "ppc7450fp")
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24 (define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
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25 (define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
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26 (define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
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27 (define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
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28
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29
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30 ;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
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31 ;; IU1,IU2,IU3 can perform all integer operations
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32 ;; MCIU performs imul and idiv, cr logical, SPR moves
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33 ;; LSU 2 stage pipelined
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34 ;; FPU 3 stage pipelined
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35 ;; It also has 4 vector units, one for each type of vector instruction.
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36 ;; However, we can only dispatch 2 instructions per cycle.
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37 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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38 ;; In-order execution
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39
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40 ;; Branches go straight to the BPU. All other insns are handled
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41 ;; by a dispatch unit which can issue a max of 3 insns per cycle.
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42 (define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
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43 (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
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44
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45 (define_insn_reservation "ppc7450-load" 3
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46 (and (eq_attr "type" "load,vecload")
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47 (eq_attr "cpu" "ppc7450"))
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48 "ppc7450_du,lsu_7450")
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49
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50 (define_insn_reservation "ppc7450-store" 3
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51 (and (eq_attr "type" "store,vecstore")
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52 (eq_attr "cpu" "ppc7450"))
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53 "ppc7450_du,lsu_7450")
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54
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55 (define_insn_reservation "ppc7450-fpload" 4
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56 (and (eq_attr "type" "fpload")
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57 (eq_attr "cpu" "ppc7450"))
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58 "ppc7450_du,lsu_7450")
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59
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60 (define_insn_reservation "ppc7450-fpstore" 3
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61 (and (eq_attr "type" "fpstore")
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62 (eq_attr "cpu" "ppc7450"))
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63 "ppc7450_du,lsu_7450*3")
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64
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65 (define_insn_reservation "ppc7450-llsc" 3
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66 (and (eq_attr "type" "load_l,store_c")
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67 (eq_attr "cpu" "ppc7450"))
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68 "ppc7450_du,lsu_7450")
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69
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70 (define_insn_reservation "ppc7450-sync" 35
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71 (and (eq_attr "type" "sync")
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72 (eq_attr "cpu" "ppc7450"))
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73 "ppc7450_du,lsu_7450")
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74
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75 (define_insn_reservation "ppc7450-integer" 1
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76 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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77 (and (eq_attr "type" "add,logical,shift,exts")
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78 (eq_attr "dot" "no")))
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79 (eq_attr "cpu" "ppc7450"))
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80 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
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81
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82 (define_insn_reservation "ppc7450-two" 1
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83 (and (eq_attr "type" "two")
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84 (eq_attr "cpu" "ppc7450"))
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85 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
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86
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87 (define_insn_reservation "ppc7450-three" 1
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88 (and (eq_attr "type" "three")
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89 (eq_attr "cpu" "ppc7450"))
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90 "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
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91 iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
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92
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93 (define_insn_reservation "ppc7450-imul" 4
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94 (and (eq_attr "type" "mul")
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95 (eq_attr "size" "32")
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96 (eq_attr "cpu" "ppc7450"))
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97 "ppc7450_du,mciu_7450*2")
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98
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99 (define_insn_reservation "ppc7450-imul2" 3
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100 (and (eq_attr "type" "mul")
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101 (eq_attr "size" "8,16")
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102 (eq_attr "cpu" "ppc7450"))
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103 "ppc7450_du,mciu_7450")
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104
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105 (define_insn_reservation "ppc7450-idiv" 23
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106 (and (eq_attr "type" "div")
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107 (eq_attr "cpu" "ppc7450"))
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108 "ppc7450_du,mciu_7450*23")
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109
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110 (define_insn_reservation "ppc7450-compare" 2
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111 (and (ior (eq_attr "type" "cmp")
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112 (and (eq_attr "type" "add,logical,shift,exts")
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113 (eq_attr "dot" "yes")))
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114 (eq_attr "cpu" "ppc7450"))
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115 "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
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116
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117 (define_insn_reservation "ppc7450-fpcompare" 5
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118 (and (eq_attr "type" "fpcompare")
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119 (eq_attr "cpu" "ppc7450"))
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120 "ppc7450_du,fpu_7450")
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121
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122 (define_insn_reservation "ppc7450-fp" 5
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123 (and (eq_attr "type" "fp,fpsimple,dmul")
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124 (eq_attr "cpu" "ppc7450"))
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125 "ppc7450_du,fpu_7450")
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126
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127 ; Divides are not pipelined
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128 (define_insn_reservation "ppc7450-sdiv" 21
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129 (and (eq_attr "type" "sdiv")
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130 (eq_attr "cpu" "ppc7450"))
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131 "ppc7450_du,fpu_7450*21")
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132
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133 (define_insn_reservation "ppc7450-ddiv" 35
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134 (and (eq_attr "type" "ddiv")
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135 (eq_attr "cpu" "ppc7450"))
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136 "ppc7450_du,fpu_7450*35")
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137
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138 (define_insn_reservation "ppc7450-mfcr" 2
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139 (and (eq_attr "type" "mfcr,mtcr")
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140 (eq_attr "cpu" "ppc7450"))
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141 "ppc7450_du,mciu_7450")
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142
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143 (define_insn_reservation "ppc7450-crlogical" 1
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144 (and (eq_attr "type" "cr_logical,delayed_cr")
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145 (eq_attr "cpu" "ppc7450"))
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146 "ppc7450_du,mciu_7450")
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147
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148 (define_insn_reservation "ppc7450-mtjmpr" 2
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149 (and (eq_attr "type" "mtjmpr")
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150 (eq_attr "cpu" "ppc7450"))
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151 "nothing,mciu_7450*2")
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152
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153 (define_insn_reservation "ppc7450-mfjmpr" 3
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154 (and (eq_attr "type" "mfjmpr")
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155 (eq_attr "cpu" "ppc7450"))
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156 "nothing,mciu_7450*2")
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157
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158 (define_insn_reservation "ppc7450-jmpreg" 1
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159 (and (eq_attr "type" "jmpreg,branch,isync")
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160 (eq_attr "cpu" "ppc7450"))
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161 "nothing,bpu_7450")
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162
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163 ;; Altivec
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164 (define_insn_reservation "ppc7450-vecsimple" 1
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165 (and (eq_attr "type" "vecsimple,veclogical,vecmove")
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166 (eq_attr "cpu" "ppc7450"))
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167 "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
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168
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169 (define_insn_reservation "ppc7450-veccomplex" 4
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170 (and (eq_attr "type" "veccomplex")
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171 (eq_attr "cpu" "ppc7450"))
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172 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
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173
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174 (define_insn_reservation "ppc7450-veccmp" 2
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175 (and (eq_attr "type" "veccmp,veccmpfx")
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176 (eq_attr "cpu" "ppc7450"))
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177 "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
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178
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179 (define_insn_reservation "ppc7450-vecfloat" 4
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180 (and (eq_attr "type" "vecfloat")
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181 (eq_attr "cpu" "ppc7450"))
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182 "ppc7450_du,ppc7450_vec_du,vecflt_7450")
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183
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184 (define_insn_reservation "ppc7450-vecperm" 2
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185 (and (eq_attr "type" "vecperm")
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186 (eq_attr "cpu" "ppc7450"))
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187 "ppc7450_du,ppc7450_vec_du,vecperm_7450")
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188
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