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comparison gcc/config/riscv/riscv.opt @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 ; Options for the RISC-V port of the compiler
2 ;
3 ; Copyright (C) 2011-2017 Free Software Foundation, Inc.
4 ;
5 ; This file is part of GCC.
6 ;
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
10 ; version.
11 ;
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ; License for more details.
16 ;
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
20
21 HeaderInclude
22 config/riscv/riscv-opts.h
23
24 mbranch-cost=
25 Target RejectNegative Joined UInteger Var(riscv_branch_cost)
26 -mbranch-cost=N Set the cost of branches to roughly N instructions.
27
28 mplt
29 Target Report Var(TARGET_PLT) Init(1)
30 When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
31
32 mabi=
33 Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
34 Specify integer and floating-point calling convention.
35
36 Enum
37 Name(abi_type) Type(enum riscv_abi_type)
38 Supported ABIs (for use with the -mabi= option):
39
40 EnumValue
41 Enum(abi_type) String(ilp32) Value(ABI_ILP32)
42
43 EnumValue
44 Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)
45
46 EnumValue
47 Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)
48
49 EnumValue
50 Enum(abi_type) String(lp64) Value(ABI_LP64)
51
52 EnumValue
53 Enum(abi_type) String(lp64f) Value(ABI_LP64F)
54
55 EnumValue
56 Enum(abi_type) String(lp64d) Value(ABI_LP64D)
57
58 mfdiv
59 Target Report Mask(FDIV)
60 Use hardware floating-point divide and square root instructions.
61
62 mdiv
63 Target Report Mask(DIV)
64 Use hardware instructions for integer division.
65
66 march=
67 Target Report RejectNegative Joined
68 -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
69 lower-case.
70
71 mtune=
72 Target RejectNegative Joined Var(riscv_tune_string)
73 -mtune=PROCESSOR Optimize the output for PROCESSOR.
74
75 msmall-data-limit=
76 Target Joined Separate UInteger Var(g_switch_value) Init(8)
77 -msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
78
79 msave-restore
80 Target Report Mask(SAVE_RESTORE)
81 Use smaller but slower prologue and epilogue code.
82
83 mcmodel=
84 Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
85 Specify the code model.
86
87 mstrict-align
88 Target Report Mask(STRICT_ALIGN) Save
89 Do not generate unaligned memory accesses.
90
91 Enum
92 Name(code_model) Type(enum riscv_code_model)
93 Known code models (for use with the -mcmodel= option):
94
95 EnumValue
96 Enum(code_model) String(medlow) Value(CM_MEDLOW)
97
98 EnumValue
99 Enum(code_model) String(medany) Value(CM_MEDANY)
100
101 mexplicit-relocs
102 Target Report Mask(EXPLICIT_RELOCS)
103 Use %reloc() operators, rather than assembly macros, to load addresses.
104
105 Mask(64BIT)
106
107 Mask(MUL)
108
109 Mask(ATOMIC)
110
111 Mask(HARD_FLOAT)
112
113 Mask(DOUBLE_FLOAT)
114
115 Mask(RVC)