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1 ; Options for the RISC-V port of the compiler
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2 ;
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3 ; Copyright (C) 2011-2017 Free Software Foundation, Inc.
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4 ;
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5 ; This file is part of GCC.
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6 ;
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7 ; GCC is free software; you can redistribute it and/or modify it under
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8 ; the terms of the GNU General Public License as published by the Free
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9 ; Software Foundation; either version 3, or (at your option) any later
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10 ; version.
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11 ;
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12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ; License for more details.
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16 ;
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17 ; You should have received a copy of the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
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19 ; <http://www.gnu.org/licenses/>.
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20
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21 HeaderInclude
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22 config/riscv/riscv-opts.h
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23
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24 mbranch-cost=
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25 Target RejectNegative Joined UInteger Var(riscv_branch_cost)
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26 -mbranch-cost=N Set the cost of branches to roughly N instructions.
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27
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28 mplt
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29 Target Report Var(TARGET_PLT) Init(1)
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30 When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
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31
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32 mabi=
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33 Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
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34 Specify integer and floating-point calling convention.
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35
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36 Enum
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37 Name(abi_type) Type(enum riscv_abi_type)
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38 Supported ABIs (for use with the -mabi= option):
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39
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40 EnumValue
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41 Enum(abi_type) String(ilp32) Value(ABI_ILP32)
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42
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43 EnumValue
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44 Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)
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45
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46 EnumValue
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47 Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)
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48
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49 EnumValue
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50 Enum(abi_type) String(lp64) Value(ABI_LP64)
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51
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52 EnumValue
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53 Enum(abi_type) String(lp64f) Value(ABI_LP64F)
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54
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55 EnumValue
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56 Enum(abi_type) String(lp64d) Value(ABI_LP64D)
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57
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58 mfdiv
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59 Target Report Mask(FDIV)
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60 Use hardware floating-point divide and square root instructions.
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61
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62 mdiv
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63 Target Report Mask(DIV)
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64 Use hardware instructions for integer division.
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65
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66 march=
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67 Target Report RejectNegative Joined
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68 -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
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69 lower-case.
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70
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71 mtune=
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72 Target RejectNegative Joined Var(riscv_tune_string)
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73 -mtune=PROCESSOR Optimize the output for PROCESSOR.
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74
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75 msmall-data-limit=
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76 Target Joined Separate UInteger Var(g_switch_value) Init(8)
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77 -msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
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78
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79 msave-restore
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80 Target Report Mask(SAVE_RESTORE)
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81 Use smaller but slower prologue and epilogue code.
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82
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83 mcmodel=
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84 Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
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85 Specify the code model.
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86
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87 mstrict-align
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88 Target Report Mask(STRICT_ALIGN) Save
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89 Do not generate unaligned memory accesses.
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90
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91 Enum
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92 Name(code_model) Type(enum riscv_code_model)
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93 Known code models (for use with the -mcmodel= option):
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94
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95 EnumValue
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96 Enum(code_model) String(medlow) Value(CM_MEDLOW)
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97
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98 EnumValue
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99 Enum(code_model) String(medany) Value(CM_MEDANY)
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100
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101 mexplicit-relocs
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102 Target Report Mask(EXPLICIT_RELOCS)
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103 Use %reloc() operators, rather than assembly macros, to load addresses.
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104
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105 Mask(64BIT)
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106
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107 Mask(MUL)
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108
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109 Mask(ATOMIC)
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110
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111 Mask(HARD_FLOAT)
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112
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113 Mask(DOUBLE_FLOAT)
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114
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115 Mask(RVC)
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