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comparison gcc/config/rs6000/darwin.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 /* Machine description patterns for PowerPC running Darwin (Mac OS X). 1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
2 Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc. 2 Copyright (C) 2004-2017 Free Software Foundation, Inc.
3 Contributed by Apple Computer Inc. 3 Contributed by Apple Computer Inc.
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GNU CC is free software; you can redistribute it and/or modify 7 GNU CC is free software; you can redistribute it and/or modify
21 (define_insn "adddi3_high" 21 (define_insn "adddi3_high"
22 [(set (match_operand:DI 0 "gpc_reg_operand" "=b") 22 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
23 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b") 23 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
24 (high:DI (match_operand 2 "" ""))))] 24 (high:DI (match_operand 2 "" ""))))]
25 "TARGET_MACHO && TARGET_64BIT" 25 "TARGET_MACHO && TARGET_64BIT"
26 "{cau|addis} %0,%1,ha16(%2)" 26 "addis %0,%1,ha16(%2)"
27 [(set_attr "length" "4")]) 27 [(set_attr "length" "4")])
28 28
29 (define_insn "movdf_low_si" 29 (define_insn "movdf_low_si"
30 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") 30 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
31 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 31 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
32 (match_operand 2 "" ""))))] 32 (match_operand 2 "" ""))))]
33 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT" 33 "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
34 "* 34 "*
35 { 35 {
36 switch (which_alternative) 36 switch (which_alternative)
37 { 37 {
38 case 0: 38 case 0:
42 if (TARGET_POWERPC64 && TARGET_32BIT) 42 if (TARGET_POWERPC64 && TARGET_32BIT)
43 /* Note, old assemblers didn't support relocation here. */ 43 /* Note, old assemblers didn't support relocation here. */
44 return \"ld %0,lo16(%2)(%1)\"; 44 return \"ld %0,lo16(%2)(%1)\";
45 else 45 else
46 { 46 {
47 output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands); 47 output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
48 output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands); 48 output_asm_insn (\"lwz %L0,4(%0)\", operands);
49 return (\"{l|lwz} %0,0(%0)\"); 49 return (\"lwz %0,0(%0)\");
50 } 50 }
51 } 51 }
52 default: 52 default:
53 gcc_unreachable (); 53 gcc_unreachable ();
54 } 54 }
59 59
60 (define_insn "movdf_low_di" 60 (define_insn "movdf_low_di"
61 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") 61 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
62 (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") 62 (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
63 (match_operand 2 "" ""))))] 63 (match_operand 2 "" ""))))]
64 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" 64 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
65 "* 65 "*
66 { 66 {
67 switch (which_alternative) 67 switch (which_alternative)
68 { 68 {
69 case 0: 69 case 0:
79 79
80 (define_insn "movdf_low_st_si" 80 (define_insn "movdf_low_st_si"
81 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 81 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
82 (match_operand 2 "" ""))) 82 (match_operand 2 "" "")))
83 (match_operand:DF 0 "gpc_reg_operand" "f"))] 83 (match_operand:DF 0 "gpc_reg_operand" "f"))]
84 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 84 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
85 "stfd %0,lo16(%2)(%1)" 85 "stfd %0,lo16(%2)(%1)"
86 [(set_attr "type" "store") 86 [(set_attr "type" "store")
87 (set_attr "length" "4")]) 87 (set_attr "length" "4")])
88 88
89 (define_insn "movdf_low_st_di" 89 (define_insn "movdf_low_st_di"
90 [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") 90 [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
91 (match_operand 2 "" ""))) 91 (match_operand 2 "" "")))
92 (match_operand:DF 0 "gpc_reg_operand" "f"))] 92 (match_operand:DF 0 "gpc_reg_operand" "f"))]
93 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" 93 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
94 "stfd %0,lo16(%2)(%1)" 94 "stfd %0,lo16(%2)(%1)"
95 [(set_attr "type" "store") 95 [(set_attr "type" "store")
96 (set_attr "length" "4")]) 96 (set_attr "length" "4")])
97 97
98 (define_insn "movsf_low_si" 98 (define_insn "movsf_low_si"
99 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") 99 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
100 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 100 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
101 (match_operand 2 "" ""))))] 101 (match_operand 2 "" ""))))]
102 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 102 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
103 "@ 103 "@
104 lfs %0,lo16(%2)(%1) 104 lfs %0,lo16(%2)(%1)
105 {l|lwz} %0,lo16(%2)(%1)" 105 lwz %0,lo16(%2)(%1)"
106 [(set_attr "type" "load") 106 [(set_attr "type" "load")
107 (set_attr "length" "4")]) 107 (set_attr "length" "4")])
108 108
109 (define_insn "movsf_low_di" 109 (define_insn "movsf_low_di"
110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") 110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
111 (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") 111 (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
112 (match_operand 2 "" ""))))] 112 (match_operand 2 "" ""))))]
113 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" 113 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
114 "@ 114 "@
115 lfs %0,lo16(%2)(%1) 115 lfs %0,lo16(%2)(%1)
116 {l|lwz} %0,lo16(%2)(%1)" 116 lwz %0,lo16(%2)(%1)"
117 [(set_attr "type" "load") 117 [(set_attr "type" "load")
118 (set_attr "length" "4")]) 118 (set_attr "length" "4")])
119 119
120 (define_insn "movsf_low_st_si" 120 (define_insn "movsf_low_st_si"
121 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 121 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
122 (match_operand 2 "" ""))) 122 (match_operand 2 "" "")))
123 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] 123 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
124 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 124 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
125 "@ 125 "@
126 stfs %0,lo16(%2)(%1) 126 stfs %0,lo16(%2)(%1)
127 {st|stw} %0,lo16(%2)(%1)" 127 stw %0,lo16(%2)(%1)"
128 [(set_attr "type" "store") 128 [(set_attr "type" "store")
129 (set_attr "length" "4")]) 129 (set_attr "length" "4")])
130 130
131 (define_insn "movsf_low_st_di" 131 (define_insn "movsf_low_st_di"
132 [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") 132 [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
133 (match_operand 2 "" ""))) 133 (match_operand 2 "" "")))
134 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] 134 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
135 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT" 135 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
136 "@ 136 "@
137 stfs %0,lo16(%2)(%1) 137 stfs %0,lo16(%2)(%1)
138 {st|stw} %0,lo16(%2)(%1)" 138 stw %0,lo16(%2)(%1)"
139 [(set_attr "type" "store") 139 [(set_attr "type" "store")
140 (set_attr "length" "4")]) 140 (set_attr "length" "4")])
141 141
142 ;; 64-bit MachO load/store support 142 ;; 64-bit MachO load/store support
143 (define_insn "movdi_low" 143 (define_insn "movdi_low"
144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d") 144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
145 (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") 145 (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
146 (match_operand 2 "" ""))))] 146 (match_operand 2 "" ""))))]
147 "TARGET_MACHO && TARGET_64BIT" 147 "TARGET_MACHO && TARGET_64BIT"
148 "@ 148 "@
149 {l|ld} %0,lo16(%2)(%1) 149 ld %0,lo16(%2)(%1)
150 lfd %0,lo16(%2)(%1)" 150 lfd %0,lo16(%2)(%1)"
151 [(set_attr "type" "load") 151 [(set_attr "type" "load")
152 (set_attr "length" "4")]) 152 (set_attr "length" "4")])
153 153
154 (define_insn "movsi_low_st" 154 (define_insn "movsi_low_st"
155 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 155 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
156 (match_operand 2 "" ""))) 156 (match_operand 2 "" "")))
157 (match_operand:SI 0 "gpc_reg_operand" "r"))] 157 (match_operand:SI 0 "gpc_reg_operand" "r"))]
158 "TARGET_MACHO && ! TARGET_64BIT" 158 "TARGET_MACHO && ! TARGET_64BIT"
159 "{st|stw} %0,lo16(%2)(%1)" 159 "stw %0,lo16(%2)(%1)"
160 [(set_attr "type" "store") 160 [(set_attr "type" "store")
161 (set_attr "length" "4")]) 161 (set_attr "length" "4")])
162 162
163 (define_insn "movdi_low_st" 163 (define_insn "movdi_low_st"
164 [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") 164 [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
165 (match_operand 2 "" ""))) 165 (match_operand 2 "" "")))
166 (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))] 166 (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
167 "TARGET_MACHO && TARGET_64BIT" 167 "TARGET_MACHO && TARGET_64BIT"
168 "@ 168 "@
169 {st|std} %0,lo16(%2)(%1) 169 std %0,lo16(%2)(%1)
170 stfd %0,lo16(%2)(%1)" 170 stfd %0,lo16(%2)(%1)"
171 [(set_attr "type" "store") 171 [(set_attr "type" "store")
172 (set_attr "length" "4")]) 172 (set_attr "length" "4")])
173 173
174 ;; Mach-O PIC trickery. 174 ;; Mach-O PIC trickery.
187 187
188 (define_insn "macho_high_si" 188 (define_insn "macho_high_si"
189 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 189 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
190 (high:SI (match_operand 1 "" "")))] 190 (high:SI (match_operand 1 "" "")))]
191 "TARGET_MACHO && ! TARGET_64BIT" 191 "TARGET_MACHO && ! TARGET_64BIT"
192 "{liu|lis} %0,ha16(%1)") 192 "lis %0,ha16(%1)")
193 193
194 194
195 (define_insn "macho_high_di" 195 (define_insn "macho_high_di"
196 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") 196 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
197 (high:DI (match_operand 1 "" "")))] 197 (high:DI (match_operand 1 "" "")))]
198 "TARGET_MACHO && TARGET_64BIT" 198 "TARGET_MACHO && TARGET_64BIT"
199 "{liu|lis} %0,ha16(%1)") 199 "lis %0,ha16(%1)")
200 200
201 (define_expand "macho_low" 201 (define_expand "macho_low"
202 [(set (match_operand 0 "" "") 202 [(set (match_operand 0 "" "")
203 (lo_sum (match_operand 1 "" "") 203 (lo_sum (match_operand 1 "" "")
204 (match_operand 2 "" "")))] 204 (match_operand 2 "" "")))]
211 211
212 DONE; 212 DONE;
213 }) 213 })
214 214
215 (define_insn "macho_low_si" 215 (define_insn "macho_low_si"
216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
217 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 217 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
218 (match_operand 2 "" "")))] 218 (match_operand 2 "" "")))]
219 "TARGET_MACHO && ! TARGET_64BIT" 219 "TARGET_MACHO && ! TARGET_64BIT"
220 "@ 220 "la %0,lo16(%2)(%1)")
221 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
222 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
223 221
224 (define_insn "macho_low_di" 222 (define_insn "macho_low_di"
225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 223 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
226 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") 224 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
227 (match_operand 2 "" "")))] 225 (match_operand 2 "" "")))]
228 "TARGET_MACHO && TARGET_64BIT" 226 "TARGET_MACHO && TARGET_64BIT"
229 "@ 227 "la %0,lo16(%2)(%1)")
230 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
231 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
232 228
233 (define_split 229 (define_split
234 [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") 230 [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
235 (match_operand:DI 1 "short_cint_operand" ""))) 231 (match_operand:DI 1 "short_cint_operand" "")))
236 (match_operand:V4SI 2 "register_operand" "")) 232 (match_operand:V4SI 2 "register_operand" ""))
240 (set (mem:V4SI (match_dup 3)) 236 (set (mem:V4SI (match_dup 3))
241 (match_dup 2))] 237 (match_dup 2))]
242 "") 238 "")
243 239
244 (define_expand "load_macho_picbase" 240 (define_expand "load_macho_picbase"
245 [(set (reg:SI 65) 241 [(set (reg:SI LR_REGNO)
246 (unspec [(match_operand 0 "" "")] 242 (unspec [(match_operand 0 "" "")]
247 UNSPEC_LD_MPIC))] 243 UNSPEC_LD_MPIC))]
248 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" 244 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
249 { 245 {
250 if (TARGET_32BIT) 246 if (TARGET_32BIT)
254 250
255 DONE; 251 DONE;
256 }) 252 })
257 253
258 (define_insn "load_macho_picbase_si" 254 (define_insn "load_macho_picbase_si"
259 [(set (reg:SI 65) 255 [(set (reg:SI LR_REGNO)
260 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") 256 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
261 (pc)] UNSPEC_LD_MPIC))] 257 (pc)] UNSPEC_LD_MPIC))]
262 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" 258 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
263 "bcl 20,31,%0\\n%0:" 259 {
260 #if TARGET_MACHO
261 machopic_should_output_picbase_label (); /* Update for new func. */
262 #else
263 gcc_unreachable ();
264 #endif
265 return "bcl 20,31,%0\\n%0:";
266 }
264 [(set_attr "type" "branch") 267 [(set_attr "type" "branch")
268 (set_attr "cannot_copy" "yes")
265 (set_attr "length" "4")]) 269 (set_attr "length" "4")])
266 270
267 (define_insn "load_macho_picbase_di" 271 (define_insn "load_macho_picbase_di"
268 [(set (reg:DI 65) 272 [(set (reg:DI LR_REGNO)
269 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s") 273 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
270 (pc)] UNSPEC_LD_MPIC))] 274 (pc)] UNSPEC_LD_MPIC))]
271 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT" 275 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
272 "bcl 20,31,%0\\n%0:" 276 {
277 #if TARGET_MACHO
278 machopic_should_output_picbase_label (); /* Update for new func. */
279 #else
280 gcc_unreachable ();
281 #endif
282 return "bcl 20,31,%0\\n%0:";
283 }
273 [(set_attr "type" "branch") 284 [(set_attr "type" "branch")
285 (set_attr "cannot_copy" "yes")
274 (set_attr "length" "4")]) 286 (set_attr "length" "4")])
275 287
276 (define_expand "macho_correct_pic" 288 (define_expand "macho_correct_pic"
277 [(set (match_operand 0 "" "") 289 [(set (match_operand 0 "" "")
278 (plus (match_operand 1 "" "") 290 (plus (match_operand 1 "" "")
313 325
314 (define_insn "*call_indirect_nonlocal_darwin64" 326 (define_insn "*call_indirect_nonlocal_darwin64"
315 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l")) 327 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
316 (match_operand 1 "" "g,g,g,g")) 328 (match_operand 1 "" "g,g,g,g"))
317 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) 329 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
318 (clobber (reg:SI 65))] 330 (clobber (reg:SI LR_REGNO))]
319 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT" 331 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
320 { 332 {
321 return "b%T0l"; 333 return "b%T0l";
322 } 334 }
323 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 335 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
325 337
326 (define_insn "*call_nonlocal_darwin64" 338 (define_insn "*call_nonlocal_darwin64"
327 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s")) 339 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
328 (match_operand 1 "" "g,g")) 340 (match_operand 1 "" "g,g"))
329 (use (match_operand:SI 2 "immediate_operand" "O,n")) 341 (use (match_operand:SI 2 "immediate_operand" "O,n"))
330 (clobber (reg:SI 65))] 342 (clobber (reg:SI LR_REGNO))]
331 "(DEFAULT_ABI == ABI_DARWIN) 343 "(DEFAULT_ABI == ABI_DARWIN)
332 && (INTVAL (operands[2]) & CALL_LONG) == 0" 344 && (INTVAL (operands[2]) & CALL_LONG) == 0"
333 { 345 {
334 #if TARGET_MACHO 346 #if TARGET_MACHO
335 return output_call(insn, operands, 0, 2); 347 return output_call(insn, operands, 0, 2);
343 (define_insn "*call_value_indirect_nonlocal_darwin64" 355 (define_insn "*call_value_indirect_nonlocal_darwin64"
344 [(set (match_operand 0 "" "") 356 [(set (match_operand 0 "" "")
345 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l")) 357 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
346 (match_operand 2 "" "g,g,g,g"))) 358 (match_operand 2 "" "g,g,g,g")))
347 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) 359 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
348 (clobber (reg:SI 65))] 360 (clobber (reg:SI LR_REGNO))]
349 "DEFAULT_ABI == ABI_DARWIN" 361 "DEFAULT_ABI == ABI_DARWIN"
350 { 362 {
351 return "b%T1l"; 363 return "b%T1l";
352 } 364 }
353 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 365 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
356 (define_insn "*call_value_nonlocal_darwin64" 368 (define_insn "*call_value_nonlocal_darwin64"
357 [(set (match_operand 0 "" "") 369 [(set (match_operand 0 "" "")
358 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s")) 370 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
359 (match_operand 2 "" "g,g"))) 371 (match_operand 2 "" "g,g")))
360 (use (match_operand:SI 3 "immediate_operand" "O,n")) 372 (use (match_operand:SI 3 "immediate_operand" "O,n"))
361 (clobber (reg:SI 65))] 373 (clobber (reg:SI LR_REGNO))]
362 "(DEFAULT_ABI == ABI_DARWIN) 374 "(DEFAULT_ABI == ABI_DARWIN)
363 && (INTVAL (operands[3]) & CALL_LONG) == 0" 375 && (INTVAL (operands[3]) & CALL_LONG) == 0"
364 { 376 {
365 #if TARGET_MACHO 377 #if TARGET_MACHO
366 return output_call(insn, operands, 1, 3); 378 return output_call(insn, operands, 1, 3);
369 #endif 381 #endif
370 } 382 }
371 [(set_attr "type" "branch,branch") 383 [(set_attr "type" "branch,branch")
372 (set_attr "length" "4,8")]) 384 (set_attr "length" "4,8")])
373 385
374 (define_insn "*sibcall_nonlocal_darwin64" 386 (define_expand "reload_macho_picbase"
375 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s")) 387 [(set (reg:SI LR_REGNO)
376 (match_operand 1 "" "")) 388 (unspec [(match_operand 0 "" "")]
377 (use (match_operand 2 "immediate_operand" "O,n")) 389 UNSPEC_RELD_MPIC))]
378 (use (reg:SI 65)) 390 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
379 (return)] 391 {
380 "(DEFAULT_ABI == ABI_DARWIN) 392 if (TARGET_32BIT)
381 && (INTVAL (operands[2]) & CALL_LONG) == 0" 393 emit_insn (gen_reload_macho_picbase_si (operands[0]));
382 { 394 else
383 return "b %z0"; 395 emit_insn (gen_reload_macho_picbase_di (operands[0]));
384 } 396
385 [(set_attr "type" "branch,branch") 397 DONE;
386 (set_attr "length" "4,8")]) 398 })
387 399
388 (define_insn "*sibcall_value_nonlocal_darwin64" 400 (define_insn "reload_macho_picbase_si"
389 [(set (match_operand 0 "" "") 401 [(set (reg:SI LR_REGNO)
390 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s")) 402 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
391 (match_operand 2 "" ""))) 403 (pc)] UNSPEC_RELD_MPIC))]
392 (use (match_operand:SI 3 "immediate_operand" "O,n")) 404 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
393 (use (reg:SI 65)) 405 {
394 (return)] 406 #if TARGET_MACHO
395 "(DEFAULT_ABI == ABI_DARWIN) 407 if (machopic_should_output_picbase_label ())
396 && (INTVAL (operands[3]) & CALL_LONG) == 0"
397 "*
398 {
399 return \"b %z1\";
400 }"
401 [(set_attr "type" "branch,branch")
402 (set_attr "length" "4,8")])
403
404
405 (define_insn "*sibcall_symbolic_64"
406 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
407 (match_operand 1 "" ""))
408 (use (match_operand 2 "" ""))
409 (use (reg:SI 65))
410 (return)]
411 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
412 "*
413 {
414 switch (which_alternative)
415 { 408 {
416 case 0: return \"b %z0\"; 409 static char tmp[64];
417 case 1: return \"b%T0\"; 410 const char *cnam = machopic_get_function_picbase ();
418 default: gcc_unreachable (); 411 snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
412 return tmp;
419 } 413 }
420 }" 414 else
415 #else
416 gcc_unreachable ();
417 #endif
418 return "bcl 20,31,%0\\n%0:";
419 }
421 [(set_attr "type" "branch") 420 [(set_attr "type" "branch")
422 (set_attr "length" "4")]) 421 (set_attr "cannot_copy" "yes")
423 422 (set_attr "length" "4")])
424 (define_insn "*sibcall_value_symbolic_64" 423
425 [(set (match_operand 0 "" "") 424 (define_insn "reload_macho_picbase_di"
426 (call (mem:SI (match_operand:DI 1 "call_operand" "s,c")) 425 [(set (reg:DI LR_REGNO)
427 (match_operand 2 "" ""))) 426 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
428 (use (match_operand:SI 3 "" "")) 427 (pc)] UNSPEC_RELD_MPIC))]
429 (use (reg:SI 65)) 428 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
430 (return)] 429 {
431 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN" 430 #if TARGET_MACHO
432 "* 431 if (machopic_should_output_picbase_label ())
433 {
434 switch (which_alternative)
435 { 432 {
436 case 0: return \"b %z1\"; 433 static char tmp[64];
437 case 1: return \"b%T1\"; 434 const char *cnam = machopic_get_function_picbase ();
438 default: gcc_unreachable (); 435 snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
436 return tmp;
439 } 437 }
440 }" 438 else
439 #else
440 gcc_unreachable ();
441 #endif
442 return "bcl 20,31,%0\\n%0:";
443 }
441 [(set_attr "type" "branch") 444 [(set_attr "type" "branch")
442 (set_attr "length" "4")]) 445 (set_attr "cannot_copy" "yes")
446 (set_attr "length" "4")])
447
448 ;; We need to restore the PIC register, at the site of nonlocal label.
449
450 (define_insn_and_split "nonlocal_goto_receiver"
451 [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
452 "TARGET_MACHO && flag_pic"
453 "#"
454 "&& reload_completed"
455 [(const_int 0)]
456 {
457 #if TARGET_MACHO
458 if (crtl->uses_pic_offset_table)
459 {
460 static unsigned n = 0;
461 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
462 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
463 rtx tmplrtx;
464 char tmplab[20];
465
466 ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
467 tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
468
469 emit_insn (gen_reload_macho_picbase (tmplrtx));
470 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
471 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
472 }
473 else
474 /* Not using PIC reg, no reload needed. */
475 emit_note (NOTE_INSN_DELETED);
476 #else
477 gcc_unreachable ();
478 #endif
479 DONE;
480 })