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comparison gcc/config/rs6000/mpc.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling description for Motorola PowerPC processor cores. 1 ;; Scheduling description for Motorola PowerPC processor cores.
2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published 7 ;; under the terms of the GNU General Public License as published
24 24
25 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU 25 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
26 ;; 505/801/821/823 26 ;; 505/801/821/823
27 27
28 (define_insn_reservation "mpccore-load" 2 28 (define_insn_reservation "mpccore-load" 2
29 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 29 (and (eq_attr "type" "load,load_l,store_c,sync")
30 load_l,store_c,sync")
31 (eq_attr "cpu" "mpccore")) 30 (eq_attr "cpu" "mpccore"))
32 "lsu_mpc") 31 "lsu_mpc")
33 32
34 (define_insn_reservation "mpccore-store" 2 33 (define_insn_reservation "mpccore-store" 2
35 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 34 (and (eq_attr "type" "store,fpstore")
36 (eq_attr "cpu" "mpccore")) 35 (eq_attr "cpu" "mpccore"))
37 "lsu_mpc") 36 "lsu_mpc")
38 37
39 (define_insn_reservation "mpccore-fpload" 2 38 (define_insn_reservation "mpccore-fpload" 2
40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 39 (and (eq_attr "type" "fpload")
41 (eq_attr "cpu" "mpccore")) 40 (eq_attr "cpu" "mpccore"))
42 "lsu_mpc") 41 "lsu_mpc")
43 42
44 (define_insn_reservation "mpccore-integer" 1 43 (define_insn_reservation "mpccore-integer" 1
45 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ 44 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
46 var_shift_rotate,cntlz,exts,isel") 45 (and (eq_attr "type" "add,logical,shift,exts")
46 (eq_attr "dot" "no")))
47 (eq_attr "cpu" "mpccore")) 47 (eq_attr "cpu" "mpccore"))
48 "iu_mpc") 48 "iu_mpc")
49 49
50 (define_insn_reservation "mpccore-two" 1 50 (define_insn_reservation "mpccore-two" 1
51 (and (eq_attr "type" "two") 51 (and (eq_attr "type" "two")
56 (and (eq_attr "type" "three") 56 (and (eq_attr "type" "three")
57 (eq_attr "cpu" "mpccore")) 57 (eq_attr "cpu" "mpccore"))
58 "iu_mpc,iu_mpc,iu_mpc") 58 "iu_mpc,iu_mpc,iu_mpc")
59 59
60 (define_insn_reservation "mpccore-imul" 2 60 (define_insn_reservation "mpccore-imul" 2
61 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 61 (and (eq_attr "type" "mul")
62 (eq_attr "cpu" "mpccore")) 62 (eq_attr "cpu" "mpccore"))
63 "mciu_mpc") 63 "mciu_mpc")
64 64
65 ; Divide latency varies greatly from 2-11, use 6 as average 65 ; Divide latency varies greatly from 2-11, use 6 as average
66 (define_insn_reservation "mpccore-idiv" 6 66 (define_insn_reservation "mpccore-idiv" 6
67 (and (eq_attr "type" "idiv") 67 (and (eq_attr "type" "div")
68 (eq_attr "cpu" "mpccore")) 68 (eq_attr "cpu" "mpccore"))
69 "mciu_mpc*6") 69 "mciu_mpc*6")
70 70
71 (define_insn_reservation "mpccore-compare" 3 71 (define_insn_reservation "mpccore-compare" 3
72 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ 72 (and (ior (eq_attr "type" "cmp")
73 var_delayed_compare") 73 (and (eq_attr "type" "add,logical,shift,exts")
74 (eq_attr "dot" "yes")))
74 (eq_attr "cpu" "mpccore")) 75 (eq_attr "cpu" "mpccore"))
75 "iu_mpc,nothing,bpu_mpc") 76 "iu_mpc,nothing,bpu_mpc")
76 77
77 (define_insn_reservation "mpccore-fpcompare" 2 78 (define_insn_reservation "mpccore-fpcompare" 2
78 (and (eq_attr "type" "fpcompare") 79 (and (eq_attr "type" "fpcompare")
79 (eq_attr "cpu" "mpccore")) 80 (eq_attr "cpu" "mpccore"))
80 "fpu_mpc,bpu_mpc") 81 "fpu_mpc,bpu_mpc")
81 82
82 (define_insn_reservation "mpccore-fp" 4 83 (define_insn_reservation "mpccore-fp" 4
83 (and (eq_attr "type" "fp") 84 (and (eq_attr "type" "fp,fpsimple")
84 (eq_attr "cpu" "mpccore")) 85 (eq_attr "cpu" "mpccore"))
85 "fpu_mpc*2") 86 "fpu_mpc*2")
86 87
87 (define_insn_reservation "mpccore-dmul" 5 88 (define_insn_reservation "mpccore-dmul" 5
88 (and (eq_attr "type" "dmul") 89 (and (eq_attr "type" "dmul")