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comparison gcc/config/rs6000/power7.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling description for IBM POWER7 processor. 1 ;; Scheduling description for IBM POWER7 processor.
2 ;; Copyright (C) 2009 Free Software Foundation, Inc. 2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). 4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 ;; 7 ;;
56 56
57 57
58 ; LS Unit 58 ; LS Unit
59 (define_insn_reservation "power7-load" 2 59 (define_insn_reservation "power7-load" 2
60 (and (eq_attr "type" "load") 60 (and (eq_attr "type" "load")
61 (eq_attr "sign_extend" "no")
62 (eq_attr "update" "no")
61 (eq_attr "cpu" "power7")) 63 (eq_attr "cpu" "power7"))
62 "DU_power7,LSU_power7") 64 "DU_power7,LSU_power7")
63 65
64 (define_insn_reservation "power7-load-ext" 3 66 (define_insn_reservation "power7-load-ext" 3
65 (and (eq_attr "type" "load_ext") 67 (and (eq_attr "type" "load")
68 (eq_attr "sign_extend" "yes")
69 (eq_attr "update" "no")
66 (eq_attr "cpu" "power7")) 70 (eq_attr "cpu" "power7"))
67 "DU2F_power7,LSU_power7,FXU_power7") 71 "DU2F_power7,LSU_power7,FXU_power7")
68 72
69 (define_insn_reservation "power7-load-update" 2 73 (define_insn_reservation "power7-load-update" 2
70 (and (eq_attr "type" "load_u") 74 (and (eq_attr "type" "load")
75 (eq_attr "sign_extend" "no")
76 (eq_attr "update" "yes")
77 (eq_attr "indexed" "no")
71 (eq_attr "cpu" "power7")) 78 (eq_attr "cpu" "power7"))
72 "DU2F_power7,LSU_power7+FXU_power7") 79 "DU2F_power7,LSU_power7+FXU_power7")
73 80
74 (define_insn_reservation "power7-load-update-indexed" 3 81 (define_insn_reservation "power7-load-update-indexed" 3
75 (and (eq_attr "type" "load_ux") 82 (and (eq_attr "type" "load")
83 (eq_attr "sign_extend" "no")
84 (eq_attr "update" "yes")
85 (eq_attr "indexed" "yes")
76 (eq_attr "cpu" "power7")) 86 (eq_attr "cpu" "power7"))
77 "DU4_power7,FXU_power7,LSU_power7+FXU_power7") 87 "DU4_power7,FXU_power7,LSU_power7+FXU_power7")
78 88
79 (define_insn_reservation "power7-load-ext-update" 4 89 (define_insn_reservation "power7-load-ext-update" 4
80 (and (eq_attr "type" "load_ext_u") 90 (and (eq_attr "type" "load")
91 (eq_attr "sign_extend" "yes")
92 (eq_attr "update" "yes")
93 (eq_attr "indexed" "no")
81 (eq_attr "cpu" "power7")) 94 (eq_attr "cpu" "power7"))
82 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7") 95 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
83 96
84 (define_insn_reservation "power7-load-ext-update-indexed" 4 97 (define_insn_reservation "power7-load-ext-update-indexed" 4
85 (and (eq_attr "type" "load_ext_ux") 98 (and (eq_attr "type" "load")
99 (eq_attr "sign_extend" "yes")
100 (eq_attr "update" "yes")
101 (eq_attr "indexed" "yes")
86 (eq_attr "cpu" "power7")) 102 (eq_attr "cpu" "power7"))
87 "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7") 103 "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
88 104
89 (define_insn_reservation "power7-fpload" 3 105 (define_insn_reservation "power7-fpload" 3
90 (and (eq_attr "type" "fpload") 106 (and (eq_attr "type" "fpload")
107 (eq_attr "update" "no")
91 (eq_attr "cpu" "power7")) 108 (eq_attr "cpu" "power7"))
92 "DU_power7,LSU_power7") 109 "DU_power7,LSU_power7")
93 110
94 (define_insn_reservation "power7-fpload-update" 3 111 (define_insn_reservation "power7-fpload-update" 3
95 (and (eq_attr "type" "fpload_u,fpload_ux") 112 (and (eq_attr "type" "fpload")
113 (eq_attr "update" "yes")
96 (eq_attr "cpu" "power7")) 114 (eq_attr "cpu" "power7"))
97 "DU2F_power7,LSU_power7+FXU_power7") 115 "DU2F_power7,LSU_power7+FXU_power7")
98 116
99 (define_insn_reservation "power7-store" 6 ; store-forwarding latency 117 (define_insn_reservation "power7-store" 6 ; store-forwarding latency
100 (and (eq_attr "type" "store") 118 (and (eq_attr "type" "store")
119 (eq_attr "update" "no")
101 (eq_attr "cpu" "power7")) 120 (eq_attr "cpu" "power7"))
102 "DU_power7,LSU_power7+FXU_power7") 121 "DU_power7,LSU_power7+FXU_power7")
103 122
104 (define_insn_reservation "power7-store-update" 6 123 (define_insn_reservation "power7-store-update" 6
105 (and (eq_attr "type" "store_u") 124 (and (eq_attr "type" "store")
125 (eq_attr "update" "yes")
126 (eq_attr "indexed" "no")
106 (eq_attr "cpu" "power7")) 127 (eq_attr "cpu" "power7"))
107 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7") 128 "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
108 129
109 (define_insn_reservation "power7-store-update-indexed" 6 130 (define_insn_reservation "power7-store-update-indexed" 6
110 (and (eq_attr "type" "store_ux") 131 (and (eq_attr "type" "store")
132 (eq_attr "update" "yes")
133 (eq_attr "indexed" "yes")
111 (eq_attr "cpu" "power7")) 134 (eq_attr "cpu" "power7"))
112 "DU4_power7,LSU_power7+FXU_power7,FXU_power7") 135 "DU4_power7,LSU_power7+FXU_power7,FXU_power7")
113 136
114 (define_insn_reservation "power7-fpstore" 6 137 (define_insn_reservation "power7-fpstore" 6
115 (and (eq_attr "type" "fpstore") 138 (and (eq_attr "type" "fpstore")
139 (eq_attr "update" "no")
116 (eq_attr "cpu" "power7")) 140 (eq_attr "cpu" "power7"))
117 "DU_power7,LSU_power7+VSU_power7") 141 "DU_power7,LSU_power7+VSU_power7")
118 142
119 (define_insn_reservation "power7-fpstore-update" 6 143 (define_insn_reservation "power7-fpstore-update" 6
120 (and (eq_attr "type" "fpstore_u,fpstore_ux") 144 (and (eq_attr "type" "fpstore")
145 (eq_attr "update" "yes")
121 (eq_attr "cpu" "power7")) 146 (eq_attr "cpu" "power7"))
122 "DU_power7,LSU_power7+VSU_power7+FXU_power7") 147 "DU_power7,LSU_power7+VSU_power7+FXU_power7")
123 148
124 (define_insn_reservation "power7-larx" 3 149 (define_insn_reservation "power7-larx" 3
125 (and (eq_attr "type" "load_l") 150 (and (eq_attr "type" "load_l")
137 "DU_power7,LSU_power7") 162 "DU_power7,LSU_power7")
138 163
139 (define_insn_reservation "power7-vecstore" 6 164 (define_insn_reservation "power7-vecstore" 6
140 (and (eq_attr "type" "vecstore") 165 (and (eq_attr "type" "vecstore")
141 (eq_attr "cpu" "power7")) 166 (eq_attr "cpu" "power7"))
142 "DU_power7,LSU_power7+VSU_power7") 167 "DU_power7,LSU_power7+vsu2_power7")
143 168
144 (define_insn_reservation "power7-sync" 11 169 (define_insn_reservation "power7-sync" 11
145 (and (eq_attr "type" "sync") 170 (and (eq_attr "type" "sync")
146 (eq_attr "cpu" "power7")) 171 (eq_attr "cpu" "power7"))
147 "DU4_power7,LSU_power7") 172 "DU4_power7,LSU_power7")
148 173
149 174
150 ; FX Unit 175 ; FX Unit
151 (define_insn_reservation "power7-integer" 1 176 (define_insn_reservation "power7-integer" 1
152 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ 177 (and (ior (eq_attr "type" "integer,insert,trap,isel,popcnt")
153 var_shift_rotate,exts,isel") 178 (and (eq_attr "type" "add,logical,shift,exts")
179 (eq_attr "dot" "no")))
154 (eq_attr "cpu" "power7")) 180 (eq_attr "cpu" "power7"))
155 "DU_power7,FXU_power7") 181 "DU_power7,FXU_power7")
156 182
157 (define_insn_reservation "power7-cntlz" 2 183 (define_insn_reservation "power7-cntlz" 2
158 (and (eq_attr "type" "cntlz") 184 (and (eq_attr "type" "cntlz")
168 (and (eq_attr "type" "three") 194 (and (eq_attr "type" "three")
169 (eq_attr "cpu" "power7")) 195 (eq_attr "cpu" "power7"))
170 "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7") 196 "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
171 197
172 (define_insn_reservation "power7-cmp" 1 198 (define_insn_reservation "power7-cmp" 1
173 (and (eq_attr "type" "cmp,fast_compare") 199 (and (ior (eq_attr "type" "cmp")
200 (and (eq_attr "type" "add,logical")
201 (eq_attr "dot" "yes")))
174 (eq_attr "cpu" "power7")) 202 (eq_attr "cpu" "power7"))
175 "DU_power7,FXU_power7") 203 "DU_power7,FXU_power7")
176 204
177 (define_insn_reservation "power7-compare" 2 205 (define_insn_reservation "power7-compare" 2
178 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") 206 (and (eq_attr "type" "shift,exts")
207 (eq_attr "dot" "yes")
179 (eq_attr "cpu" "power7")) 208 (eq_attr "cpu" "power7"))
180 "DU2F_power7,FXU_power7,FXU_power7") 209 "DU2F_power7,FXU_power7,FXU_power7")
181 210
182 (define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr") 211 (define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
183 212
184 (define_insn_reservation "power7-mul" 4 213 (define_insn_reservation "power7-mul" 4
185 (and (eq_attr "type" "imul,imul2,imul3,lmul") 214 (and (eq_attr "type" "mul")
215 (eq_attr "dot" "no")
186 (eq_attr "cpu" "power7")) 216 (eq_attr "cpu" "power7"))
187 "DU_power7,FXU_power7") 217 "DU_power7,FXU_power7")
188 218
189 (define_insn_reservation "power7-mul-compare" 5 219 (define_insn_reservation "power7-mul-compare" 5
190 (and (eq_attr "type" "imul_compare,lmul_compare") 220 (and (eq_attr "type" "mul")
221 (eq_attr "dot" "yes")
191 (eq_attr "cpu" "power7")) 222 (eq_attr "cpu" "power7"))
192 "DU2F_power7,FXU_power7,nothing*3,FXU_power7") 223 "DU2F_power7,FXU_power7,nothing*3,FXU_power7")
193 224
194 (define_insn_reservation "power7-idiv" 36 225 (define_insn_reservation "power7-idiv" 36
195 (and (eq_attr "type" "idiv") 226 (and (eq_attr "type" "div")
227 (eq_attr "size" "32")
196 (eq_attr "cpu" "power7")) 228 (eq_attr "cpu" "power7"))
197 "DU2F_power7,iu1_power7*36|iu2_power7*36") 229 "DU2F_power7,iu1_power7*36|iu2_power7*36")
198 230
199 (define_insn_reservation "power7-ldiv" 68 231 (define_insn_reservation "power7-ldiv" 68
200 (and (eq_attr "type" "ldiv") 232 (and (eq_attr "type" "div")
233 (eq_attr "size" "64")
201 (eq_attr "cpu" "power7")) 234 (eq_attr "cpu" "power7"))
202 "DU2F_power7,iu1_power7*68|iu2_power7*68") 235 "DU2F_power7,iu1_power7*68|iu2_power7*68")
203 236
204 (define_insn_reservation "power7-isync" 1 ; 237 (define_insn_reservation "power7-isync" 1 ;
205 (and (eq_attr "type" "isync") 238 (and (eq_attr "type" "isync")
257 |du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7") 290 |du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
258 291
259 292
260 ; VS Unit (includes FP/VSX/VMX/DFP) 293 ; VS Unit (includes FP/VSX/VMX/DFP)
261 (define_insn_reservation "power7-fp" 6 294 (define_insn_reservation "power7-fp" 6
262 (and (eq_attr "type" "fp,dmul") 295 (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
263 (eq_attr "cpu" "power7")) 296 (eq_attr "cpu" "power7"))
264 "DU_power7,VSU_power7") 297 "DU_power7,VSU_power7")
265 298
266 (define_bypass 8 "power7-fp" "power7-branch") 299 (define_bypass 8 "power7-fp" "power7-branch")
267 300
268 (define_insn_reservation "power7-fpcompare" 4 301 (define_insn_reservation "power7-fpcompare" 8
269 (and (eq_attr "type" "fpcompare") 302 (and (eq_attr "type" "fpcompare")
270 (eq_attr "cpu" "power7")) 303 (eq_attr "cpu" "power7"))
271 "DU_power7,VSU_power7") 304 "DU_power7,VSU_power7")
272 305
273 (define_insn_reservation "power7-sdiv" 26 306 (define_insn_reservation "power7-sdiv" 27
274 (and (eq_attr "type" "sdiv") 307 (and (eq_attr "type" "sdiv")
275 (eq_attr "cpu" "power7")) 308 (eq_attr "cpu" "power7"))
276 "DU_power7,VSU_power7") 309 "DU_power7,VSU_power7")
277 310
278 (define_insn_reservation "power7-ddiv" 32 311 (define_insn_reservation "power7-ddiv" 33
279 (and (eq_attr "type" "ddiv") 312 (and (eq_attr "type" "ddiv")
280 (eq_attr "cpu" "power7")) 313 (eq_attr "cpu" "power7"))
281 "DU_power7,VSU_power7") 314 "DU_power7,VSU_power7")
282 315
283 (define_insn_reservation "power7-sqrt" 31 316 (define_insn_reservation "power7-sqrt" 32
284 (and (eq_attr "type" "ssqrt") 317 (and (eq_attr "type" "ssqrt")
285 (eq_attr "cpu" "power7")) 318 (eq_attr "cpu" "power7"))
286 "DU_power7,VSU_power7") 319 "DU_power7,VSU_power7")
287 320
288 (define_insn_reservation "power7-dsqrt" 43 321 (define_insn_reservation "power7-dsqrt" 44
289 (and (eq_attr "type" "dsqrt") 322 (and (eq_attr "type" "dsqrt")
290 (eq_attr "cpu" "power7")) 323 (eq_attr "cpu" "power7"))
291 "DU_power7,VSU_power7") 324 "DU_power7,VSU_power7")
292 325
293 (define_insn_reservation "power7-vecsimple" 2 326 (define_insn_reservation "power7-vecsimple" 2
294 (and (eq_attr "type" "vecsimple") 327 (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
295 (eq_attr "cpu" "power7")) 328 (eq_attr "cpu" "power7"))
296 "du1_power7,VSU_power7") 329 "DU_power7,vsu1_power7")
297 330
298 (define_insn_reservation "power7-veccmp" 7 331 (define_insn_reservation "power7-vecfloat" 6
299 (and (eq_attr "type" "veccmp")
300 (eq_attr "cpu" "power7"))
301 "du1_power7,VSU_power7")
302
303 (define_insn_reservation "power7-vecfloat" 7
304 (and (eq_attr "type" "vecfloat") 332 (and (eq_attr "type" "vecfloat")
305 (eq_attr "cpu" "power7")) 333 (eq_attr "cpu" "power7"))
306 "du1_power7,VSU_power7") 334 "DU_power7,vsu1_power7")
307 335
308 (define_bypass 6 "power7-vecfloat" "power7-vecfloat") 336 (define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\
337 power7-vecperm")
309 338
310 (define_insn_reservation "power7-veccomplex" 7 339 (define_insn_reservation "power7-veccomplex" 7
311 (and (eq_attr "type" "veccomplex") 340 (and (eq_attr "type" "veccomplex")
312 (eq_attr "cpu" "power7")) 341 (eq_attr "cpu" "power7"))
313 "du1_power7,VSU_power7") 342 "DU_power7,vsu1_power7")
314 343
315 (define_insn_reservation "power7-vecperm" 3 344 (define_insn_reservation "power7-vecperm" 3
316 (and (eq_attr "type" "vecperm") 345 (and (eq_attr "type" "vecperm")
317 (eq_attr "cpu" "power7")) 346 (eq_attr "cpu" "power7"))
318 "du2_power7,VSU_power7") 347 "DU_power7,vsu2_power7")
348
349 (define_insn_reservation "power7-vecdouble" 6
350 (and (eq_attr "type" "vecdouble")
351 (eq_attr "cpu" "power7"))
352 "DU_power7,VSU_power7")
353
354 (define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\
355 power7-vecperm")
356
357 (define_insn_reservation "power7-vecfdiv" 26
358 (and (eq_attr "type" "vecfdiv")
359 (eq_attr "cpu" "power7"))
360 "DU_power7,VSU_power7")
361
362 (define_insn_reservation "power7-vecdiv" 32
363 (and (eq_attr "type" "vecdiv")
364 (eq_attr "cpu" "power7"))
365 "DU_power7,VSU_power7")
366