--- a/gcc/config/rs6000/power7.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/rs6000/power7.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; Scheduling description for IBM POWER7 processor.
-;; Copyright (C) 2009 Free Software Foundation, Inc.
+;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
 
@@ -58,66 +58,91 @@
 ; LS Unit
 (define_insn_reservation "power7-load" 2
   (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "no")
+       (eq_attr "update" "no")
        (eq_attr "cpu" "power7"))
   "DU_power7,LSU_power7")
 
 (define_insn_reservation "power7-load-ext" 3
-  (and (eq_attr "type" "load_ext")
+  (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "yes")
+       (eq_attr "update" "no")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,LSU_power7,FXU_power7")
 
 (define_insn_reservation "power7-load-update" 2
-  (and (eq_attr "type" "load_u")
+  (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "no")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "no")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,LSU_power7+FXU_power7")
 
 (define_insn_reservation "power7-load-update-indexed" 3
-  (and (eq_attr "type" "load_ux")
+  (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "no")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "yes")
        (eq_attr "cpu" "power7"))
   "DU4_power7,FXU_power7,LSU_power7+FXU_power7")
 
 (define_insn_reservation "power7-load-ext-update" 4
-  (and (eq_attr "type" "load_ext_u")
+  (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "yes")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "no")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
 
 (define_insn_reservation "power7-load-ext-update-indexed" 4
-  (and (eq_attr "type" "load_ext_ux")
+  (and (eq_attr "type" "load")
+       (eq_attr "sign_extend" "yes")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "yes")
        (eq_attr "cpu" "power7"))
   "DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
 
 (define_insn_reservation "power7-fpload" 3
   (and (eq_attr "type" "fpload")
+       (eq_attr "update" "no")
        (eq_attr "cpu" "power7"))
   "DU_power7,LSU_power7")
 
 (define_insn_reservation "power7-fpload-update" 3
-  (and (eq_attr "type" "fpload_u,fpload_ux")
+  (and (eq_attr "type" "fpload")
+       (eq_attr "update" "yes")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,LSU_power7+FXU_power7")
 
 (define_insn_reservation "power7-store" 6 ; store-forwarding latency
   (and (eq_attr "type" "store")
+       (eq_attr "update" "no")
        (eq_attr "cpu" "power7"))
   "DU_power7,LSU_power7+FXU_power7")
 
 (define_insn_reservation "power7-store-update" 6
-  (and (eq_attr "type" "store_u")
+  (and (eq_attr "type" "store")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "no")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
 
 (define_insn_reservation "power7-store-update-indexed" 6
-  (and (eq_attr "type" "store_ux")
+  (and (eq_attr "type" "store")
+       (eq_attr "update" "yes")
+       (eq_attr "indexed" "yes")
        (eq_attr "cpu" "power7"))
   "DU4_power7,LSU_power7+FXU_power7,FXU_power7")
 
 (define_insn_reservation "power7-fpstore" 6
   (and (eq_attr "type" "fpstore")
+       (eq_attr "update" "no")
        (eq_attr "cpu" "power7"))
   "DU_power7,LSU_power7+VSU_power7")
 
 (define_insn_reservation "power7-fpstore-update" 6
-  (and (eq_attr "type" "fpstore_u,fpstore_ux")
+  (and (eq_attr "type" "fpstore")
+       (eq_attr "update" "yes")
        (eq_attr "cpu" "power7"))
   "DU_power7,LSU_power7+VSU_power7+FXU_power7")
 
@@ -139,7 +164,7 @@
 (define_insn_reservation "power7-vecstore" 6
   (and (eq_attr "type" "vecstore")
        (eq_attr "cpu" "power7"))
-  "DU_power7,LSU_power7+VSU_power7")
+  "DU_power7,LSU_power7+vsu2_power7")
 
 (define_insn_reservation "power7-sync" 11
   (and (eq_attr "type" "sync")
@@ -149,8 +174,9 @@
 
 ; FX Unit
 (define_insn_reservation "power7-integer" 1
-  (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
-                        var_shift_rotate,exts,isel")
+  (and (ior (eq_attr "type" "integer,insert,trap,isel,popcnt")
+	    (and (eq_attr "type" "add,logical,shift,exts")
+		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "power7"))
   "DU_power7,FXU_power7")
 
@@ -170,34 +196,41 @@
   "DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
 
 (define_insn_reservation "power7-cmp" 1
-  (and (eq_attr "type" "cmp,fast_compare")
+  (and (ior (eq_attr "type" "cmp")
+	    (and (eq_attr "type" "add,logical")
+		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power7"))
   "DU_power7,FXU_power7")
 
 (define_insn_reservation "power7-compare" 2
-  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+  (and (eq_attr "type" "shift,exts")
+       (eq_attr "dot" "yes")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,FXU_power7,FXU_power7")
 
 (define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
 
 (define_insn_reservation "power7-mul" 4
-  (and (eq_attr "type" "imul,imul2,imul3,lmul")
+  (and (eq_attr "type" "mul")
+       (eq_attr "dot" "no")
        (eq_attr "cpu" "power7"))
   "DU_power7,FXU_power7")
 
 (define_insn_reservation "power7-mul-compare" 5
-  (and (eq_attr "type" "imul_compare,lmul_compare")
+  (and (eq_attr "type" "mul")
+       (eq_attr "dot" "yes")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,FXU_power7,nothing*3,FXU_power7")
 
 (define_insn_reservation "power7-idiv" 36
-  (and (eq_attr "type" "idiv")
+  (and (eq_attr "type" "div")
+       (eq_attr "size" "32")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,iu1_power7*36|iu2_power7*36")
 
 (define_insn_reservation "power7-ldiv" 68
-  (and (eq_attr "type" "ldiv")
+  (and (eq_attr "type" "div")
+       (eq_attr "size" "64")
        (eq_attr "cpu" "power7"))
   "DU2F_power7,iu1_power7*68|iu2_power7*68")
 
@@ -259,60 +292,75 @@
 
 ; VS Unit (includes FP/VSX/VMX/DFP)
 (define_insn_reservation "power7-fp" 6
-  (and (eq_attr "type" "fp,dmul")
+  (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
 (define_bypass 8 "power7-fp" "power7-branch")
 
-(define_insn_reservation "power7-fpcompare" 4
+(define_insn_reservation "power7-fpcompare" 8
   (and (eq_attr "type" "fpcompare")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
-(define_insn_reservation "power7-sdiv" 26
+(define_insn_reservation "power7-sdiv" 27
   (and (eq_attr "type" "sdiv")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
-(define_insn_reservation "power7-ddiv" 32
+(define_insn_reservation "power7-ddiv" 33
   (and (eq_attr "type" "ddiv")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
-(define_insn_reservation "power7-sqrt" 31
+(define_insn_reservation "power7-sqrt" 32
   (and (eq_attr "type" "ssqrt")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
-(define_insn_reservation "power7-dsqrt" 43
+(define_insn_reservation "power7-dsqrt" 44
   (and (eq_attr "type" "dsqrt")
        (eq_attr "cpu" "power7"))
   "DU_power7,VSU_power7")
 
 (define_insn_reservation "power7-vecsimple" 2
-  (and (eq_attr "type" "vecsimple")
+  (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
        (eq_attr "cpu" "power7"))
-  "du1_power7,VSU_power7")
+  "DU_power7,vsu1_power7")
 
-(define_insn_reservation "power7-veccmp" 7
-  (and (eq_attr "type" "veccmp")
-       (eq_attr "cpu" "power7"))
-  "du1_power7,VSU_power7")
-
-(define_insn_reservation "power7-vecfloat" 7
+(define_insn_reservation "power7-vecfloat" 6
   (and (eq_attr "type" "vecfloat")
        (eq_attr "cpu" "power7"))
-  "du1_power7,VSU_power7")
+  "DU_power7,vsu1_power7")
 
-(define_bypass 6 "power7-vecfloat" "power7-vecfloat")
+(define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\
+				    power7-vecperm")
 
 (define_insn_reservation "power7-veccomplex" 7
   (and (eq_attr "type" "veccomplex")
        (eq_attr "cpu" "power7"))
-  "du1_power7,VSU_power7")
+  "DU_power7,vsu1_power7")
 
 (define_insn_reservation "power7-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "cpu" "power7"))
-  "du2_power7,VSU_power7")
+  "DU_power7,vsu2_power7")
+
+(define_insn_reservation "power7-vecdouble" 6
+  (and (eq_attr "type" "vecdouble")
+       (eq_attr "cpu" "power7"))
+  "DU_power7,VSU_power7")
+
+(define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\
+				    power7-vecperm")
+
+(define_insn_reservation "power7-vecfdiv" 26
+  (and (eq_attr "type" "vecfdiv")
+       (eq_attr "cpu" "power7"))
+  "DU_power7,VSU_power7")
+
+(define_insn_reservation "power7-vecdiv" 32
+  (and (eq_attr "type" "vecdiv")
+       (eq_attr "cpu" "power7"))
+  "DU_power7,VSU_power7")
+