Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/rx/rx.opt @ 111:04ced10e8804

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ; Command line options for the Renesas RX port of GCC. 1 ; Command line options for the Renesas RX port of GCC.
2 ; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. 2 ; Copyright (C) 2008-2017 Free Software Foundation, Inc.
3 ; Contributed by Red Hat. 3 ; Contributed by Red Hat.
4 ; 4 ;
5 ; This file is part of GCC. 5 ; This file is part of GCC.
6 ; 6 ;
7 ; GCC is free software; you can redistribute it and/or modify it under 7 ; GCC is free software; you can redistribute it and/or modify it under
16 ; 16 ;
17 ; You should have received a copy of the GNU General Public License 17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see 18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>. 19 ; <http://www.gnu.org/licenses/>.
20 ;--------------------------------------------------- 20 ;---------------------------------------------------
21
22 HeaderInclude
23 config/rx/rx-opts.h
21 24
22 ; The default is -fpu -m32bit-doubles. 25 ; The default is -fpu -m32bit-doubles.
23 26
24 m64bit-doubles 27 m64bit-doubles
25 Target RejectNegative Mask(64BIT_DOUBLES) Report 28 Target RejectNegative Mask(64BIT_DOUBLES) Report
41 Enable the use of RX FPU instructions. This is the default. 44 Enable the use of RX FPU instructions. This is the default.
42 45
43 ;--------------------------------------------------- 46 ;---------------------------------------------------
44 47
45 mcpu= 48 mcpu=
46 Target RejectNegative Joined Var(rx_cpu_name) Report 49 Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600)
47 Specify the target RX cpu type. 50 Specify the target RX cpu type.
51
52 Enum
53 Name(rx_cpu_types) Type(enum rx_cpu_types)
54
55 EnumValue
56 Enum(rx_cpu_types) String(rx610) Value(RX610)
57
58 EnumValue
59 Enum(rx_cpu_types) String(rx200) Value(RX200)
60
61 EnumValue
62 Enum(rx_cpu_types) String(rx600) Value(RX600)
63
64 EnumValue
65 Enum(rx_cpu_types) String(rx100) Value(RX100)
48 66
49 ;--------------------------------------------------- 67 ;---------------------------------------------------
50 68
51 mbig-endian-data 69 mbig-endian-data
52 Target RejectNegative Mask(BIG_ENDIAN_DATA) Report 70 Target RejectNegative Mask(BIG_ENDIAN_DATA) Report
70 88
71 ;--------------------------------------------------- 89 ;---------------------------------------------------
72 90
73 mas100-syntax 91 mas100-syntax
74 Target Mask(AS100_SYNTAX) Report 92 Target Mask(AS100_SYNTAX) Report
75 Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatable syntax. 93 Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax.
76 94
77 ;--------------------------------------------------- 95 ;---------------------------------------------------
78 96
79 mrelax 97 mrelax
80 Target 98 Target
87 Maximum size in bytes of constant values allowed as operands. 105 Maximum size in bytes of constant values allowed as operands.
88 106
89 ;--------------------------------------------------- 107 ;---------------------------------------------------
90 108
91 mint-register= 109 mint-register=
92 Target RejectNegative Joined UInteger Var(rx_interrupt_registers) Init(0) 110 Target RejectNegative Joined UInteger Var(rx_deferred_options) Defer
93 Specifies the number of registers to reserve for interrupt handlers. 111 Specifies the number of registers to reserve for interrupt handlers.
94 112
95 ;--------------------------------------------------- 113 ;---------------------------------------------------
96 114
97 msave-acc-in-interrupts 115 msave-acc-in-interrupts
98 Target Mask(SAVE_ACC_REGISTER) 116 Target Mask(SAVE_ACC_REGISTER)
99 Specifies whether interrupt functions should save and restore the accumulator register. 117 Specifies whether interrupt functions should save and restore the accumulator register.
118
119 ;---------------------------------------------------
120
121 mpid
122 Target Mask(PID)
123 Enables Position-Independent-Data (PID) mode.
124
125 ;---------------------------------------------------
126
127 mwarn-multiple-fast-interrupts
128 Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
129 Warn when multiple, different, fast interrupt handlers are in the compilation unit.
130
131 ;---------------------------------------------------
132
133 mgcc-abi
134 Target RejectNegative Report Mask(GCC_ABI)
135 Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits.
136
137 mrx-abi
138 Target RejectNegative Report InverseMask(GCC_ABI)
139 Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default.
140
141 ;---------------------------------------------------
142
143 mlra
144 Target Report Mask(ENABLE_LRA)
145 Enable the use of the LRA register allocator.
146
147 ;---------------------------------------------------
148
149 mallow-string-insns
150 Target Report Var(rx_allow_string_insns) Init(1)
151 Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default.
152
153 ;---------------------------------------------------
154
155 mjsr
156 Target Report Mask(JSR)
157 Always use JSR, never BSR, for calls.