--- a/gcc/config/rx/rx.opt	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/rx/rx.opt	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ; Command line options for the Renesas RX port of GCC.
-; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+; Copyright (C) 2008-2017 Free Software Foundation, Inc.
 ; Contributed by Red Hat.
 ;
 ; This file is part of GCC.
@@ -19,6 +19,9 @@
 ; <http://www.gnu.org/licenses/>.
 ;---------------------------------------------------
 
+HeaderInclude
+config/rx/rx-opts.h
+
 ; The default is -fpu -m32bit-doubles.
 
 m64bit-doubles
@@ -43,9 +46,24 @@
 ;---------------------------------------------------
 
 mcpu=
-Target RejectNegative Joined Var(rx_cpu_name) Report
+Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600)
 Specify the target RX cpu type.
 
+Enum
+Name(rx_cpu_types) Type(enum rx_cpu_types)
+
+EnumValue
+Enum(rx_cpu_types) String(rx610) Value(RX610)
+
+EnumValue
+Enum(rx_cpu_types) String(rx200) Value(RX200)
+
+EnumValue
+Enum(rx_cpu_types) String(rx600) Value(RX600)
+
+EnumValue
+Enum(rx_cpu_types) String(rx100) Value(RX100)
+
 ;---------------------------------------------------
 
 mbig-endian-data
@@ -72,7 +90,7 @@
 
 mas100-syntax
 Target Mask(AS100_SYNTAX) Report
-Generate assembler output that is compatible with the Renesas AS100 assembler.  This may restrict some of the compiler's capabilities.  The default is to generate GAS compatable syntax.
+Generate assembler output that is compatible with the Renesas AS100 assembler.  This may restrict some of the compiler's capabilities.  The default is to generate GAS compatible syntax.
 
 ;---------------------------------------------------
 
@@ -89,7 +107,7 @@
 ;---------------------------------------------------
 
 mint-register=
-Target RejectNegative Joined UInteger Var(rx_interrupt_registers) Init(0)
+Target RejectNegative Joined UInteger Var(rx_deferred_options) Defer
 Specifies the number of registers to reserve for interrupt handlers.
 
 ;---------------------------------------------------
@@ -97,3 +115,43 @@
 msave-acc-in-interrupts
 Target Mask(SAVE_ACC_REGISTER)
 Specifies whether interrupt functions should save and restore the accumulator register.
+
+;---------------------------------------------------
+
+mpid
+Target Mask(PID)
+Enables Position-Independent-Data (PID) mode.
+
+;---------------------------------------------------
+
+mwarn-multiple-fast-interrupts
+Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
+Warn when multiple, different, fast interrupt handlers are in the compilation unit.
+
+;---------------------------------------------------
+
+mgcc-abi
+Target RejectNegative Report Mask(GCC_ABI)
+Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits.
+
+mrx-abi
+Target RejectNegative Report InverseMask(GCC_ABI)
+Enable the use the standard RX ABI where all stacked function arguments are naturally aligned.  This is the default.
+
+;---------------------------------------------------
+
+mlra
+Target Report Mask(ENABLE_LRA)
+Enable the use of the LRA register allocator.
+
+;---------------------------------------------------
+
+mallow-string-insns
+Target Report Var(rx_allow_string_insns) Init(1)
+Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions.  Enabled by default.
+
+;---------------------------------------------------
+
+mjsr
+Target Report Mask(JSR)
+Always use JSR, never BSR, for calls.