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comparison gcc/config/v850/v850.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 ;; GCC machine description for NEC V850 1 ;; GCC machine description for NEC V850
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010 2 ;; Copyright (C) 1996-2017 Free Software Foundation, Inc.
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com). 3 ;; Contributed by Jeff Law (law@cygnus.com).
5 4
6 ;; This file is part of GCC. 5 ;; This file is part of GCC.
7 6
8 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
38 ;; 37 ;;
39 (define_constants 38 (define_constants
40 [(ZERO_REGNUM 0) ; constant zero 39 [(ZERO_REGNUM 0) ; constant zero
41 (SP_REGNUM 3) ; Stack Pointer 40 (SP_REGNUM 3) ; Stack Pointer
42 (GP_REGNUM 4) ; GP Pointer 41 (GP_REGNUM 4) ; GP Pointer
42 (RV_REGNUM 10) ; Return value register
43 (EP_REGNUM 30) ; EP pointer 43 (EP_REGNUM 30) ; EP pointer
44 (LP_REGNUM 31) ; Return address register 44 (LP_REGNUM 31) ; Return address register
45 (CC_REGNUM 32) ; Condition code pseudo register 45 (CC_REGNUM 32) ; Condition code pseudo register
46 (FCC_REGNUM 33) ; Floating Condition code pseudo register 46 (FCC_REGNUM 33) ; Floating Condition code pseudo register
47 (UNSPEC_LOOP 200) ; loop counter
47 ] 48 ]
48 ) 49 )
49 50
50 (define_attr "length" "" 51 (define_attr "length" ""
51 (const_int 4)) 52 (const_int 4))
58 ;; Types of instructions (for scheduling purposes). 59 ;; Types of instructions (for scheduling purposes).
59 60
60 (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other" 61 (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other"
61 (const_string "other")) 62 (const_string "other"))
62 63
63 (define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3" 64 (define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3,v850e3v5"
64 (cond [(ne (symbol_ref "TARGET_V850") (const_int 0)) 65 (cond [(match_test "TARGET_V850")
65 (const_string "v850") 66 (const_string "v850")
66 (ne (symbol_ref "TARGET_V850E") (const_int 0)) 67 (match_test "TARGET_V850E")
67 (const_string "v850e") 68 (const_string "v850e")
68 (ne (symbol_ref "TARGET_V850E1") (const_int 0)) 69 (match_test "TARGET_V850E1")
69 (const_string "v850e1") 70 (const_string "v850e1")
70 (ne (symbol_ref "TARGET_V850E2") (const_int 0)) 71 (match_test "TARGET_V850E2")
71 (const_string "v850e2") 72 (const_string "v850e2")
72 (ne (symbol_ref "TARGET_V850E2") (const_int 0)) 73 (match_test "TARGET_V850E2V3")
73 (const_string "v850e2v3")] 74 (const_string "v850e2v3")
74 (const_string "none"))) 75 (match_test "TARGET_V850E3V5")
76 (const_string "v850e3v5")]
77 (const_string "none")))
75 78
76 ;; Condition code settings. 79 ;; Condition code settings.
77 ;; none - insn does not affect cc 80 ;; none - insn does not affect cc
78 ;; none_0hit - insn does not affect cc but it does modify operand 0 81 ;; none_0hit - insn does not affect cc but it does modify operand 0
79 ;; This attribute is used to keep track of when operand 0 changes. 82 ;; This attribute is used to keep track of when operand 0 changes.
108 (define_insn "sign23byte_load" 111 (define_insn "sign23byte_load"
109 [(set (match_operand:SI 0 "register_operand" "=r") 112 [(set (match_operand:SI 0 "register_operand" "=r")
110 (sign_extend:SI 113 (sign_extend:SI
111 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") 114 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
112 (match_operand 2 "disp23_operand" "W")))))] 115 (match_operand 2 "disp23_operand" "W")))))]
113 "TARGET_V850E2V3" 116 "TARGET_V850E2V3_UP"
114 "ld.b %2[%1],%0" 117 "ld.b %2[%1],%0"
115 [(set_attr "length" "4") 118 [(set_attr "length" "4")
116 (set_attr "cc" "none_0hit")]) 119 (set_attr "cc" "none_0hit")])
117 120
118 (define_insn "unsign23byte_load" 121 (define_insn "unsign23byte_load"
119 [(set (match_operand:SI 0 "register_operand" "=r") 122 [(set (match_operand:SI 0 "register_operand" "=r")
120 (zero_extend:SI 123 (zero_extend:SI
121 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") 124 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
122 (match_operand 2 "disp23_operand" "W")))))] 125 (match_operand 2 "disp23_operand" "W")))))]
123 "TARGET_V850E2V3" 126 "TARGET_V850E2V3_UP"
124 "ld.bu %2[%1],%0" 127 "ld.bu %2[%1],%0"
125 [(set_attr "length" "4") 128 [(set_attr "length" "4")
126 (set_attr "cc" "none_0hit")]) 129 (set_attr "cc" "none_0hit")])
127 130
128 (define_insn "sign23hword_load" 131 (define_insn "sign23hword_load"
129 [(set (match_operand:SI 0 "register_operand" "=r") 132 [(set (match_operand:SI 0 "register_operand" "=r")
130 (sign_extend:SI 133 (sign_extend:SI
131 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") 134 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
132 (match_operand 2 "disp23_operand" "W")))))] 135 (match_operand 2 "disp23_operand" "W")))))]
133 "TARGET_V850E2V3" 136 "TARGET_V850E2V3_UP"
134 "ld.h %2[%1],%0" 137 "ld.h %2[%1],%0"
135 [(set_attr "length" "4") 138 [(set_attr "length" "4")
136 (set_attr "cc" "none_0hit")]) 139 (set_attr "cc" "none_0hit")])
137 140
138 (define_insn "unsign23hword_load" 141 (define_insn "unsign23hword_load"
139 [(set (match_operand:SI 0 "register_operand" "=r") 142 [(set (match_operand:SI 0 "register_operand" "=r")
140 (zero_extend:SI 143 (zero_extend:SI
141 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") 144 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
142 (match_operand 2 "disp23_operand" "W")))))] 145 (match_operand 2 "disp23_operand" "W")))))]
143 "TARGET_V850E2V3" 146 "TARGET_V850E2V3_UP"
144 "ld.hu %2[%1],%0" 147 "ld.hu %2[%1],%0"
145 [(set_attr "length" "4") 148 [(set_attr "length" "4")
146 (set_attr "cc" "none_0hit")]) 149 (set_attr "cc" "none_0hit")])
147 150
148 (define_insn "23word_load" 151 (define_insn "23word_load"
149 [(set (match_operand:SI 0 "register_operand" "=r") 152 [(set (match_operand:SI 0 "register_operand" "=r")
150 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") 153 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
151 (match_operand 2 "disp23_operand" "W"))))] 154 (match_operand 2 "disp23_operand" "W"))))]
152 "TARGET_V850E2V3" 155 "TARGET_V850E2V3_UP"
153 "ld.w %2[%1],%0" 156 "ld.w %2[%1],%0"
154 [(set_attr "length" "4") 157 [(set_attr "length" "4")
155 (set_attr "cc" "none_0hit")]) 158 (set_attr "cc" "none_0hit")])
156 159
157 (define_insn "23byte_store" 160 (define_insn "23byte_store"
158 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r") 161 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
159 (match_operand 1 "disp23_operand" "W"))) 162 (match_operand 1 "disp23_operand" "W")))
160 (match_operand:QI 2 "register_operand" "r"))] 163 (match_operand:QI 2 "register_operand" "r"))]
161 "TARGET_V850E2V3" 164 "TARGET_V850E2V3_UP"
162 "st.b %2,%1[%0]" 165 "st.b %2,%1[%0]"
163 [(set_attr "length" "4") 166 [(set_attr "length" "4")
164 (set_attr "cc" "none_0hit")]) 167 (set_attr "cc" "none_0hit")])
165 168
166 (define_insn "23hword_store" 169 (define_insn "23hword_store"
167 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r") 170 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r")
168 (match_operand 1 "disp23_operand" "W"))) 171 (match_operand 1 "disp23_operand" "W")))
169 (match_operand:HI 2 "register_operand" "r"))] 172 (match_operand:HI 2 "register_operand" "r"))]
170 "TARGET_V850E2V3" 173 "TARGET_V850E2V3_UP"
171 "st.h %2,%1[%0]" 174 "st.h %2,%1[%0]"
172 [(set_attr "length" "4") 175 [(set_attr "length" "4")
173 (set_attr "cc" "none_0hit")]) 176 (set_attr "cc" "none_0hit")])
174 177
175 (define_insn "23word_store" 178 (define_insn "23word_store"
176 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") 179 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
177 (match_operand 1 "disp23_operand" "W"))) 180 (match_operand 1 "disp23_operand" "W")))
178 (match_operand:SI 2 "register_operand" "r"))] 181 (match_operand:SI 2 "register_operand" "r"))]
179 "TARGET_V850E2V3" 182 "TARGET_V850E2V3_UP"
180 "st.w %2,%1[%0]" 183 "st.w %2,%1[%0]"
181 [(set_attr "length" "4") 184 [(set_attr "length" "4")
182 (set_attr "cc" "none_0hit")]) 185 (set_attr "cc" "none_0hit")])
186
187 ;; movdi
188
189 (define_expand "movdi"
190 [(set (match_operand:DI 0 "general_operand")
191 (match_operand:DI 1 "general_operand"))]
192 "TARGET_V850E3V5_UP"
193 {
194 /* One of the ops has to be in a register or 0. */
195 if (!register_operand (operand0, DImode)
196 && !register_operand (operand1, DImode))
197 operands[1] = copy_to_mode_reg (DImode, operand1);
198
199 if (register_operand (operand0, DImode)
200 && (CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])))
201 {
202 int i;
203
204 for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
205 emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
206 simplify_gen_subreg (SImode, operands[1], DImode, i));
207 DONE;
208 }
209 }
210 )
211
212 (define_insn "*movdi_internal"
213 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,e!r,m")
214 (match_operand:DI 1 "nonimmediate_operand" "r,m,e!r"))]
215 "TARGET_V850E3V5_UP
216 || (register_operand (operands[0], DImode) && register_operand (operands[1], DImode))"
217 { return v850_gen_movdi (operands); }
218 [(set_attr "length" "4,12,12")
219 (set_attr "cc" "none_0hit")
220 (set_attr "type" "other,load,store")]
221 )
222
183 ;; movqi 223 ;; movqi
184 224
185 (define_expand "movqi" 225 (define_expand "movqi"
186 [(set (match_operand:QI 0 "general_operand" "") 226 [(set (match_operand:QI 0 "general_operand" "")
187 (match_operand:QI 1 "general_operand" ""))] 227 (match_operand:QI 1 "general_operand" ""))]
188 "" 228 ""
189 " 229 {
190 { 230 /* One of the ops has to be in a register or 0 */
191 /* One of the ops has to be in a register or 0 */ 231 if (!register_operand (operand0, QImode)
192 if (!register_operand (operand0, QImode) 232 && !reg_or_0_operand (operand1, QImode))
193 && !reg_or_0_operand (operand1, QImode)) 233 operands[1] = copy_to_mode_reg (QImode, operand1);
194 operands[1] = copy_to_mode_reg (QImode, operand1); 234 })
195 }")
196 235
197 (define_insn "*movqi_internal" 236 (define_insn "*movqi_internal"
198 [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m") 237 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m")
199 (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] 238 (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
200 "register_operand (operands[0], QImode) 239 "register_operand (operands[0], QImode)
201 || reg_or_0_operand (operands[1], QImode)" 240 || reg_or_0_operand (operands[1], QImode)"
202 "* return output_move_single (operands);" 241 {
242 return output_move_single (operands);
243 }
203 [(set_attr "length" "2,4,2,2,4,4,4") 244 [(set_attr "length" "2,4,2,2,4,4,4")
204 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 245 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
205 (set_attr "type" "other,other,load,other,load,store,store")]) 246 (set_attr "type" "other,other,load,other,load,store,store")])
206 247
207 ;; movhi 248 ;; movhi
208 249
209 (define_expand "movhi" 250 (define_expand "movhi"
210 [(set (match_operand:HI 0 "general_operand" "") 251 [(set (match_operand:HI 0 "general_operand" "")
211 (match_operand:HI 1 "general_operand" ""))] 252 (match_operand:HI 1 "general_operand" ""))]
212 "" 253 ""
213 "
214 { 254 {
215 /* One of the ops has to be in a register or 0 */ 255 /* One of the ops has to be in a register or 0 */
216 if (!register_operand (operand0, HImode) 256 if (!register_operand (operand0, HImode)
217 && !reg_or_0_operand (operand1, HImode)) 257 && !reg_or_0_operand (operand1, HImode))
218 operands[1] = copy_to_mode_reg (HImode, operand1); 258 operands[1] = copy_to_mode_reg (HImode, operand1);
219 }") 259 })
220 260
221 (define_insn "*movhi_internal" 261 (define_insn "*movhi_internal"
222 [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m") 262 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m")
223 (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] 263 (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
224 "register_operand (operands[0], HImode) 264 "register_operand (operands[0], HImode)
225 || reg_or_0_operand (operands[1], HImode)" 265 || reg_or_0_operand (operands[1], HImode)"
226 "* return output_move_single (operands);" 266 {
267 return output_move_single (operands);
268 }
227 [(set_attr "length" "2,4,2,2,4,4,4") 269 [(set_attr "length" "2,4,2,2,4,4,4")
228 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 270 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
229 (set_attr "type" "other,other,load,other,load,store,store")]) 271 (set_attr "type" "other,other,load,other,load,store,store")])
230 272
231 ;; movsi and helpers 273 ;; movsi and helpers
232 274
233 (define_insn "*movsi_high" 275 (define_insn "*movsi_high"
234 [(set (match_operand:SI 0 "register_operand" "=r") 276 [(set (match_operand:SI 0 "register_operand" "=r")
235 (high:SI (match_operand 1 "" "")))] 277 (high:SI (match_operand 1 "immediate_operand" "i")))]
236 "" 278 ""
237 "movhi hi(%1),%.,%0" 279 "movhi hi(%1),%.,%0"
238 [(set_attr "length" "4") 280 [(set_attr "length" "4")
239 (set_attr "cc" "none_0hit") 281 (set_attr "cc" "none_0hit")
240 (set_attr "type" "other")]) 282 (set_attr "type" "other")])
251 293
252 (define_expand "movsi" 294 (define_expand "movsi"
253 [(set (match_operand:SI 0 "general_operand" "") 295 [(set (match_operand:SI 0 "general_operand" "")
254 (match_operand:SI 1 "general_operand" ""))] 296 (match_operand:SI 1 "general_operand" ""))]
255 "" 297 ""
256 " 298 {
257 { 299 /* One of the ops has to be in a register or 0 */
258 /* One of the ops has to be in a register or 0 */ 300 if (!register_operand (operand0, SImode)
259 if (!register_operand (operand0, SImode) 301 && !reg_or_0_operand (operand1, SImode))
260 && !reg_or_0_operand (operand1, SImode)) 302 operands[1] = copy_to_mode_reg (SImode, operand1);
261 operands[1] = copy_to_mode_reg (SImode, operand1); 303
262 304 /* Some constants, as well as symbolic operands
263 /* Some constants, as well as symbolic operands 305 must be done with HIGH & LO_SUM patterns. */
264 must be done with HIGH & LO_SUM patterns. */ 306 if (CONSTANT_P (operands[1])
265 if (CONSTANT_P (operands[1]) 307 && GET_CODE (operands[1]) != HIGH
266 && GET_CODE (operands[1]) != HIGH 308 && ! (TARGET_V850E_UP)
267 && ! (TARGET_V850E || TARGET_V850E2_ALL) 309 && !special_symbolref_operand (operands[1], VOIDmode)
268 && !special_symbolref_operand (operands[1], VOIDmode) 310 && !(GET_CODE (operands[1]) == CONST_INT
269 && !(GET_CODE (operands[1]) == CONST_INT 311 && (CONST_OK_FOR_J (INTVAL (operands[1]))
270 && (CONST_OK_FOR_J (INTVAL (operands[1])) 312 || CONST_OK_FOR_K (INTVAL (operands[1]))
271 || CONST_OK_FOR_K (INTVAL (operands[1])) 313 || CONST_OK_FOR_L (INTVAL (operands[1])))))
272 || CONST_OK_FOR_L (INTVAL (operands[1]))))) 314 {
273 { 315 rtx temp;
274 rtx temp; 316
275 317 if (reload_in_progress || reload_completed)
276 if (reload_in_progress || reload_completed) 318 temp = operands[0];
277 temp = operands[0]; 319 else
278 else 320 temp = gen_reg_rtx (SImode);
279 temp = gen_reg_rtx (SImode); 321
280 322 emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (SImode, operand1)));
281 emit_insn (gen_rtx_SET (SImode, temp, 323 emit_insn (gen_rtx_SET (operand0,
282 gen_rtx_HIGH (SImode, operand1))); 324 gen_rtx_LO_SUM (SImode, temp, operand1)));
283 emit_insn (gen_rtx_SET (SImode, operand0, 325 DONE;
284 gen_rtx_LO_SUM (SImode, temp, operand1))); 326 }
285 DONE; 327 })
286 }
287 }")
288 328
289 ;; This is the same as the following pattern, except that it includes 329 ;; This is the same as the following pattern, except that it includes
290 ;; support for arbitrary 32-bit immediates. 330 ;; support for arbitrary 32-bit immediates.
291 331
292 ;; ??? This always loads addresses using hilo. If the only use of this address 332 ;; ??? This always loads addresses using hilo. If the only use of this address
293 ;; was in a load/store, then we would get smaller code if we only loaded the 333 ;; was in a load/store, then we would get smaller code if we only loaded the
294 ;; upper part with hi, and then put the lower part in the load/store insn. 334 ;; upper part with hi, and then put the lower part in the load/store insn.
295 335
296 (define_insn "*movsi_internal_v850e" 336 (define_insn "*movsi_internal_v850e"
297 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r") 337 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m,r")
298 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))] 338 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
299 "(TARGET_V850E || TARGET_V850E2_ALL) 339 "(TARGET_V850E_UP)
300 && (register_operand (operands[0], SImode) 340 && (register_operand (operands[0], SImode)
301 || reg_or_0_operand (operands[1], SImode))" 341 || reg_or_0_operand (operands[1], SImode))"
302 "* return output_move_single (operands);" 342 {
343 return output_move_single (operands);
344 }
303 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6") 345 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
304 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 346 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
305 (set_attr "type" "other,other,other,load,other,load,other,store,store,other")]) 347 (set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
306 348
307 (define_insn "*movsi_internal" 349 (define_insn "*movsi_internal"
308 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m") 350 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m")
309 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))] 351 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
310 "register_operand (operands[0], SImode) 352 "register_operand (operands[0], SImode)
311 || reg_or_0_operand (operands[1], SImode)" 353 || reg_or_0_operand (operands[1], SImode)"
312 "* return output_move_single (operands);" 354 {
355 return output_move_single (operands);
356 }
313 [(set_attr "length" "2,4,4,2,2,4,4,4,4") 357 [(set_attr "length" "2,4,4,2,2,4,4,4,4")
314 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 358 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
315 (set_attr "type" "other,other,other,load,other,load,store,store,other")]) 359 (set_attr "type" "other,other,other,load,other,load,store,store,other")])
316 360
317 (define_insn "*movsf_internal" 361 (define_insn "*movsf_internal"
318 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r") 362 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,Q,r,m,m,r")
319 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))] 363 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
320 "register_operand (operands[0], SFmode) 364 "register_operand (operands[0], SFmode)
321 || reg_or_0_operand (operands[1], SFmode)" 365 || reg_or_0_operand (operands[1], SFmode)"
322 "* return output_move_single (operands);" 366 {
367 return output_move_single (operands);
368 }
323 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8") 369 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
324 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 370 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
325 (set_attr "type" "other,other,other,other,load,other,load,store,store,other")]) 371 (set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
326 372
327 ;; ---------------------------------------------------------------------- 373 ;; ----------------------------------------------------------------------
378 (define_expand "cmpsi" 424 (define_expand "cmpsi"
379 [(set (cc0) 425 [(set (cc0)
380 (compare (match_operand:SI 0 "register_operand" "r,r") 426 (compare (match_operand:SI 0 "register_operand" "r,r")
381 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] 427 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
382 "" 428 ""
383 " 429 {
384 { 430 v850_compare_op0 = operands[0];
385 v850_compare_op0 = operands[0]; 431 v850_compare_op1 = operands[1];
386 v850_compare_op1 = operands[1]; 432 DONE;
387 DONE; 433 })
388 }")
389 434
390 (define_insn "cmpsi_insn" 435 (define_insn "cmpsi_insn"
391 [(set (cc0) 436 [(set (cc0)
392 (compare (match_operand:SI 0 "register_operand" "r,r") 437 (compare (match_operand:SI 0 "register_operand" "r,r")
393 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] 438 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
396 cmp %1,%0 441 cmp %1,%0
397 cmp %1,%0" 442 cmp %1,%0"
398 [(set_attr "length" "2,2") 443 [(set_attr "length" "2,2")
399 (set_attr "cc" "compare")]) 444 (set_attr "cc" "compare")])
400 445
446 (define_expand "cbranchsf4"
447 [(set (pc)
448 (if_then_else (match_operator 0 "ordered_comparison_operator"
449 [(match_operand:SF 1 "register_operand")
450 (match_operand:SF 2 "register_operand")])
451 (label_ref (match_operand 3 ""))
452 (pc)))
453 (clobber (cc0))]
454 "TARGET_USE_FPU"
455 {
456 enum rtx_code cond = GET_CODE (operands[0]);
457 machine_mode mode;
458 rtx fcc_reg;
459 rtx cc_reg;
460 rtx tmp;
461
462 v850_compare_op0 = operands[1];
463 v850_compare_op1 = operands[2];
464
465 if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT)
466 FAIL;
467
468 mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1);
469 fcc_reg = gen_rtx_REG (mode, FCC_REGNUM);
470 cc_reg = gen_rtx_REG (mode, CC_REGNUM);
471 emit_insn (gen_rtx_SET (cc_reg, fcc_reg));
472 tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx);
473 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
474 gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx);
475 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
476 DONE;
477 })
478
479 (define_insn "cstoresf4"
480 [(set (match_operand:SI 0 "register_operand" "=r")
481 (match_operator:SI 1 "ordered_comparison_operator"
482 [(match_operand:SF 2 "register_operand" "r")
483 (match_operand:SF 3 "register_operand" "r")]))]
484 "TARGET_USE_FPU"
485 {
486 if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
487 return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf nz, %0";
488 if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
489 return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf z, %0";
490 if (GET_CODE (operands[1]) == EQ)
491 return "cmpf.s eq, %z2, %z3 ; trfsr ; setf z, %0";
492 if (GET_CODE (operands[1]) == NE)
493 return "cmpf.s neq, %z2, %z3 ; trfsr ; setf nz, %0";
494 gcc_unreachable ();
495 }
496 [(set_attr "length" "12")
497 (set_attr "type" "fpu")]
498 )
499
500 (define_expand "cbranchdf4"
501 [(set (pc)
502 (if_then_else (match_operator 0 "ordered_comparison_operator"
503 [(match_operand:DF 1 "even_reg_operand")
504 (match_operand:DF 2 "even_reg_operand")])
505 (label_ref (match_operand 3 ""))
506 (pc)))
507 (clobber (cc0))]
508 "TARGET_USE_FPU"
509 {
510 enum rtx_code cond = GET_CODE (operands[0]);
511 machine_mode mode;
512 rtx fcc_reg;
513 rtx cc_reg;
514 rtx tmp;
515
516 v850_compare_op0 = operands[1];
517 v850_compare_op1 = operands[2];
518
519 if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT)
520 FAIL;
521
522 mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1);
523 fcc_reg = gen_rtx_REG (mode, FCC_REGNUM);
524 cc_reg = gen_rtx_REG (mode, CC_REGNUM);
525 emit_insn (gen_rtx_SET (cc_reg, fcc_reg));
526 tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx);
527 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
528 gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx);
529 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
530 DONE;
531 })
532
533 (define_insn "cstoredf4"
534 [(set (match_operand:SI 0 "register_operand" "=r")
535 (match_operator:SI 1 "ordered_comparison_operator"
536 [(match_operand:DF 2 "even_reg_operand" "r")
537 (match_operand:DF 3 "even_reg_operand" "r")]))]
538 "TARGET_USE_FPU"
539 {
540 if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
541 return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf nz, %0";
542 if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
543 return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf z, %0";
544 if (GET_CODE (operands[1]) == EQ)
545 return "cmpf.d eq, %z2, %z3 ; trfsr ; setf z ,%0";
546 if (GET_CODE (operands[1]) == NE)
547 return "cmpf.d neq, %z2, %z3 ; trfsr ; setf nz, %0";
548 gcc_unreachable ();
549 }
550 [(set_attr "length" "12")
551 (set_attr "type" "fpu")]
552 )
553
401 (define_expand "cmpsf" 554 (define_expand "cmpsf"
402 [(set (reg:CC CC_REGNUM) 555 [(set (reg:CC CC_REGNUM)
403 (compare (match_operand:SF 0 "register_operand" "r") 556 (compare (match_operand:SF 0 "register_operand" "r")
404 (match_operand:SF 1 "register_operand" "r")))] 557 (match_operand:SF 1 "register_operand" "r")))]
405 "TARGET_V850E2V3" 558 "TARGET_USE_FPU"
406 " 559 {
407 { 560 v850_compare_op0 = operands[0];
408 v850_compare_op0 = operands[0]; 561 v850_compare_op1 = operands[1];
409 v850_compare_op1 = operands[1]; 562 DONE;
410 DONE; 563 })
411 }")
412 564
413 (define_expand "cmpdf" 565 (define_expand "cmpdf"
414 [(set (reg:CC CC_REGNUM) 566 [(set (reg:CC CC_REGNUM)
415 (compare (match_operand:DF 0 "even_reg_operand" "r") 567 (compare (match_operand:DF 0 "even_reg_operand" "r")
416 (match_operand:DF 1 "even_reg_operand" "r")))] 568 (match_operand:DF 1 "even_reg_operand" "r")))]
417 "TARGET_V850E2V3" 569 "TARGET_USE_FPU"
418 " 570 {
419 { 571 v850_compare_op0 = operands[0];
420 v850_compare_op0 = operands[0]; 572 v850_compare_op1 = operands[1];
421 v850_compare_op1 = operands[1]; 573 DONE;
422 DONE; 574 })
423 }")
424 575
425 ;; ---------------------------------------------------------------------- 576 ;; ----------------------------------------------------------------------
426 ;; ADD INSTRUCTIONS 577 ;; ADD INSTRUCTIONS
427 ;; ---------------------------------------------------------------------- 578 ;; ----------------------------------------------------------------------
428 579
473 [(set (match_operand:SI 0 "register_operand" "") 624 [(set (match_operand:SI 0 "register_operand" "")
474 (mult:SI 625 (mult:SI
475 (sign_extend:SI (match_operand:HI 1 "register_operand" "")) 626 (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
476 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))] 627 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
477 "" 628 ""
478 "if (GET_CODE (operands[2]) == CONST_INT) 629 {
479 { 630 if (GET_CODE (operands[2]) == CONST_INT)
480 emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2])); 631 {
481 DONE; 632 emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
482 }") 633 DONE;
634 }
635 })
483 636
484 (define_insn "*mulhisi3_internal1" 637 (define_insn "*mulhisi3_internal1"
485 [(set (match_operand:SI 0 "register_operand" "=r") 638 [(set (match_operand:SI 0 "register_operand" "=r")
486 (mult:SI 639 (mult:SI
487 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) 640 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
517 670
518 (define_insn "mulsi3" 671 (define_insn "mulsi3"
519 [(set (match_operand:SI 0 "register_operand" "=r") 672 [(set (match_operand:SI 0 "register_operand" "=r")
520 (mult:SI (match_operand:SI 1 "register_operand" "%0") 673 (mult:SI (match_operand:SI 1 "register_operand" "%0")
521 (match_operand:SI 2 "reg_or_int9_operand" "rO")))] 674 (match_operand:SI 2 "reg_or_int9_operand" "rO")))]
522 "(TARGET_V850E || TARGET_V850E2_ALL)" 675 "(TARGET_V850E_UP)"
523 "mul %2,%1,%." 676 "mul %2,%1,%."
524 [(set_attr "length" "4") 677 [(set_attr "length" "4")
525 (set_attr "cc" "none_0hit") 678 (set_attr "cc" "none_0hit")
526 (set_attr "type" "mult")]) 679 (set_attr "type" "mult")])
527 680
541 (match_operand:SI 2 "register_operand" "r"))) 694 (match_operand:SI 2 "register_operand" "r")))
542 (set (match_operand:SI 3 "register_operand" "=r") 695 (set (match_operand:SI 3 "register_operand" "=r")
543 (mod:SI (match_dup 1) 696 (mod:SI (match_dup 1)
544 (match_dup 2))) 697 (match_dup 2)))
545 (clobber (reg:CC CC_REGNUM))] 698 (clobber (reg:CC CC_REGNUM))]
546 "TARGET_V850E" 699 "TARGET_V850E_UP"
547 "div %2,%0,%3" 700 {
701 if (TARGET_V850E2_UP)
702 return "divq %2,%0,%3";
703 else
704 return "div %2,%0,%3";
705 }
548 [(set_attr "length" "4") 706 [(set_attr "length" "4")
549 (set_attr "cc" "clobber") 707 (set_attr "cc" "clobber")
550 (set_attr "type" "div")]) 708 (set_attr "type" "div")])
551 709
552 (define_insn "udivmodsi4" 710 (define_insn "udivmodsi4"
555 (match_operand:SI 2 "register_operand" "r"))) 713 (match_operand:SI 2 "register_operand" "r")))
556 (set (match_operand:SI 3 "register_operand" "=r") 714 (set (match_operand:SI 3 "register_operand" "=r")
557 (umod:SI (match_dup 1) 715 (umod:SI (match_dup 1)
558 (match_dup 2))) 716 (match_dup 2)))
559 (clobber (reg:CC CC_REGNUM))] 717 (clobber (reg:CC CC_REGNUM))]
560 "TARGET_V850E" 718 "TARGET_V850E_UP"
561 "divu %2,%0,%3" 719 {
720 if (TARGET_V850E2_UP)
721 return "divqu %2,%0,%3";
722 else
723 return "divu %2,%0,%3";
724 }
562 [(set_attr "length" "4") 725 [(set_attr "length" "4")
563 (set_attr "cc" "clobber") 726 (set_attr "cc" "clobber")
564 (set_attr "type" "div")]) 727 (set_attr "type" "div")])
565 728
566 ;; ??? There is a 2 byte instruction for generating only the quotient. 729 ;; ??? There is a 2 byte instruction for generating only the quotient.
572 (match_operand:HI 2 "register_operand" "r"))) 735 (match_operand:HI 2 "register_operand" "r")))
573 (set (match_operand:HI 3 "register_operand" "=r") 736 (set (match_operand:HI 3 "register_operand" "=r")
574 (mod:HI (match_dup 1) 737 (mod:HI (match_dup 1)
575 (match_dup 2))) 738 (match_dup 2)))
576 (clobber (reg:CC CC_REGNUM))] 739 (clobber (reg:CC CC_REGNUM))]
577 "TARGET_V850E" 740 "TARGET_V850E_UP"
578 "divh %2,%0,%3" 741 "divh %2,%0,%3"
579 [(set_attr "length" "4") 742 [(set_attr "length" "4")
580 (set_attr "cc" "clobber") 743 (set_attr "cc" "clobber")
581 (set_attr "type" "div")]) 744 (set_attr "type" "div")])
582 745
589 (match_operand:HI 2 "register_operand" "r"))) 752 (match_operand:HI 2 "register_operand" "r")))
590 (set (match_operand:HI 3 "register_operand" "=r") 753 (set (match_operand:HI 3 "register_operand" "=r")
591 (umod:HI (match_dup 1) 754 (umod:HI (match_dup 1)
592 (match_dup 2))) 755 (match_dup 2)))
593 (clobber (reg:CC CC_REGNUM))] 756 (clobber (reg:CC CC_REGNUM))]
594 "TARGET_V850E" 757 "TARGET_V850E_UP"
595 "zxh %0 ; divhu %2,%0,%3" 758 "zxh %0 ; divhu %2,%0,%3"
596 [(set_attr "length" "4") 759 [(set_attr "length" "4")
597 (set_attr "cc" "clobber") 760 (set_attr "cc" "clobber")
598 (set_attr "type" "div")]) 761 (set_attr "type" "div")])
599 762
606 (subreg:QI 769 (subreg:QI
607 (and:SI (subreg:SI (match_dup 0) 0) 770 (and:SI (subreg:SI (match_dup 0) 0)
608 (match_operand:QI 1 "not_power_of_two_operand" "")) 0)) 771 (match_operand:QI 1 "not_power_of_two_operand" "")) 0))
609 (clobber (reg:CC CC_REGNUM))] 772 (clobber (reg:CC CC_REGNUM))]
610 "" 773 ""
611 "*
612 { 774 {
613 rtx xoperands[2]; 775 rtx xoperands[2];
614 xoperands[0] = operands[0]; 776 xoperands[0] = operands[0];
615 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff); 777 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
616 output_asm_insn (\"clr1 %M1,%0\", xoperands); 778 output_asm_insn ("clr1 %M1,%0", xoperands);
617 return \"\"; 779 return "";
618 }" 780 }
619 [(set_attr "length" "4") 781 [(set_attr "length" "4")
620 (set_attr "cc" "clobber") 782 (set_attr "cc" "clobber")
621 (set_attr "type" "bit1")]) 783 (set_attr "type" "bit1")])
622 784
623 (define_insn "*v850_clr1_2" 785 (define_insn "*v850_clr1_2"
625 (subreg:HI 787 (subreg:HI
626 (and:SI (subreg:SI (match_dup 0) 0) 788 (and:SI (subreg:SI (match_dup 0) 0)
627 (match_operand:HI 1 "not_power_of_two_operand" "")) 0)) 789 (match_operand:HI 1 "not_power_of_two_operand" "")) 0))
628 (clobber (reg:CC CC_REGNUM))] 790 (clobber (reg:CC CC_REGNUM))]
629 "" 791 ""
630 "*
631 { 792 {
632 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff); 793 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
633 794
634 rtx xoperands[2]; 795 rtx xoperands[2];
635 xoperands[0] = gen_rtx_MEM (QImode, 796 xoperands[0] = gen_rtx_MEM (QImode,
636 plus_constant (XEXP (operands[0], 0), log2 / 8)); 797 plus_constant (Pmode, XEXP (operands[0], 0),
798 log2 / 8));
637 xoperands[1] = GEN_INT (log2 % 8); 799 xoperands[1] = GEN_INT (log2 % 8);
638 output_asm_insn (\"clr1 %1,%0\", xoperands); 800 output_asm_insn ("clr1 %1,%0", xoperands);
639 return \"\"; 801 return "";
640 }" 802 }
641 [(set_attr "length" "4") 803 [(set_attr "length" "4")
642 (set_attr "cc" "clobber") 804 (set_attr "cc" "clobber")
643 (set_attr "type" "bit1")]) 805 (set_attr "type" "bit1")])
644 806
645 (define_insn "*v850_clr1_3" 807 (define_insn "*v850_clr1_3"
646 [(set (match_operand:SI 0 "indirect_operand" "=m") 808 [(set (match_operand:SI 0 "indirect_operand" "=m")
647 (and:SI (match_dup 0) 809 (and:SI (match_dup 0)
648 (match_operand:SI 1 "not_power_of_two_operand" ""))) 810 (match_operand:SI 1 "not_power_of_two_operand" "")))
649 (clobber (reg:CC CC_REGNUM))] 811 (clobber (reg:CC CC_REGNUM))]
650 "" 812 ""
651 "*
652 { 813 {
653 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff); 814 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
654 815
655 rtx xoperands[2]; 816 rtx xoperands[2];
656 xoperands[0] = gen_rtx_MEM (QImode, 817 xoperands[0] = gen_rtx_MEM (QImode,
657 plus_constant (XEXP (operands[0], 0), log2 / 8)); 818 plus_constant (Pmode, XEXP (operands[0], 0),
819 log2 / 8));
658 xoperands[1] = GEN_INT (log2 % 8); 820 xoperands[1] = GEN_INT (log2 % 8);
659 output_asm_insn (\"clr1 %1,%0\", xoperands); 821 output_asm_insn ("clr1 %1,%0", xoperands);
660 return \"\"; 822 return "";
661 }" 823 }
662 [(set_attr "length" "4") 824 [(set_attr "length" "4")
663 (set_attr "cc" "clobber") 825 (set_attr "cc" "clobber")
664 (set_attr "type" "bit1")]) 826 (set_attr "type" "bit1")])
665 827
666 (define_insn "andsi3" 828 (define_insn "andsi3"
694 (define_insn "*v850_set1_2" 856 (define_insn "*v850_set1_2"
695 [(set (match_operand:HI 0 "indirect_operand" "=m") 857 [(set (match_operand:HI 0 "indirect_operand" "=m")
696 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0) 858 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
697 (match_operand 1 "power_of_two_operand" "")) 0))] 859 (match_operand 1 "power_of_two_operand" "")) 0))]
698 "" 860 ""
699 "*
700 { 861 {
701 int log2 = exact_log2 (INTVAL (operands[1])); 862 int log2 = exact_log2 (INTVAL (operands[1]));
702 863
703 if (log2 < 8) 864 if (log2 < 8)
704 return \"set1 %M1,%0\"; 865 return "set1 %M1,%0";
705 else 866 else
706 { 867 {
707 rtx xoperands[2]; 868 rtx xoperands[2];
708 xoperands[0] = gen_rtx_MEM (QImode, 869 xoperands[0] = gen_rtx_MEM (QImode,
709 plus_constant (XEXP (operands[0], 0), 870 plus_constant (Pmode, XEXP (operands[0], 0),
710 log2 / 8)); 871 log2 / 8));
711 xoperands[1] = GEN_INT (log2 % 8); 872 xoperands[1] = GEN_INT (log2 % 8);
712 output_asm_insn (\"set1 %1,%0\", xoperands); 873 output_asm_insn ("set1 %1,%0", xoperands);
713 } 874 }
714 return \"\"; 875 return "";
715 }" 876 }
716 [(set_attr "length" "4") 877 [(set_attr "length" "4")
717 (set_attr "cc" "clobber") 878 (set_attr "cc" "clobber")
718 (set_attr "type" "bit1")]) 879 (set_attr "type" "bit1")])
719 880
720 (define_insn "*v850_set1_3" 881 (define_insn "*v850_set1_3"
721 [(set (match_operand:SI 0 "indirect_operand" "=m") 882 [(set (match_operand:SI 0 "indirect_operand" "=m")
722 (ior:SI (match_dup 0) 883 (ior:SI (match_dup 0)
723 (match_operand 1 "power_of_two_operand" ""))) 884 (match_operand 1 "power_of_two_operand" "")))
724 (clobber (reg:CC CC_REGNUM))] 885 (clobber (reg:CC CC_REGNUM))]
725 "" 886 ""
726 "*
727 { 887 {
728 int log2 = exact_log2 (INTVAL (operands[1])); 888 int log2 = exact_log2 (INTVAL (operands[1]));
729 889
730 if (log2 < 8) 890 if (log2 < 8)
731 return \"set1 %M1,%0\"; 891 return "set1 %M1,%0";
732 else 892 else
733 { 893 {
734 rtx xoperands[2]; 894 rtx xoperands[2];
735 xoperands[0] = gen_rtx_MEM (QImode, 895 xoperands[0] = gen_rtx_MEM (QImode,
736 plus_constant (XEXP (operands[0], 0), 896 plus_constant (Pmode, XEXP (operands[0], 0),
737 log2 / 8)); 897 log2 / 8));
738 xoperands[1] = GEN_INT (log2 % 8); 898 xoperands[1] = GEN_INT (log2 % 8);
739 output_asm_insn (\"set1 %1,%0\", xoperands); 899 output_asm_insn ("set1 %1,%0", xoperands);
740 } 900 }
741 return \"\"; 901 return "";
742 }" 902 }
743 [(set_attr "length" "4") 903 [(set_attr "length" "4")
744 (set_attr "cc" "clobber") 904 (set_attr "cc" "clobber")
745 (set_attr "type" "bit1")]) 905 (set_attr "type" "bit1")])
746 906
747 (define_insn "iorsi3" 907 (define_insn "iorsi3"
775 (define_insn "*v850_not1_2" 935 (define_insn "*v850_not1_2"
776 [(set (match_operand:HI 0 "indirect_operand" "=m") 936 [(set (match_operand:HI 0 "indirect_operand" "=m")
777 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0) 937 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
778 (match_operand 1 "power_of_two_operand" "")) 0))] 938 (match_operand 1 "power_of_two_operand" "")) 0))]
779 "" 939 ""
780 "*
781 { 940 {
782 int log2 = exact_log2 (INTVAL (operands[1])); 941 int log2 = exact_log2 (INTVAL (operands[1]));
783 942
784 if (log2 < 8) 943 if (log2 < 8)
785 return \"not1 %M1,%0\"; 944 return "not1 %M1,%0";
786 else 945 else
787 { 946 {
788 rtx xoperands[2]; 947 rtx xoperands[2];
789 xoperands[0] = gen_rtx_MEM (QImode, 948 xoperands[0] = gen_rtx_MEM (QImode,
790 plus_constant (XEXP (operands[0], 0), 949 plus_constant (Pmode, XEXP (operands[0], 0),
791 log2 / 8)); 950 log2 / 8));
792 xoperands[1] = GEN_INT (log2 % 8); 951 xoperands[1] = GEN_INT (log2 % 8);
793 output_asm_insn (\"not1 %1,%0\", xoperands); 952 output_asm_insn ("not1 %1,%0", xoperands);
794 } 953 }
795 return \"\"; 954 return "";
796 }" 955 }
797 [(set_attr "length" "4") 956 [(set_attr "length" "4")
798 (set_attr "cc" "clobber") 957 (set_attr "cc" "clobber")
799 (set_attr "type" "bit1")]) 958 (set_attr "type" "bit1")])
800 959
801 (define_insn "*v850_not1_3" 960 (define_insn "*v850_not1_3"
802 [(set (match_operand:SI 0 "indirect_operand" "=m") 961 [(set (match_operand:SI 0 "indirect_operand" "=m")
803 (xor:SI (match_dup 0) 962 (xor:SI (match_dup 0)
804 (match_operand 1 "power_of_two_operand" ""))) 963 (match_operand 1 "power_of_two_operand" "")))
805 (clobber (reg:CC CC_REGNUM))] 964 (clobber (reg:CC CC_REGNUM))]
806 "" 965 ""
807 "*
808 { 966 {
809 int log2 = exact_log2 (INTVAL (operands[1])); 967 int log2 = exact_log2 (INTVAL (operands[1]));
810 968
811 if (log2 < 8) 969 if (log2 < 8)
812 return \"not1 %M1,%0\"; 970 return "not1 %M1,%0";
813 else 971 else
814 { 972 {
815 rtx xoperands[2]; 973 rtx xoperands[2];
816 xoperands[0] = gen_rtx_MEM (QImode, 974 xoperands[0] = gen_rtx_MEM (QImode,
817 plus_constant (XEXP (operands[0], 0), 975 plus_constant (Pmode, XEXP (operands[0], 0),
818 log2 / 8)); 976 log2 / 8));
819 xoperands[1] = GEN_INT (log2 % 8); 977 xoperands[1] = GEN_INT (log2 % 8);
820 output_asm_insn (\"not1 %1,%0\", xoperands); 978 output_asm_insn ("not1 %1,%0", xoperands);
821 } 979 }
822 return \"\"; 980 return "";
823 }" 981 }
824 [(set_attr "length" "4") 982 [(set_attr "length" "4")
825 (set_attr "cc" "clobber") 983 (set_attr "cc" "clobber")
826 (set_attr "type" "bit1")]) 984 (set_attr "type" "bit1")])
827 985
828 (define_insn "xorsi3" 986 (define_insn "xorsi3"
863 1021
864 ;; extv/extzv patterns would be useful, but do not get used because 1022 ;; extv/extzv patterns would be useful, but do not get used because
865 ;; optimize_bitfield_compare in fold-const usually converts single 1023 ;; optimize_bitfield_compare in fold-const usually converts single
866 ;; bit extracts into an AND with a mask. 1024 ;; bit extracts into an AND with a mask.
867 1025
1026 (define_insn "insv"
1027 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1028 (match_operand:SI 1 "immediate_operand" "n")
1029 (match_operand:SI 2 "immediate_operand" "n"))
1030 (match_operand:SI 3 "register_operand" "r"))]
1031 "TARGET_V850E3V5_UP"
1032 "bins %3, %2, %1, %0"
1033 [(set_attr "length" "4")
1034 (set_attr "cc" "set_zn")]
1035 )
1036
868 ;; ----------------------------------------------------------------- 1037 ;; -----------------------------------------------------------------
869 ;; Scc INSTRUCTIONS 1038 ;; Scc INSTRUCTIONS
870 ;; ----------------------------------------------------------------- 1039 ;; -----------------------------------------------------------------
871 1040
872 (define_insn "*setcc" 1041 (define_insn "*setcc"
873 [(set (match_operand:SI 0 "register_operand" "=r") 1042 [(set (match_operand:SI 0 "register_operand" "=r")
874 (match_operator:SI 1 "comparison_operator" 1043 (match_operator:SI 1 "comparison_operator"
875 [(cc0) (const_int 0)]))] 1044 [(cc0) (const_int 0)]))]
876 "" 1045 ""
877 "*
878 { 1046 {
879 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 1047 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
880 && (GET_CODE (operands[1]) == GT 1048 && (GET_CODE (operands[1]) == GT
881 || GET_CODE (operands[1]) == GE 1049 || GET_CODE (operands[1]) == GE
882 || GET_CODE (operands[1]) == LE 1050 || GET_CODE (operands[1]) == LE
883 || GET_CODE (operands[1]) == LT)) 1051 || GET_CODE (operands[1]) == LT))
884 return 0; 1052 return 0;
885 1053
886 return \"setf %c1,%0\"; 1054 return "setf %c1,%0";
887 }" 1055 }
888 [(set_attr "length" "4") 1056 [(set_attr "length" "4")
889 (set_attr "cc" "none_0hit")]) 1057 (set_attr "cc" "none_0hit")])
890 1058
891 (define_insn "setf_insn" 1059 (define_insn "setf_insn"
892 [(set (match_operand:SI 0 "register_operand" "=r") 1060 [(set (match_operand:SI 0 "register_operand" "=r")
898 (set_attr "cc" "none_0hit")]) 1066 (set_attr "cc" "none_0hit")])
899 1067
900 (define_insn "set_z_insn" 1068 (define_insn "set_z_insn"
901 [(set (match_operand:SI 0 "register_operand" "=r") 1069 [(set (match_operand:SI 0 "register_operand" "=r")
902 (match_operand 1 "v850_float_z_comparison_operator" ""))] 1070 (match_operand 1 "v850_float_z_comparison_operator" ""))]
903 "TARGET_V850E2V3" 1071 "TARGET_V850E2V3_UP"
904 "setf z,%0" 1072 "setf z,%0"
905 [(set_attr "length" "4") 1073 [(set_attr "length" "4")
906 (set_attr "cc" "none_0hit")]) 1074 (set_attr "cc" "none_0hit")])
907 1075
908 (define_insn "set_nz_insn" 1076 (define_insn "set_nz_insn"
909 [(set (match_operand:SI 0 "register_operand" "=r") 1077 [(set (match_operand:SI 0 "register_operand" "=r")
910 (match_operand 1 "v850_float_nz_comparison_operator" ""))] 1078 (match_operand 1 "v850_float_nz_comparison_operator" ""))]
911 "TARGET_V850E2V3" 1079 "TARGET_V850E2V3_UP"
912 "setf nz,%0" 1080 "setf nz,%0"
913 [(set_attr "length" "4") 1081 [(set_attr "length" "4")
914 (set_attr "cc" "none_0hit")]) 1082 (set_attr "cc" "none_0hit")])
915 1083
916 ;; ---------------------------------------------------------------------- 1084 ;; ----------------------------------------------------------------------
925 [(set (match_operand:SI 0 "register_operand" "=r") 1093 [(set (match_operand:SI 0 "register_operand" "=r")
926 (if_then_else:SI 1094 (if_then_else:SI
927 (match_operand 1 "comparison_operator") 1095 (match_operand 1 "comparison_operator")
928 (match_operand:SI 2 "reg_or_const_operand" "rJ") 1096 (match_operand:SI 2 "reg_or_const_operand" "rJ")
929 (match_operand:SI 3 "reg_or_const_operand" "rI")))] 1097 (match_operand:SI 3 "reg_or_const_operand" "rI")))]
930 "(TARGET_V850E || TARGET_V850E2_ALL)" 1098 "(TARGET_V850E_UP)"
931 " 1099 {
932 { 1100 /* Make sure that we have an integer comparison... */
933 if ( (GET_CODE (operands[2]) == CONST_INT 1101 if (GET_MODE (XEXP (operands[1], 0)) != CCmode
934 && GET_CODE (operands[3]) == CONST_INT)) 1102 && GET_MODE (XEXP (operands[1], 0)) != SImode)
935 { 1103 FAIL;
936 int o2 = INTVAL (operands[2]); 1104
937 int o3 = INTVAL (operands[3]); 1105 if ((GET_CODE (operands[2]) == CONST_INT
938 1106 && GET_CODE (operands[3]) == CONST_INT))
939 if (o2 == 1 && o3 == 0) 1107 {
940 FAIL; /* setf */ 1108 int o2 = INTVAL (operands[2]);
941 if (o3 == 1 && o2 == 0) 1109 int o3 = INTVAL (operands[3]);
942 FAIL; /* setf */ 1110
943 if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0) 1111 if (o2 == 1 && o3 == 0)
944 FAIL; /* setf + shift */ 1112 FAIL; /* setf */
945 if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0) 1113 if (o3 == 1 && o2 == 0)
946 FAIL; /* setf + shift */ 1114 FAIL; /* setf */
947 if (o2 != 0) 1115 if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
948 operands[2] = copy_to_mode_reg (SImode, operands[2]); 1116 FAIL; /* setf + shift */
949 if (o3 !=0 ) 1117 if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
950 operands[3] = copy_to_mode_reg (SImode, operands[3]); 1118 FAIL; /* setf + shift */
951 } 1119 if (o2 != 0)
952 else 1120 operands[2] = copy_to_mode_reg (SImode, operands[2]);
953 { 1121 if (o3 !=0 )
954 if (GET_CODE (operands[2]) != REG) 1122 operands[3] = copy_to_mode_reg (SImode, operands[3]);
955 operands[2] = copy_to_mode_reg (SImode,operands[2]); 1123 }
956 if (GET_CODE (operands[3]) != REG) 1124 else
957 operands[3] = copy_to_mode_reg (SImode, operands[3]); 1125 {
958 } 1126 if (GET_CODE (operands[2]) != REG)
959 }") 1127 operands[2] = copy_to_mode_reg (SImode,operands[2]);
1128 if (GET_CODE (operands[3]) != REG)
1129 operands[3] = copy_to_mode_reg (SImode, operands[3]);
1130 }
1131 })
960 1132
961 ;; ??? Clobbering the condition codes is overkill. 1133 ;; ??? Clobbering the condition codes is overkill.
962 1134
963 ;; ??? We sometimes emit an unnecessary compare instruction because the 1135 ;; ??? We sometimes emit an unnecessary compare instruction because the
964 ;; condition codes may have already been set by an earlier instruction, 1136 ;; condition codes may have already been set by an earlier instruction,
969 (if_then_else:SI 1141 (if_then_else:SI
970 (match_operator 1 "comparison_operator" 1142 (match_operator 1 "comparison_operator"
971 [(reg:CC CC_REGNUM) (const_int 0)]) 1143 [(reg:CC CC_REGNUM) (const_int 0)])
972 (match_operand:SI 2 "reg_or_int5_operand" "rJ") 1144 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
973 (match_operand:SI 3 "reg_or_0_operand" "rI")))] 1145 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
974 "(TARGET_V850E || TARGET_V850E2_ALL)" 1146 "(TARGET_V850E_UP)"
975 "cmov %c1,%2,%z3,%0"; 1147 "cmov %c1,%2,%z3,%0";
976 [(set_attr "length" "6") 1148 [(set_attr "length" "6")
977 (set_attr "cc" "compare")]) 1149 (set_attr "cc" "compare")])
978 1150
979 (define_insn "movsicc_reversed_cc" 1151 (define_insn "movsicc_reversed_cc"
981 (if_then_else:SI 1153 (if_then_else:SI
982 (match_operator 1 "comparison_operator" 1154 (match_operator 1 "comparison_operator"
983 [(reg:CC CC_REGNUM) (const_int 0)]) 1155 [(reg:CC CC_REGNUM) (const_int 0)])
984 (match_operand:SI 2 "reg_or_0_operand" "rI") 1156 (match_operand:SI 2 "reg_or_0_operand" "rI")
985 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] 1157 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
986 "(TARGET_V850E || TARGET_V850E2_ALL)" 1158 "(TARGET_V850E_UP)"
987 "cmov %C1,%3,%z2,%0" 1159 "cmov %C1,%3,%z2,%0"
988 [(set_attr "length" "6") 1160 [(set_attr "length" "6")
989 (set_attr "cc" "compare")]) 1161 (set_attr "cc" "compare")])
990 1162
991 (define_insn "*movsicc_normal" 1163 (define_insn "*movsicc_normal"
994 (match_operator 1 "comparison_operator" 1166 (match_operator 1 "comparison_operator"
995 [(match_operand:SI 4 "register_operand" "r") 1167 [(match_operand:SI 4 "register_operand" "r")
996 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) 1168 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
997 (match_operand:SI 2 "reg_or_int5_operand" "rJ") 1169 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
998 (match_operand:SI 3 "reg_or_0_operand" "rI")))] 1170 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
999 "(TARGET_V850E || TARGET_V850E2_ALL)" 1171 "(TARGET_V850E_UP)"
1000 "cmp %5,%4 ; cmov %c1,%2,%z3,%0" 1172 "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
1001 [(set_attr "length" "6") 1173 [(set_attr "length" "6")
1002 (set_attr "cc" "clobber")]) 1174 (set_attr "cc" "clobber")])
1003 1175
1004 (define_insn "*movsicc_reversed" 1176 (define_insn "*movsicc_reversed"
1007 (match_operator 1 "comparison_operator" 1179 (match_operator 1 "comparison_operator"
1008 [(match_operand:SI 4 "register_operand" "r") 1180 [(match_operand:SI 4 "register_operand" "r")
1009 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) 1181 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
1010 (match_operand:SI 2 "reg_or_0_operand" "rI") 1182 (match_operand:SI 2 "reg_or_0_operand" "rI")
1011 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] 1183 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
1012 "(TARGET_V850E || TARGET_V850E2_ALL)" 1184 "(TARGET_V850E_UP)"
1013 "cmp %5,%4 ; cmov %C1,%3,%z2,%0" 1185 "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
1014 [(set_attr "length" "6") 1186 [(set_attr "length" "6")
1015 (set_attr "cc" "clobber")]) 1187 (set_attr "cc" "clobber")])
1016 1188
1017 (define_insn "*movsicc_tst1" 1189 (define_insn "*movsicc_tst1"
1023 (const_int 1) 1195 (const_int 1)
1024 (match_operand 3 "const_int_operand" "n")) 1196 (match_operand 3 "const_int_operand" "n"))
1025 (const_int 0)]) 1197 (const_int 0)])
1026 (match_operand:SI 4 "reg_or_int5_operand" "rJ") 1198 (match_operand:SI 4 "reg_or_int5_operand" "rJ")
1027 (match_operand:SI 5 "reg_or_0_operand" "rI")))] 1199 (match_operand:SI 5 "reg_or_0_operand" "rI")))]
1028 "(TARGET_V850E || TARGET_V850E2_ALL)" 1200 "(TARGET_V850E_UP)"
1029 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0" 1201 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
1030 [(set_attr "length" "8") 1202 [(set_attr "length" "8")
1031 (set_attr "cc" "clobber")]) 1203 (set_attr "cc" "clobber")])
1032 1204
1033 (define_insn "*movsicc_tst1_reversed" 1205 (define_insn "*movsicc_tst1_reversed"
1039 (const_int 1) 1211 (const_int 1)
1040 (match_operand 3 "const_int_operand" "n")) 1212 (match_operand 3 "const_int_operand" "n"))
1041 (const_int 0)]) 1213 (const_int 0)])
1042 (match_operand:SI 4 "reg_or_0_operand" "rI") 1214 (match_operand:SI 4 "reg_or_0_operand" "rI")
1043 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))] 1215 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
1044 "(TARGET_V850E || TARGET_V850E2_ALL)" 1216 "(TARGET_V850E_UP)"
1045 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0" 1217 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
1046 [(set_attr "length" "8") 1218 [(set_attr "length" "8")
1047 (set_attr "cc" "clobber")]) 1219 (set_attr "cc" "clobber")])
1048 1220
1049 ;; Matching for sasf requires combining 4 instructions, so we provide a 1221 ;; Matching for sasf requires combining 4 instructions, so we provide a
1058 [(match_operand:SI 3 "register_operand" "r") 1230 [(match_operand:SI 3 "register_operand" "r")
1059 (match_operand:SI 4 "reg_or_int5_operand" "rJ")]) 1231 (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
1060 (ashift:SI (match_operand:SI 2 "register_operand" "0") 1232 (ashift:SI (match_operand:SI 2 "register_operand" "0")
1061 (const_int 1)))) 1233 (const_int 1))))
1062 (clobber (reg:CC CC_REGNUM))] 1234 (clobber (reg:CC CC_REGNUM))]
1063 "(TARGET_V850E || TARGET_V850E2_ALL)" 1235 "(TARGET_V850E_UP)"
1064 "cmp %4,%3 ; sasf %c1,%0" 1236 "cmp %4,%3 ; sasf %c1,%0"
1065 [(set_attr "length" "6") 1237 [(set_attr "length" "6")
1066 (set_attr "cc" "clobber")]) 1238 (set_attr "cc" "clobber")])
1067 1239
1068 (define_split 1240 (define_split
1072 [(match_operand:SI 4 "register_operand" "") 1244 [(match_operand:SI 4 "register_operand" "")
1073 (match_operand:SI 5 "reg_or_int5_operand" "")]) 1245 (match_operand:SI 5 "reg_or_int5_operand" "")])
1074 (match_operand:SI 2 "const_int_operand" "") 1246 (match_operand:SI 2 "const_int_operand" "")
1075 (match_operand:SI 3 "const_int_operand" ""))) 1247 (match_operand:SI 3 "const_int_operand" "")))
1076 (clobber (reg:CC CC_REGNUM))] 1248 (clobber (reg:CC CC_REGNUM))]
1077 "(TARGET_V850E || TARGET_V850E2_ALL) 1249 "(TARGET_V850E_UP)
1078 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1) 1250 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
1079 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1) 1251 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
1080 && (GET_CODE (operands[5]) == CONST_INT 1252 && (GET_CODE (operands[5]) == CONST_INT
1081 || REGNO (operands[0]) != REGNO (operands[5])) 1253 || REGNO (operands[0]) != REGNO (operands[5]))
1082 && REGNO (operands[0]) != REGNO (operands[4])" 1254 && REGNO (operands[0]) != REGNO (operands[4])"
1083 [(set (match_dup 0) (match_dup 6)) 1255 [(set (match_dup 0) (match_dup 6))
1084 (parallel [(set (match_dup 0) 1256 (parallel [(set (match_dup 0)
1085 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)]) 1257 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
1086 (ashift:SI (match_dup 0) (const_int 1)))) 1258 (ashift:SI (match_dup 0) (const_int 1))))
1087 (clobber (reg:CC CC_REGNUM))])] 1259 (clobber (reg:CC CC_REGNUM))])]
1088 " 1260 {
1089 { 1261 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
1090 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); 1262 if (INTVAL (operands[2]) & 0x1)
1091 if (INTVAL (operands[2]) & 0x1) 1263 operands[7] = operands[1];
1092 operands[7] = operands[1]; 1264 else
1093 else 1265 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
1094 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), 1266 GET_MODE (operands[1]),
1095 GET_MODE (operands[1]), 1267 XEXP (operands[1], 0), XEXP (operands[1], 1));
1096 XEXP (operands[1], 0), XEXP (operands[1], 1)); 1268 })
1097 }")
1098 1269
1099 ;; --------------------------------------------------------------------- 1270 ;; ---------------------------------------------------------------------
1100 ;; BYTE SWAP INSTRUCTIONS 1271 ;; BYTE SWAP INSTRUCTIONS
1101 ;; --------------------------------------------------------------------- 1272 ;; ---------------------------------------------------------------------
1102 (define_expand "rotlhi3" 1273 (define_expand "rotlhi3"
1103 [(parallel [(set (match_operand:HI 0 "register_operand" "") 1274 [(parallel [(set (match_operand:HI 0 "register_operand" "")
1104 (rotate:HI (match_operand:HI 1 "register_operand" "") 1275 (rotate:HI (match_operand:HI 1 "register_operand" "")
1105 (match_operand:HI 2 "const_int_operand" ""))) 1276 (match_operand:HI 2 "const_int_operand" "")))
1106 (clobber (reg:CC CC_REGNUM))])] 1277 (clobber (reg:CC CC_REGNUM))])]
1107 "(TARGET_V850E || TARGET_V850E2_ALL)" 1278 "(TARGET_V850E_UP)"
1108 " 1279 {
1109 { 1280 if (INTVAL (operands[2]) != 8)
1110 if (INTVAL (operands[2]) != 8) 1281 FAIL;
1111 FAIL; 1282 })
1112 }")
1113 1283
1114 (define_insn "*rotlhi3_8" 1284 (define_insn "*rotlhi3_8"
1115 [(set (match_operand:HI 0 "register_operand" "=r") 1285 [(set (match_operand:HI 0 "register_operand" "=r")
1116 (rotate:HI (match_operand:HI 1 "register_operand" "r") 1286 (rotate:HI (match_operand:HI 1 "register_operand" "r")
1117 (const_int 8))) 1287 (const_int 8)))
1118 (clobber (reg:CC CC_REGNUM))] 1288 (clobber (reg:CC CC_REGNUM))]
1119 "(TARGET_V850E || TARGET_V850E2_ALL)" 1289 "(TARGET_V850E_UP)"
1120 "bsh %1,%0" 1290 "bsh %1,%0"
1121 [(set_attr "length" "4") 1291 [(set_attr "length" "4")
1122 (set_attr "cc" "clobber")]) 1292 (set_attr "cc" "clobber")])
1123 1293
1124 (define_expand "rotlsi3" 1294 (define_expand "rotlsi3"
1125 [(parallel [(set (match_operand:SI 0 "register_operand" "") 1295 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1126 (rotate:SI (match_operand:SI 1 "register_operand" "") 1296 (rotate:SI (match_operand:SI 1 "register_operand" "")
1127 (match_operand:SI 2 "const_int_operand" ""))) 1297 (match_operand:SI 2 "const_int_operand" "")))
1128 (clobber (reg:CC CC_REGNUM))])] 1298 (clobber (reg:CC CC_REGNUM))])]
1129 "(TARGET_V850E || TARGET_V850E2_ALL)" 1299 "(TARGET_V850E_UP)"
1130 " 1300 {
1131 { 1301 if (INTVAL (operands[2]) != 16)
1132 if (INTVAL (operands[2]) != 16) 1302 FAIL;
1133 FAIL; 1303 })
1134 }") 1304
1305 (define_insn "rotlsi3_a"
1306 [(set (match_operand:SI 0 "register_operand" "=r")
1307 (match_operator:SI 4 "ior_operator"
1308 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
1309 (match_operand:SI 2 "const_int_operand" "n"))
1310 (lshiftrt:SI (match_dup 1)
1311 (match_operand:SI 3 "const_int_operand" "n"))]))]
1312 "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)"
1313 "rotl %2, %1, %0"
1314 [(set_attr "length" "4")
1315 (set_attr "cc" "set_zn")]
1316 )
1317
1318 (define_insn "rotlsi3_b"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (match_operator:SI 4 "ior_operator"
1321 [(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1322 (match_operand:SI 3 "const_int_operand" "n"))
1323 (ashift:SI (match_dup 1)
1324 (match_operand:SI 2 "const_int_operand" "n"))]))]
1325 "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)"
1326 "rotl %2, %1, %0"
1327 [(set_attr "length" "4")
1328 (set_attr "cc" "set_zn")]
1329 )
1330
1331 (define_insn "rotlsi3_v850e3v5"
1332 [(set (match_operand:SI 0 "register_operand" "=r")
1333 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1334 (match_operand:SI 2 "e3v5_shift_operand" "rn")))
1335 (clobber (reg:CC CC_REGNUM))]
1336 "TARGET_V850E3V5_UP"
1337 "rotl %2, %1, %0"
1338 [(set_attr "length" "4")
1339 (set_attr "cc" "set_zn")]
1340 )
1135 1341
1136 (define_insn "*rotlsi3_16" 1342 (define_insn "*rotlsi3_16"
1137 [(set (match_operand:SI 0 "register_operand" "=r") 1343 [(set (match_operand:SI 0 "register_operand" "=r")
1138 (rotate:SI (match_operand:SI 1 "register_operand" "r") 1344 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1139 (const_int 16))) 1345 (const_int 16)))
1140 (clobber (reg:CC CC_REGNUM))] 1346 (clobber (reg:CC CC_REGNUM))]
1141 "(TARGET_V850E || TARGET_V850E2_ALL)" 1347 "(TARGET_V850E_UP)"
1142 "hsw %1,%0" 1348 "hsw %1,%0"
1143 [(set_attr "length" "4") 1349 [(set_attr "length" "4")
1144 (set_attr "cc" "clobber")]) 1350 (set_attr "cc" "clobber")])
1145 1351
1146 ;; ---------------------------------------------------------------------- 1352 ;; ----------------------------------------------------------------------
1147 ;; JUMP INSTRUCTIONS 1353 ;; JUMP INSTRUCTIONS
1148 ;; ---------------------------------------------------------------------- 1354 ;; ----------------------------------------------------------------------
1355
1356 ;; Doloop
1357
1358 (define_expand "doloop_begin"
1359 [(use (match_operand 0 "" "")) ; loop pseudo
1360 (use (match_operand 1 "" ""))] ; doloop_end pattern
1361 "TARGET_V850E3V5_UP && TARGET_LOOP"
1362 {
1363 rtx loop_cnt = operands[0];
1364 gcc_assert (GET_MODE (loop_cnt) == SImode);
1365 emit_insn (gen_fix_loop_counter (loop_cnt));
1366 DONE;
1367 }
1368 )
1369
1370 (define_insn "fix_loop_counter"
1371 [(unspec:SI [(match_operand:SI 0 "register_operand" "+r,!m")
1372 (clobber (match_scratch:SI 1 "=X,r"))] UNSPEC_LOOP)]
1373 "TARGET_V850E3V5_UP && TARGET_LOOP"
1374 {
1375 switch (which_alternative)
1376 {
1377 case 0: return "add 1, %0 # LOOP_BEGIN";
1378 case 1: return "ld.w %0, %1; add 1, %1; st.w %1, %0 # LOOP_BEGIN";
1379 default: gcc_unreachable ();
1380 }
1381 }
1382 [(set_attr "length" "2,6")
1383 (set_attr "cc" "none")]
1384 )
1385
1386 (define_expand "doloop_end"
1387 [(use (match_operand 0 "" "")) ; loop pseudo
1388 (use (match_operand 1 "" ""))] ; label
1389 "TARGET_V850E3V5_UP && TARGET_LOOP"
1390 {
1391 rtx loop_cnt = operands[0];
1392 rtx label = operands[1];
1393
1394 if (GET_MODE (loop_cnt) != SImode)
1395 FAIL;
1396
1397 emit_jump_insn (gen_doloop_end_internal_loop (label, loop_cnt));
1398 DONE;
1399 }
1400 )
1401
1402 (define_insn "doloop_end_internal_loop"
1403 [(set (pc)
1404 (if_then_else (ne (match_operand:SI 1 "register_operand" "+r,!m")
1405 (const_int 0))
1406 (label_ref (match_operand 0 "" ""))
1407 (pc)))
1408 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))
1409 (clobber (match_scratch:SI 2 "=X,r"))
1410 (clobber (reg:CC CC_REGNUM))]
1411 "TARGET_V850E3V5_UP && TARGET_LOOP"
1412 {
1413 switch (which_alternative)
1414 {
1415 case 0:
1416 if (get_attr_length (insn) == 4)
1417 return "loop %1, %0 # LOOP.1.0";
1418
1419 return "add -1, %1; bne %l0 # LOOP.1.1";
1420 case 1:
1421 return "ld.w %1, %2; add -1, %2; st.w %2, %1; bne %l0 # LOOP.2.1";
1422 default:
1423 gcc_unreachable ();
1424 }
1425 }
1426 [(set (attr "length")
1427 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1428 (const_int 65534))
1429 (const_int 4)
1430 (const_int 14)))
1431 (set_attr "cc" "none")])
1149 1432
1150 ;; Conditional jump instructions 1433 ;; Conditional jump instructions
1151 1434
1152 (define_insn "*branch_normal" 1435 (define_insn "*branch_normal"
1153 [(set (pc) 1436 [(set (pc)
1154 (if_then_else (match_operator 1 "comparison_operator" 1437 (if_then_else (match_operator 1 "comparison_operator"
1155 [(cc0) (const_int 0)]) 1438 [(cc0) (const_int 0)])
1156 (label_ref (match_operand 0 "" "")) 1439 (label_ref (match_operand 0 "" ""))
1157 (pc)))] 1440 (pc)))]
1158 "" 1441 ""
1159 "*
1160 { 1442 {
1161 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 1443 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1162 && (GET_CODE (operands[1]) == GT 1444 && (GET_CODE (operands[1]) == GT
1163 || GET_CODE (operands[1]) == GE 1445 || GET_CODE (operands[1]) == GE
1164 || GET_CODE (operands[1]) == LE 1446 || GET_CODE (operands[1]) == LE
1165 || GET_CODE (operands[1]) == LT)) 1447 || GET_CODE (operands[1]) == LT))
1166 return 0; 1448 return 0;
1167 1449
1168 if (get_attr_length (insn) == 2) 1450 if (get_attr_length (insn) == 2)
1169 return \"b%b1 %l0\"; 1451 return "b%b1 %l0";
1170 else 1452 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1171 return \"b%B1 .+6 ; jr %l0\"; 1453 return "b%b1 %l0";
1172 }" 1454 return "b%B1 .+6 ; jr %l0";
1455 }
1173 [(set (attr "length") 1456 [(set (attr "length")
1174 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1457 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1175 (const_int 256)) 1458 (const_int 256))
1176 (const_int 2) 1459 (const_int 2)
1177 (const_int 6))) 1460 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1461 (const_int 65536))
1462 (const_int 4)
1463 (const_int 6))))
1178 (set_attr "cc" "none")]) 1464 (set_attr "cc" "none")])
1179 1465
1180 (define_insn "*branch_invert" 1466 (define_insn "*branch_invert"
1181 [(set (pc) 1467 [(set (pc)
1182 (if_then_else (match_operator 1 "comparison_operator" 1468 (if_then_else (match_operator 1 "comparison_operator"
1183 [(cc0) (const_int 0)]) 1469 [(cc0) (const_int 0)])
1184 (pc) 1470 (pc)
1185 (label_ref (match_operand 0 "" ""))))] 1471 (label_ref (match_operand 0 "" ""))))]
1186 "" 1472 ""
1187 "*
1188 { 1473 {
1189 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 1474 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1190 && (GET_CODE (operands[1]) == GT 1475 && (GET_CODE (operands[1]) == GT
1191 || GET_CODE (operands[1]) == GE 1476 || GET_CODE (operands[1]) == GE
1192 || GET_CODE (operands[1]) == LE 1477 || GET_CODE (operands[1]) == LE
1193 || GET_CODE (operands[1]) == LT)) 1478 || GET_CODE (operands[1]) == LT))
1194 return 0; 1479 return NULL;
1480
1195 if (get_attr_length (insn) == 2) 1481 if (get_attr_length (insn) == 2)
1196 return \"b%B1 %l0\"; 1482 return "b%B1 %l0";
1197 else 1483
1198 return \"b%b1 .+6 ; jr %l0\"; 1484 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1199 }" 1485 return "b%B1 %l0";
1486
1487 return "b%b1 .+6 ; jr %l0";
1488 }
1200 [(set (attr "length") 1489 [(set (attr "length")
1201 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1490 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1202 (const_int 256)) 1491 (const_int 256))
1203 (const_int 2) 1492 (const_int 2)
1204 (const_int 6))) 1493 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1494 (const_int 65536))
1495 (const_int 4)
1496 (const_int 6))))
1205 (set_attr "cc" "none")]) 1497 (set_attr "cc" "none")])
1206 1498
1207 (define_insn "branch_z_normal" 1499 (define_insn "branch_z_normal"
1208 [(set (pc) 1500 [(set (pc)
1209 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") 1501 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1210 (label_ref (match_operand 0 "" "")) 1502 (label_ref (match_operand 0 "" ""))
1211 (pc)))] 1503 (pc)))]
1212 "TARGET_V850E2V3" 1504 "TARGET_V850E2V3_UP"
1213 "*
1214 { 1505 {
1215 if (get_attr_length (insn) == 2) 1506 if (get_attr_length (insn) == 2)
1216 return \"bz %l0\"; 1507 return "bz %l0";
1217 else 1508
1218 return \"bnz 1f ; jr %l0 ; 1:\"; 1509 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1219 }" 1510 return "bz %l0";
1511
1512 return "bnz 1f ; jr %l0 ; 1:";
1513 }
1220 [(set (attr "length") 1514 [(set (attr "length")
1221 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1515 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1222 (const_int 256)) 1516 (const_int 256))
1223 (const_int 2) 1517 (const_int 2)
1224 (const_int 6))) 1518 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1519 (const_int 65536))
1520 (const_int 4)
1521 (const_int 6))))
1225 (set_attr "cc" "none")]) 1522 (set_attr "cc" "none")])
1226 1523
1227 (define_insn "*branch_z_invert" 1524 (define_insn "*branch_z_invert"
1228 [(set (pc) 1525 [(set (pc)
1229 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") 1526 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1230 (pc) 1527 (pc)
1231 (label_ref (match_operand 0 "" ""))))] 1528 (label_ref (match_operand 0 "" ""))))]
1232 "TARGET_V850E2V3" 1529 "TARGET_V850E2V3_UP"
1233 "*
1234 { 1530 {
1235 if (get_attr_length (insn) == 2) 1531 if (get_attr_length (insn) == 2)
1236 return \"bnz %l0\"; 1532 return "bnz %l0";
1237 else 1533
1238 return \"bz 1f ; jr %l0 ; 1:\"; 1534 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1239 }" 1535 return "bnz %l0";
1536
1537 return "bz 1f ; jr %l0 ; 1:";
1538 }
1240 [(set (attr "length") 1539 [(set (attr "length")
1241 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1540 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1242 (const_int 256)) 1541 (const_int 256))
1243 (const_int 2) 1542 (const_int 2)
1244 (const_int 6))) 1543 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1544 (const_int 65536))
1545 (const_int 4)
1546 (const_int 6))))
1245 (set_attr "cc" "none")]) 1547 (set_attr "cc" "none")])
1246 1548
1247 (define_insn "branch_nz_normal" 1549 (define_insn "branch_nz_normal"
1248 [(set (pc) 1550 [(set (pc)
1249 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") 1551 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1250 (label_ref (match_operand 0 "" "")) 1552 (label_ref (match_operand 0 "" ""))
1251 (pc)))] 1553 (pc)))]
1252 "TARGET_V850E2V3" 1554 "TARGET_V850E2V3_UP"
1253 "*
1254 { 1555 {
1255 if (get_attr_length (insn) == 2) 1556 if (get_attr_length (insn) == 2)
1256 return \"bnz %l0\"; 1557 return "bnz %l0";
1257 else 1558
1258 return \"bz 1f ; jr %l0 ; 1:\"; 1559 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1259 }" 1560 return "bnz %l0";
1561
1562 return "bz 1f ; jr %l0 ; 1:";
1563 }
1260 [(set (attr "length") 1564 [(set (attr "length")
1261 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1565 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1262 (const_int 256)) 1566 (const_int 256))
1263 (const_int 2) 1567 (const_int 2)
1264 (const_int 6))) 1568 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1569 (const_int 65536))
1570 (const_int 4)
1571 (const_int 6))))
1265 (set_attr "cc" "none")]) 1572 (set_attr "cc" "none")])
1266 1573
1267 (define_insn "*branch_nz_invert" 1574 (define_insn "*branch_nz_invert"
1268 [(set (pc) 1575 [(set (pc)
1269 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") 1576 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1270 (pc) 1577 (pc)
1271 (label_ref (match_operand 0 "" ""))))] 1578 (label_ref (match_operand 0 "" ""))))]
1272 "TARGET_V850E2V3" 1579 "TARGET_V850E2V3_UP"
1273 "*
1274 { 1580 {
1275 if (get_attr_length (insn) == 2) 1581 if (get_attr_length (insn) == 2)
1276 return \"bz %l0\"; 1582 return "bz %l0";
1277 else 1583
1278 return \"bnz 1f ; jr %l0 ; 1:\"; 1584 if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
1279 }" 1585 return "bz %l0";
1586
1587 return "bnz 1f ; jr %l0 ; 1:";
1588 }
1280 [(set (attr "length") 1589 [(set (attr "length")
1281 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1590 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1282 (const_int 256)) 1591 (const_int 256))
1283 (const_int 2) 1592 (const_int 2)
1284 (const_int 6))) 1593 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1594 (const_int 65536))
1595 (const_int 4)
1596 (const_int 6))))
1285 (set_attr "cc" "none")]) 1597 (set_attr "cc" "none")])
1286 1598
1287 ;; Unconditional and other jump instructions. 1599 ;; Unconditional and other jump instructions.
1288 1600
1289 (define_insn "jump" 1601 (define_insn "jump"
1290 [(set (pc) 1602 [(set (pc)
1291 (label_ref (match_operand 0 "" "")))] 1603 (label_ref (match_operand 0 "" "")))]
1292 "" 1604 ""
1293 "*
1294 { 1605 {
1295 if (get_attr_length (insn) == 2) 1606 if (get_attr_length (insn) == 2)
1296 return \"br %0\"; 1607 return "br %0";
1297 else 1608 else
1298 return \"jr %0\"; 1609 return "jr %0";
1299 }" 1610 }
1300 [(set (attr "length") 1611 [(set (attr "length")
1301 (if_then_else (lt (abs (minus (match_dup 0) (pc))) 1612 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1302 (const_int 256)) 1613 (const_int 256))
1303 (const_int 2) 1614 (const_int 2)
1304 (const_int 4))) 1615 (const_int 4)))
1326 (mem:HI 1637 (mem:HI
1327 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r") 1638 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
1328 (const_int 1)) 1639 (const_int 1))
1329 (label_ref (match_operand 1 "" ""))))) 1640 (label_ref (match_operand 1 "" "")))))
1330 (label_ref (match_dup 1))))] 1641 (label_ref (match_dup 1))))]
1331 "(TARGET_V850E || TARGET_V850E2_ALL)" 1642 "(TARGET_V850E_UP)"
1332 "switch %0" 1643 "switch %0"
1333 [(set_attr "length" "2") 1644 [(set_attr "length" "2")
1334 (set_attr "cc" "none")]) 1645 (set_attr "cc" "none")])
1335 1646
1336 (define_expand "casesi" 1647 (define_expand "casesi"
1337 [(match_operand:SI 0 "register_operand" "") 1648 [(match_operand:SI 0 "register_operand" "")
1338 (match_operand:SI 1 "register_operand" "") 1649 (match_operand:SI 1 "register_operand" "")
1339 (match_operand:SI 2 "register_operand" "") 1650 (match_operand:SI 2 "register_operand" "")
1340 (match_operand 3 "" "") (match_operand 4 "" "")] 1651 (match_operand 3 "" "") (match_operand 4 "" "")]
1341 "" 1652 ""
1342 " 1653 {
1343 { 1654 rtx reg = gen_reg_rtx (SImode);
1344 rtx reg = gen_reg_rtx (SImode); 1655 rtx tableaddress = gen_reg_rtx (SImode);
1345 rtx tableaddress = gen_reg_rtx (SImode); 1656 rtx test;
1346 rtx test; 1657 rtx mem;
1347 rtx mem; 1658
1348 1659 /* Subtract the lower bound from the index. */
1349 /* Subtract the lower bound from the index. */ 1660 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
1350 emit_insn (gen_subsi3 (reg, operands[0], operands[1])); 1661
1351 1662 /* Compare the result against the number of table entries;
1352 /* Compare the result against the number of table entries; 1663 branch to the default label if out of range of the table. */
1353 branch to the default label if out of range of the table. */ 1664 test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
1354 test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]); 1665 emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
1355 emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4])); 1666
1356 1667 /* Shift index for the table array access. */
1357 /* Shift index for the table array access. */ 1668 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
1358 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1))); 1669 /* Load the table address into a pseudo. */
1359 /* Load the table address into a pseudo. */ 1670 emit_insn (gen_movsi (tableaddress,
1360 emit_insn (gen_movsi (tableaddress, 1671 gen_rtx_LABEL_REF (Pmode, operands[3])));
1361 gen_rtx_LABEL_REF (Pmode, operands[3]))); 1672 /* Add the table address to the index. */
1362 /* Add the table address to the index. */ 1673 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1363 emit_insn (gen_addsi3 (reg, reg, tableaddress)); 1674 /* Load the table entry. */
1364 /* Load the table entry. */ 1675 mem = gen_const_mem (CASE_VECTOR_MODE, reg);
1365 mem = gen_const_mem (CASE_VECTOR_MODE, reg); 1676 if (! TARGET_BIG_SWITCH)
1366 if (! TARGET_BIG_SWITCH) 1677 {
1367 { 1678 rtx reg2 = gen_reg_rtx (HImode);
1368 rtx reg2 = gen_reg_rtx (HImode); 1679 emit_insn (gen_movhi (reg2, mem));
1369 emit_insn (gen_movhi (reg2, mem)); 1680 emit_insn (gen_extendhisi2 (reg, reg2));
1370 emit_insn (gen_extendhisi2 (reg, reg2)); 1681 }
1371 } 1682 else
1372 else 1683 emit_insn (gen_movsi (reg, mem));
1373 emit_insn (gen_movsi (reg, mem)); 1684 /* Add the table address. */
1374 /* Add the table address. */ 1685 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1375 emit_insn (gen_addsi3 (reg, reg, tableaddress)); 1686 /* Branch to the switch label. */
1376 /* Branch to the switch label. */ 1687 emit_jump_insn (gen_tablejump (reg, operands[3]));
1377 emit_jump_insn (gen_tablejump (reg, operands[3])); 1688 DONE;
1378 DONE; 1689 })
1379 }")
1380 1690
1381 ;; Call subroutine with no return value. 1691 ;; Call subroutine with no return value.
1382 1692
1383 (define_expand "call" 1693 (define_expand "call"
1384 [(call (match_operand:QI 0 "general_operand" "") 1694 [(call (match_operand:QI 0 "general_operand" "")
1385 (match_operand:SI 1 "general_operand" ""))] 1695 (match_operand:SI 1 "general_operand" ""))]
1386 "" 1696 ""
1387 " 1697 {
1388 { 1698 if (! call_address_operand (XEXP (operands[0], 0), QImode)
1389 if (! call_address_operand (XEXP (operands[0], 0), QImode) 1699 || TARGET_LONG_CALLS)
1390 || TARGET_LONG_CALLS) 1700 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1391 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); 1701 if (TARGET_LONG_CALLS)
1392 if (TARGET_LONG_CALLS) 1702 emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
1393 emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1])); 1703 else
1394 else 1704 emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
1395 emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
1396 1705
1397 DONE; 1706 DONE;
1398 }") 1707 })
1399 1708
1400 (define_insn "call_internal_short" 1709 (define_insn "call_internal_short"
1401 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) 1710 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1402 (match_operand:SI 1 "general_operand" "g,g")) 1711 (match_operand:SI 1 "general_operand" "g,g"))
1403 (clobber (reg:SI 31))] 1712 (clobber (reg:SI 31))]
1404 "! TARGET_LONG_CALLS" 1713 "! TARGET_LONG_CALLS"
1405 "@ 1714 {
1406 jarl %0,r31 1715 if (which_alternative == 1)
1407 jarl .+4,r31 ; add 4,r31 ; jmp %0" 1716 {
1717 if (TARGET_V850E3V5_UP)
1718 return "jarl [%0], r31";
1719
1720 return "jarl .+4, r31 ; add 4, r31 ; jmp %0";
1721 }
1722
1723 return "jarl %0, r31";
1724 }
1408 [(set_attr "length" "4,8") 1725 [(set_attr "length" "4,8")
1409 (set_attr "cc" "clobber,clobber")] 1726 (set_attr "cc" "clobber,clobber")]
1410 ) 1727 )
1411 1728
1412 (define_insn "call_internal_long" 1729 (define_insn "call_internal_long"
1413 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) 1730 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1414 (match_operand:SI 1 "general_operand" "g,g")) 1731 (match_operand:SI 1 "general_operand" "g,g"))
1415 (clobber (reg:SI 31))] 1732 (clobber (reg:SI 31))]
1416 "TARGET_LONG_CALLS" 1733 "TARGET_LONG_CALLS"
1417 "* 1734 {
1418 {
1419 if (which_alternative == 0) 1735 if (which_alternative == 0)
1420 { 1736 {
1421 if (GET_CODE (operands[0]) == REG) 1737 if (GET_CODE (operands[0]) == REG)
1422 return \"jarl %0,r31\"; 1738 return "jarl %0,r31";
1423 else 1739
1424 return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\"; 1740 if (TARGET_V850E3V5_UP)
1741 return "mov hilo(%0), r11 ; jarl [r11], r31";
1742
1743 return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
1425 } 1744 }
1426 else 1745
1427 return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\"; 1746 if (TARGET_V850E3V5_UP)
1428 }" 1747 return "jarl [%0], r31";
1748
1749 return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
1750 }
1429 [(set_attr "length" "16,8") 1751 [(set_attr "length" "16,8")
1430 (set_attr "cc" "clobber,clobber")] 1752 (set_attr "cc" "clobber,clobber")]
1431 ) 1753 )
1432 1754
1433 ;; Call subroutine, returning value in operand 0 1755 ;; Call subroutine, returning value in operand 0
1436 (define_expand "call_value" 1758 (define_expand "call_value"
1437 [(set (match_operand 0 "" "") 1759 [(set (match_operand 0 "" "")
1438 (call (match_operand:QI 1 "general_operand" "") 1760 (call (match_operand:QI 1 "general_operand" "")
1439 (match_operand:SI 2 "general_operand" "")))] 1761 (match_operand:SI 2 "general_operand" "")))]
1440 "" 1762 ""
1441 " 1763 {
1442 { 1764 if (! call_address_operand (XEXP (operands[1], 0), QImode)
1443 if (! call_address_operand (XEXP (operands[1], 0), QImode) 1765 || TARGET_LONG_CALLS)
1444 || TARGET_LONG_CALLS) 1766 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1445 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); 1767 if (TARGET_LONG_CALLS)
1446 if (TARGET_LONG_CALLS) 1768 emit_call_insn (gen_call_value_internal_long (operands[0],
1447 emit_call_insn (gen_call_value_internal_long (operands[0], 1769 XEXP (operands[1], 0),
1448 XEXP (operands[1], 0), 1770 operands[2]));
1449 operands[2])); 1771 else
1450 else 1772 emit_call_insn (gen_call_value_internal_short (operands[0],
1451 emit_call_insn (gen_call_value_internal_short (operands[0], 1773 XEXP (operands[1], 0),
1452 XEXP (operands[1], 0), 1774 operands[2]));
1453 operands[2])); 1775 DONE;
1454 DONE; 1776 })
1455 }")
1456 1777
1457 (define_insn "call_value_internal_short" 1778 (define_insn "call_value_internal_short"
1458 [(set (match_operand 0 "" "=r,r") 1779 [(set (match_operand 0 "" "=r,r")
1459 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r")) 1780 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1460 (match_operand:SI 2 "general_operand" "g,g"))) 1781 (match_operand:SI 2 "general_operand" "g,g")))
1461 (clobber (reg:SI 31))] 1782 (clobber (reg:SI 31))]
1462 "! TARGET_LONG_CALLS" 1783 "! TARGET_LONG_CALLS"
1463 "@ 1784 {
1464 jarl %1,r31 1785 if (which_alternative == 1)
1465 jarl .+4,r31 ; add 4,r31 ; jmp %1" 1786 {
1787 if (TARGET_V850E3V5_UP)
1788 return "jarl [%1], r31";
1789
1790 return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
1791 }
1792
1793 return "jarl %1, r31";
1794 }
1466 [(set_attr "length" "4,8") 1795 [(set_attr "length" "4,8")
1467 (set_attr "cc" "clobber,clobber")] 1796 (set_attr "cc" "clobber,clobber")]
1468 ) 1797 )
1469 1798
1470 (define_insn "call_value_internal_long" 1799 (define_insn "call_value_internal_long"
1471 [(set (match_operand 0 "" "=r,r") 1800 [(set (match_operand 0 "" "=r,r")
1472 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r")) 1801 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1473 (match_operand:SI 2 "general_operand" "g,g"))) 1802 (match_operand:SI 2 "general_operand" "g,g")))
1474 (clobber (reg:SI 31))] 1803 (clobber (reg:SI 31))]
1475 "TARGET_LONG_CALLS" 1804 "TARGET_LONG_CALLS"
1476 "* 1805 {
1477 {
1478 if (which_alternative == 0) 1806 if (which_alternative == 0)
1479 { 1807 {
1480 if (GET_CODE (operands[1]) == REG) 1808 if (GET_CODE (operands[1]) == REG)
1481 return \"jarl %1, r31\"; 1809 return "jarl %1, r31";
1482 else 1810
1483 /* Reload can generate this pattern.... */ 1811 /* Reload can generate this pattern.... */
1484 return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\"; 1812 if (TARGET_V850E3V5_UP)
1813 return "mov hilo(%1), r11 ; jarl [r11], r31";
1814
1815 return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
1485 } 1816 }
1486 else 1817
1487 return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\"; 1818 if (TARGET_V850E3V5_UP)
1488 }" 1819 return "jarl [%1], r31";
1820
1821 return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
1822 }
1489 [(set_attr "length" "16,8") 1823 [(set_attr "length" "16,8")
1490 (set_attr "cc" "clobber,clobber")] 1824 (set_attr "cc" "clobber,clobber")]
1491 ) 1825 )
1492 1826
1493 (define_insn "nop" 1827 (define_insn "nop"
1499 1833
1500 ;; ---------------------------------------------------------------------- 1834 ;; ----------------------------------------------------------------------
1501 ;; EXTEND INSTRUCTIONS 1835 ;; EXTEND INSTRUCTIONS
1502 ;; ---------------------------------------------------------------------- 1836 ;; ----------------------------------------------------------------------
1503 1837
1504 (define_insn "" 1838 (define_insn "*zero_extendhisi2_v850e"
1505 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1839 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1506 (zero_extend:SI 1840 (zero_extend:SI
1507 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m"))) 1841 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))
1508 (clobber (reg:CC CC_REGNUM))] 1842 (clobber (reg:CC CC_REGNUM))]
1509 "(TARGET_V850E || TARGET_V850E2_ALL)" 1843 "(TARGET_V850E_UP)"
1510 "@ 1844 "@
1511 zxh %0 1845 zxh %0
1512 andi 65535,%1,%0 1846 andi 65535,%1,%0
1513 sld.hu %1,%0 1847 sld.hu %1,%0
1514 ld.hu %1,%0" 1848 ld.hu %1,%0"
1515 [(set_attr "length" "2,4,2,4") 1849 [(set_attr "length" "2,4,2,4")
1516 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) 1850 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1517 1851
1518 (define_insn "zero_extendhisi2" 1852 (define_insn "*zero_extendhisi2_v850"
1519 [(set (match_operand:SI 0 "register_operand" "=r") 1853 [(set (match_operand:SI 0 "register_operand" "=r")
1520 (zero_extend:SI 1854 (zero_extend:SI
1521 (match_operand:HI 1 "register_operand" "r"))) 1855 (match_operand:HI 1 "register_operand" "r")))
1522 (clobber (reg:CC CC_REGNUM))] 1856 (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
1523 "" 1857 ""
1524 "andi 65535,%1,%0" 1858 "andi 65535,%1,%0"
1525 [(set_attr "length" "4") 1859 [(set_attr "length" "4")
1526 (set_attr "cc" "set_zn")]) 1860 (set_attr "cc" "set_zn")])
1527 1861
1528 (define_insn "" 1862 (define_expand "zero_extendhisi2"
1863 [(parallel [(set (match_operand:SI 0 "register_operand")
1864 (zero_extend:SI
1865 (match_operand:HI 1 "nonimmediate_operand")))
1866 (clobber (reg:CC CC_REGNUM))])]
1867 ""
1868 {
1869 if (! (TARGET_V850E_UP))
1870 operands[1] = force_reg (HImode, operands[1]);
1871 })
1872
1873 (define_insn "*zero_extendqisi2_v850e"
1529 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1874 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1530 (zero_extend:SI 1875 (zero_extend:SI
1531 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m"))) 1876 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))
1532 (clobber (reg:CC CC_REGNUM))] 1877 (clobber (reg:CC CC_REGNUM))]
1533 "(TARGET_V850E || TARGET_V850E2_ALL)" 1878 "(TARGET_V850E_UP)"
1534 "@ 1879 "@
1535 zxb %0 1880 zxb %0
1536 andi 255,%1,%0 1881 andi 255,%1,%0
1537 sld.bu %1,%0 1882 sld.bu %1,%0
1538 ld.bu %1,%0" 1883 ld.bu %1,%0"
1539 [(set_attr "length" "2,4,2,4") 1884 [(set_attr "length" "2,4,2,4")
1540 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) 1885 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1541 1886
1542 (define_insn "zero_extendqisi2" 1887 (define_insn "*zero_extendqisi2_v850"
1543 [(set (match_operand:SI 0 "register_operand" "=r") 1888 [(set (match_operand:SI 0 "register_operand" "=r")
1544 (zero_extend:SI 1889 (zero_extend:SI
1545 (match_operand:QI 1 "register_operand" "r"))) 1890 (match_operand:QI 1 "register_operand" "r")))
1546 (clobber (reg:CC CC_REGNUM))] 1891 (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
1547 "" 1892 ""
1548 "andi 255,%1,%0" 1893 "andi 255,%1,%0"
1549 [(set_attr "length" "4") 1894 [(set_attr "length" "4")
1550 (set_attr "cc" "set_zn")]) 1895 (set_attr "cc" "set_zn")])
1896
1897 (define_expand "zero_extendqisi2"
1898 [(parallel [(set (match_operand:SI 0 "register_operand")
1899 (zero_extend:SI
1900 (match_operand:QI 1 "nonimmediate_operand")))
1901 (clobber (reg:CC CC_REGNUM))])]
1902 ""
1903 {
1904 if (! (TARGET_V850E_UP))
1905 operands[1] = force_reg (QImode, operands[1]);
1906 })
1551 1907
1552 ;;- sign extension instructions 1908 ;;- sign extension instructions
1553 1909
1554 ;; ??? The extendhisi2 pattern should not emit shifts for v850e? 1910 ;; ??? The extendhisi2 pattern should not emit shifts for v850e?
1555 1911
1556 (define_insn "*extendhisi_insn" 1912 (define_insn "*extendhisi_insn"
1557 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1913 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1558 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m"))) 1914 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))
1559 (clobber (reg:CC CC_REGNUM))] 1915 (clobber (reg:CC CC_REGNUM))]
1560 "(TARGET_V850E || TARGET_V850E2_ALL)" 1916 "(TARGET_V850E_UP)"
1561 "@ 1917 "@
1562 sxh %0 1918 sxh %0
1563 sld.h %1,%0 1919 sld.h %1,%0
1564 ld.h %1,%0" 1920 ld.h %1,%0"
1565 [(set_attr "length" "2,2,4") 1921 [(set_attr "length" "2,2,4")
1576 (parallel [(set (match_operand:SI 0 "register_operand" "") 1932 (parallel [(set (match_operand:SI 0 "register_operand" "")
1577 (ashiftrt:SI (match_dup 2) 1933 (ashiftrt:SI (match_dup 2)
1578 (const_int 16))) 1934 (const_int 16)))
1579 (clobber (reg:CC CC_REGNUM))])] 1935 (clobber (reg:CC CC_REGNUM))])]
1580 "" 1936 ""
1581 " 1937 {
1582 { 1938 operands[1] = gen_lowpart (SImode, operands[1]);
1583 operands[1] = gen_lowpart (SImode, operands[1]); 1939 operands[2] = gen_reg_rtx (SImode);
1584 operands[2] = gen_reg_rtx (SImode); 1940 })
1585 }")
1586 1941
1587 ;; ??? The extendqisi2 pattern should not emit shifts for v850e? 1942 ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
1588 1943
1589 (define_insn "*extendqisi_insn" 1944 (define_insn "*extendqisi_insn"
1590 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1945 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1591 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m"))) 1946 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))
1592 (clobber (reg:CC CC_REGNUM))] 1947 (clobber (reg:CC CC_REGNUM))]
1593 "(TARGET_V850E || TARGET_V850E2_ALL)" 1948 "(TARGET_V850E_UP)"
1594 "@ 1949 "@
1595 sxb %0 1950 sxb %0
1596 sld.b %1,%0 1951 sld.b %1,%0
1597 ld.b %1,%0" 1952 ld.b %1,%0"
1598 [(set_attr "length" "2,2,4") 1953 [(set_attr "length" "2,2,4")
1609 (parallel [(set (match_operand:SI 0 "register_operand" "") 1964 (parallel [(set (match_operand:SI 0 "register_operand" "")
1610 (ashiftrt:SI (match_dup 2) 1965 (ashiftrt:SI (match_dup 2)
1611 (const_int 24))) 1966 (const_int 24)))
1612 (clobber (reg:CC CC_REGNUM))])] 1967 (clobber (reg:CC CC_REGNUM))])]
1613 "" 1968 ""
1614 " 1969 {
1615 { 1970 operands[1] = gen_lowpart (SImode, operands[1]);
1616 operands[1] = gen_lowpart (SImode, operands[1]); 1971 operands[2] = gen_reg_rtx (SImode);
1617 operands[2] = gen_reg_rtx (SImode); 1972 })
1618 }")
1619 1973
1620 ;; ---------------------------------------------------------------------- 1974 ;; ----------------------------------------------------------------------
1621 ;; SHIFTS 1975 ;; SHIFTS
1622 ;; ---------------------------------------------------------------------- 1976 ;; ----------------------------------------------------------------------
1623 1977
1638 [(set (match_operand:SI 0 "register_operand" "=r") 1992 [(set (match_operand:SI 0 "register_operand" "=r")
1639 (ashift:SI 1993 (ashift:SI
1640 (match_operand:SI 1 "register_operand" "r") 1994 (match_operand:SI 1 "register_operand" "r")
1641 (match_operand:SI 2 "nonmemory_operand" "r"))) 1995 (match_operand:SI 2 "nonmemory_operand" "r")))
1642 (clobber (reg:CC CC_REGNUM))] 1996 (clobber (reg:CC CC_REGNUM))]
1643 "TARGET_V850E2_ALL" 1997 "TARGET_V850E2_UP"
1644 "shl %2,%1,%0" 1998 "shl %2,%1,%0"
1645 [(set_attr "length" "4") 1999 [(set_attr "length" "4")
1646 (set_attr "cc" "set_znv")]) 2000 (set_attr "cc" "set_znv")])
1647 2001
1648 (define_insn "lshrsi3" 2002 (define_insn "lshrsi3"
1662 [(set (match_operand:SI 0 "register_operand" "=r") 2016 [(set (match_operand:SI 0 "register_operand" "=r")
1663 (lshiftrt:SI 2017 (lshiftrt:SI
1664 (match_operand:SI 1 "register_operand" "r") 2018 (match_operand:SI 1 "register_operand" "r")
1665 (match_operand:SI 2 "nonmemory_operand" "r"))) 2019 (match_operand:SI 2 "nonmemory_operand" "r")))
1666 (clobber (reg:CC CC_REGNUM))] 2020 (clobber (reg:CC CC_REGNUM))]
1667 "TARGET_V850E2_ALL" 2021 "TARGET_V850E2_UP"
1668 "shr %2,%1,%0" 2022 "shr %2,%1,%0"
1669 [(set_attr "length" "4") 2023 [(set_attr "length" "4")
1670 (set_attr "cc" "set_zn")]) 2024 (set_attr "cc" "set_zn")])
1671 2025
1672 (define_insn "ashrsi3" 2026 (define_insn "ashrsi3"
1686 [(set (match_operand:SI 0 "register_operand" "=r") 2040 [(set (match_operand:SI 0 "register_operand" "=r")
1687 (ashiftrt:SI 2041 (ashiftrt:SI
1688 (match_operand:SI 1 "register_operand" "r") 2042 (match_operand:SI 1 "register_operand" "r")
1689 (match_operand:SI 2 "nonmemory_operand" "r"))) 2043 (match_operand:SI 2 "nonmemory_operand" "r")))
1690 (clobber (reg:CC CC_REGNUM))] 2044 (clobber (reg:CC CC_REGNUM))]
1691 "TARGET_V850E2_ALL" 2045 "TARGET_V850E2_UP"
1692 "sar %2,%1,%0" 2046 "sar %2,%1,%0"
1693 [(set_attr "length" "4") 2047 [(set_attr "length" "4")
1694 (set_attr "cc" "set_zn")]) 2048 (set_attr "cc" "set_zn")])
1695 2049
1696 ;; ---------------------------------------------------------------------- 2050 ;; ----------------------------------------------------------------------
1699 2053
1700 (define_insn "ffssi2" 2054 (define_insn "ffssi2"
1701 [(set (match_operand:SI 0 "register_operand" "=r") 2055 [(set (match_operand:SI 0 "register_operand" "=r")
1702 (ffs:SI (match_operand:SI 1 "register_operand" "r"))) 2056 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
1703 (clobber (reg:CC CC_REGNUM))] 2057 (clobber (reg:CC CC_REGNUM))]
1704 "TARGET_V850E2_ALL" 2058 "TARGET_V850E2_UP"
1705 "sch1r %1,%0" 2059 "sch1r %1,%0"
1706 [(set_attr "length" "4") 2060 [(set_attr "length" "4")
1707 (set_attr "cc" "clobber")]) 2061 (set_attr "cc" "clobber")])
1708 2062
1709 ;; ---------------------------------------------------------------------- 2063 ;; ----------------------------------------------------------------------
1710 ;; PROLOGUE/EPILOGUE 2064 ;; PROLOGUE/EPILOGUE
1711 ;; ---------------------------------------------------------------------- 2065 ;; ----------------------------------------------------------------------
1712 (define_expand "prologue" 2066 (define_expand "prologue"
1713 [(const_int 0)] 2067 [(const_int 0)]
1714 "" 2068 ""
1715 "expand_prologue (); DONE;") 2069 {
2070 expand_prologue ();
2071 DONE;
2072 })
1716 2073
1717 (define_expand "epilogue" 2074 (define_expand "epilogue"
1718 [(return)] 2075 [(return)]
1719 "" 2076 ""
1720 " 2077 {
1721 { 2078 expand_epilogue ();
1722 expand_epilogue (); 2079 DONE;
1723 DONE; 2080 })
1724 }")
1725 2081
1726 (define_insn "return_simple" 2082 (define_insn "return_simple"
1727 [(return)] 2083 [(return)]
1728 "reload_completed" 2084 "reload_completed"
1729 "jmp [r31]" 2085 "jmp [r31]"
1745 2101
1746 (define_insn "addsf3" 2102 (define_insn "addsf3"
1747 [(set (match_operand:SF 0 "register_operand" "=r") 2103 [(set (match_operand:SF 0 "register_operand" "=r")
1748 (plus:SF (match_operand:SF 1 "register_operand" "r") 2104 (plus:SF (match_operand:SF 1 "register_operand" "r")
1749 (match_operand:SF 2 "register_operand" "r")))] 2105 (match_operand:SF 2 "register_operand" "r")))]
1750 "TARGET_V850E2V3" 2106 "TARGET_USE_FPU"
1751 "addf.s %1,%2,%0" 2107 "addf.s %1,%2,%0"
1752 [(set_attr "length" "4") 2108 [(set_attr "length" "4")
1753 (set_attr "cc" "none_0hit") 2109 (set_attr "cc" "none_0hit")
1754 (set_attr "type" "fpu")]) 2110 (set_attr "type" "fpu")])
1755 2111
1756 (define_insn "adddf3" 2112 (define_insn "adddf3"
1757 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2113 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1758 (plus:DF (match_operand:DF 1 "even_reg_operand" "r") 2114 (plus:DF (match_operand:DF 1 "even_reg_operand" "r")
1759 (match_operand:DF 2 "even_reg_operand" "r")))] 2115 (match_operand:DF 2 "even_reg_operand" "r")))]
1760 "TARGET_V850E2V3" 2116 "TARGET_USE_FPU"
1761 "addf.d %1,%2,%0" 2117 "addf.d %1,%2,%0"
1762 [(set_attr "length" "4") 2118 [(set_attr "length" "4")
1763 (set_attr "cc" "none_0hit") 2119 (set_attr "cc" "none_0hit")
1764 (set_attr "type" "fpu")]) 2120 (set_attr "type" "fpu")])
1765 2121
1766 (define_insn "subsf3" 2122 (define_insn "subsf3"
1767 [(set (match_operand:SF 0 "register_operand" "=r") 2123 [(set (match_operand:SF 0 "register_operand" "=r")
1768 (minus:SF (match_operand:SF 1 "register_operand" "r") 2124 (minus:SF (match_operand:SF 1 "register_operand" "r")
1769 (match_operand:SF 2 "register_operand" "r")))] 2125 (match_operand:SF 2 "register_operand" "r")))]
1770 "TARGET_V850E2V3" 2126 "TARGET_USE_FPU"
1771 "subf.s %2,%1,%0" 2127 "subf.s %2,%1,%0"
1772 [(set_attr "length" "4") 2128 [(set_attr "length" "4")
1773 (set_attr "cc" "none_0hit") 2129 (set_attr "cc" "none_0hit")
1774 (set_attr "type" "fpu")]) 2130 (set_attr "type" "fpu")])
1775 2131
1776 (define_insn "subdf3" 2132 (define_insn "subdf3"
1777 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2133 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1778 (minus:DF (match_operand:DF 1 "even_reg_operand" "r") 2134 (minus:DF (match_operand:DF 1 "even_reg_operand" "r")
1779 (match_operand:DF 2 "even_reg_operand" "r")))] 2135 (match_operand:DF 2 "even_reg_operand" "r")))]
1780 "TARGET_V850E2V3" 2136 "TARGET_USE_FPU"
1781 "subf.d %2,%1,%0" 2137 "subf.d %2,%1,%0"
1782 [(set_attr "length" "4") 2138 [(set_attr "length" "4")
1783 (set_attr "cc" "none_0hit") 2139 (set_attr "cc" "none_0hit")
1784 (set_attr "type" "fpu")]) 2140 (set_attr "type" "fpu")])
1785 2141
1786 (define_insn "mulsf3" 2142 (define_insn "mulsf3"
1787 [(set (match_operand:SF 0 "register_operand" "=r") 2143 [(set (match_operand:SF 0 "register_operand" "=r")
1788 (mult:SF (match_operand:SF 1 "register_operand" "r") 2144 (mult:SF (match_operand:SF 1 "register_operand" "r")
1789 (match_operand:SF 2 "register_operand" "r")))] 2145 (match_operand:SF 2 "register_operand" "r")))]
1790 "TARGET_V850E2V3" 2146 "TARGET_USE_FPU"
1791 "mulf.s %1,%2,%0" 2147 "mulf.s %1,%2,%0"
1792 [(set_attr "length" "4") 2148 [(set_attr "length" "4")
1793 (set_attr "cc" "none_0hit") 2149 (set_attr "cc" "none_0hit")
1794 (set_attr "type" "fpu")]) 2150 (set_attr "type" "fpu")])
1795 2151
1796 (define_insn "muldf3" 2152 (define_insn "muldf3"
1797 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2153 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1798 (mult:DF (match_operand:DF 1 "even_reg_operand" "r") 2154 (mult:DF (match_operand:DF 1 "even_reg_operand" "r")
1799 (match_operand:DF 2 "even_reg_operand" "r")))] 2155 (match_operand:DF 2 "even_reg_operand" "r")))]
1800 "TARGET_V850E2V3" 2156 "TARGET_USE_FPU"
1801 "mulf.d %1,%2,%0" 2157 "mulf.d %1,%2,%0"
1802 [(set_attr "length" "4") 2158 [(set_attr "length" "4")
1803 (set_attr "cc" "none_0hit") 2159 (set_attr "cc" "none_0hit")
1804 (set_attr "type" "fpu")]) 2160 (set_attr "type" "fpu")])
1805 2161
1806 (define_insn "divsf3" 2162 (define_insn "divsf3"
1807 [(set (match_operand:SF 0 "register_operand" "=r") 2163 [(set (match_operand:SF 0 "register_operand" "=r")
1808 (div:SF (match_operand:SF 1 "register_operand" "r") 2164 (div:SF (match_operand:SF 1 "register_operand" "r")
1809 (match_operand:SF 2 "register_operand" "r")))] 2165 (match_operand:SF 2 "register_operand" "r")))]
1810 "TARGET_V850E2V3" 2166 "TARGET_USE_FPU"
1811 "divf.s %2,%1,%0" 2167 "divf.s %2,%1,%0"
1812 [(set_attr "length" "4") 2168 [(set_attr "length" "4")
1813 (set_attr "cc" "none_0hit") 2169 (set_attr "cc" "none_0hit")
1814 (set_attr "type" "fpu")]) 2170 (set_attr "type" "fpu")])
1815 2171
1816 (define_insn "divdf3" 2172 (define_insn "divdf3"
1817 [(set (match_operand:DF 0 "register_operand" "=r") 2173 [(set (match_operand:DF 0 "register_operand" "=r")
1818 (div:DF (match_operand:DF 1 "even_reg_operand" "r") 2174 (div:DF (match_operand:DF 1 "even_reg_operand" "r")
1819 (match_operand:DF 2 "even_reg_operand" "r")))] 2175 (match_operand:DF 2 "even_reg_operand" "r")))]
1820 "TARGET_V850E2V3" 2176 "TARGET_USE_FPU"
1821 "divf.d %2,%1,%0" 2177 "divf.d %2,%1,%0"
1822 [(set_attr "length" "4") 2178 [(set_attr "length" "4")
1823 (set_attr "cc" "none_0hit") 2179 (set_attr "cc" "none_0hit")
1824 (set_attr "type" "fpu")]) 2180 (set_attr "type" "fpu")])
1825 2181
1826 (define_insn "minsf3" 2182 (define_insn "minsf3"
1827 [(set (match_operand:SF 0 "register_operand" "=r") 2183 [(set (match_operand:SF 0 "register_operand" "=r")
1828 (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r") 2184 (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1829 (match_operand:SF 2 "reg_or_0_operand" "r")))] 2185 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1830 "TARGET_V850E2V3" 2186 "TARGET_USE_FPU"
1831 "minf.s %z1,%z2,%0" 2187 "minf.s %z1,%z2,%0"
1832 [(set_attr "length" "4") 2188 [(set_attr "length" "4")
1833 (set_attr "cc" "none_0hit") 2189 (set_attr "cc" "none_0hit")
1834 (set_attr "type" "fpu")]) 2190 (set_attr "type" "fpu")])
1835 2191
1836 (define_insn "mindf3" 2192 (define_insn "mindf3"
1837 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2193 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1838 (smin:DF (match_operand:DF 1 "even_reg_operand" "r") 2194 (smin:DF (match_operand:DF 1 "even_reg_operand" "r")
1839 (match_operand:DF 2 "even_reg_operand" "r")))] 2195 (match_operand:DF 2 "even_reg_operand" "r")))]
1840 "TARGET_V850E2V3" 2196 "TARGET_USE_FPU"
1841 "minf.d %1,%2,%0" 2197 "minf.d %1,%2,%0"
1842 [(set_attr "length" "4") 2198 [(set_attr "length" "4")
1843 (set_attr "cc" "none_0hit") 2199 (set_attr "cc" "none_0hit")
1844 (set_attr "type" "fpu")]) 2200 (set_attr "type" "fpu")])
1845 2201
1846 (define_insn "maxsf3" 2202 (define_insn "maxsf3"
1847 [(set (match_operand:SF 0 "register_operand" "=r") 2203 [(set (match_operand:SF 0 "register_operand" "=r")
1848 (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r") 2204 (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1849 (match_operand:SF 2 "reg_or_0_operand" "r")))] 2205 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1850 "TARGET_V850E2V3" 2206 "TARGET_USE_FPU"
1851 "maxf.s %z1,%z2,%0" 2207 "maxf.s %z1,%z2,%0"
1852 [(set_attr "length" "4") 2208 [(set_attr "length" "4")
1853 (set_attr "cc" "none_0hit") 2209 (set_attr "cc" "none_0hit")
1854 (set_attr "type" "fpu")]) 2210 (set_attr "type" "fpu")])
1855 2211
1856 (define_insn "maxdf3" 2212 (define_insn "maxdf3"
1857 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2213 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1858 (smax:DF (match_operand:DF 1 "even_reg_operand" "r") 2214 (smax:DF (match_operand:DF 1 "even_reg_operand" "r")
1859 (match_operand:DF 2 "even_reg_operand" "r")))] 2215 (match_operand:DF 2 "even_reg_operand" "r")))]
1860 "TARGET_V850E2V3" 2216 "TARGET_USE_FPU"
1861 "maxf.d %1,%2,%0" 2217 "maxf.d %1,%2,%0"
1862 [(set_attr "length" "4") 2218 [(set_attr "length" "4")
1863 (set_attr "cc" "none_0hit") 2219 (set_attr "cc" "none_0hit")
1864 (set_attr "type" "fpu")]) 2220 (set_attr "type" "fpu")])
1865 2221
1866 (define_insn "abssf2" 2222 (define_insn "abssf2"
1867 [(set (match_operand:SF 0 "register_operand" "=r") 2223 [(set (match_operand:SF 0 "register_operand" "=r")
1868 (abs:SF (match_operand:SF 1 "register_operand" "r")))] 2224 (abs:SF (match_operand:SF 1 "register_operand" "r")))]
1869 "TARGET_V850E2V3" 2225 "TARGET_USE_FPU"
1870 "absf.s %1,%0" 2226 "absf.s %1,%0"
1871 [(set_attr "length" "4") 2227 [(set_attr "length" "4")
1872 (set_attr "cc" "none_0hit") 2228 (set_attr "cc" "none_0hit")
1873 (set_attr "type" "fpu")]) 2229 (set_attr "type" "fpu")])
1874 2230
1875 (define_insn "absdf2" 2231 (define_insn "absdf2"
1876 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2232 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1877 (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))] 2233 (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1878 "TARGET_V850E2V3" 2234 "TARGET_USE_FPU"
1879 "absf.d %1,%0" 2235 "absf.d %1,%0"
1880 [(set_attr "length" "4") 2236 [(set_attr "length" "4")
1881 (set_attr "cc" "none_0hit") 2237 (set_attr "cc" "none_0hit")
1882 (set_attr "type" "fpu")]) 2238 (set_attr "type" "fpu")])
1883 2239
1884 (define_insn "negsf2" 2240 (define_insn "negsf2"
1885 [(set (match_operand:SF 0 "register_operand" "=r") 2241 [(set (match_operand:SF 0 "register_operand" "=r")
1886 (neg:SF (match_operand:SF 1 "register_operand" "r")))] 2242 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
1887 "TARGET_V850E2V3" 2243 "TARGET_USE_FPU"
1888 "negf.s %1,%0" 2244 "negf.s %1,%0"
1889 [(set_attr "length" "4") 2245 [(set_attr "length" "4")
1890 (set_attr "cc" "none_0hit") 2246 (set_attr "cc" "none_0hit")
1891 (set_attr "type" "fpu")]) 2247 (set_attr "type" "fpu")])
1892 2248
1893 (define_insn "negdf2" 2249 (define_insn "negdf2"
1894 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2250 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1895 (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))] 2251 (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1896 "TARGET_V850E2V3" 2252 "TARGET_USE_FPU"
1897 "negf.d %1,%0" 2253 "negf.d %1,%0"
1898 [(set_attr "length" "4") 2254 [(set_attr "length" "4")
1899 (set_attr "cc" "none_0hit") 2255 (set_attr "cc" "none_0hit")
1900 (set_attr "type" "fpu")]) 2256 (set_attr "type" "fpu")])
1901 2257
1902 ;; square-root 2258 ;; square-root
1903 (define_insn "sqrtsf2" 2259 (define_insn "sqrtsf2"
1904 [(set (match_operand:SF 0 "register_operand" "=r") 2260 [(set (match_operand:SF 0 "register_operand" "=r")
1905 (sqrt:SF (match_operand:SF 1 "register_operand" "r")))] 2261 (sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
1906 "TARGET_V850E2V3" 2262 "TARGET_USE_FPU"
1907 "sqrtf.s %1,%0" 2263 "sqrtf.s %1,%0"
1908 [(set_attr "length" "4") 2264 [(set_attr "length" "4")
1909 (set_attr "cc" "none_0hit") 2265 (set_attr "cc" "none_0hit")
1910 (set_attr "type" "fpu")]) 2266 (set_attr "type" "fpu")])
1911 2267
1912 (define_insn "sqrtdf2" 2268 (define_insn "sqrtdf2"
1913 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2269 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1914 (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))] 2270 (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1915 "TARGET_V850E2V3" 2271 "TARGET_USE_FPU"
1916 "sqrtf.d %1,%0" 2272 "sqrtf.d %1,%0"
1917 [(set_attr "length" "4") 2273 [(set_attr "length" "4")
1918 (set_attr "cc" "none_0hit") 2274 (set_attr "cc" "none_0hit")
1919 (set_attr "type" "fpu")]) 2275 (set_attr "type" "fpu")])
1920 2276
1921 ;; float -> int 2277 ;; float -> int
1922 (define_insn "fix_truncsfsi2" 2278 (define_insn "fix_truncsfsi2"
1923 [(set (match_operand:SI 0 "register_operand" "=r") 2279 [(set (match_operand:SI 0 "register_operand" "=r")
1924 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "r"))))] 2280 (fix:SI (match_operand:SF 1 "register_operand" "r")))]
1925 "TARGET_V850E2V3" 2281 "TARGET_USE_FPU"
1926 "trncf.sw %1,%0" 2282 "trncf.sw %1,%0"
1927 [(set_attr "length" "4") 2283 [(set_attr "length" "4")
1928 (set_attr "cc" "none_0hit") 2284 (set_attr "cc" "none_0hit")
1929 (set_attr "type" "fpu")]) 2285 (set_attr "type" "fpu")])
1930 2286
2287 (define_insn "fixuns_truncsfsi2"
2288 [(set (match_operand:SI 0 "register_operand" "=r")
2289 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2290 "TARGET_USE_FPU"
2291 "trncf.suw %1, %0"
2292 [(set_attr "length" "4")
2293 (set_attr "cc" "none_0hit")
2294 (set_attr "type" "fpu")]
2295 )
2296
1931 (define_insn "fix_truncdfsi2" 2297 (define_insn "fix_truncdfsi2"
1932 [(set (match_operand:SI 0 "register_operand" "=r") 2298 [(set (match_operand:SI 0 "register_operand" "=r")
1933 (fix:SI (fix:DF (match_operand:DF 1 "even_reg_operand" "r"))))] 2299 (fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
1934 "TARGET_V850E2V3" 2300 "TARGET_USE_FPU"
1935 "trncf.dw %1,%0" 2301 "trncf.dw %1,%0"
1936 [(set_attr "length" "4") 2302 [(set_attr "length" "4")
1937 (set_attr "cc" "none_0hit") 2303 (set_attr "cc" "none_0hit")
1938 (set_attr "type" "fpu")]) 2304 (set_attr "type" "fpu")])
2305
2306 (define_insn "fixuns_truncdfsi2"
2307 [(set (match_operand:SI 0 "register_operand" "=r")
2308 (unsigned_fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
2309 "TARGET_USE_FPU"
2310 "trncf.duw %1, %0"
2311 [(set_attr "length" "4")
2312 (set_attr "cc" "none_0hit")
2313 (set_attr "type" "fpu")]
2314 )
2315
2316 (define_insn "fix_truncsfdi2"
2317 [(set (match_operand:DI 0 "register_operand" "=r")
2318 (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2319 "TARGET_USE_FPU"
2320 "trncf.sl %1, %0"
2321 [(set_attr "length" "4")
2322 (set_attr "cc" "none_0hit")
2323 (set_attr "type" "fpu")])
2324
2325 (define_insn "fixuns_truncsfdi2"
2326 [(set (match_operand:DI 0 "register_operand" "=r")
2327 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2328 "TARGET_USE_FPU"
2329 "trncf.sul %1, %0"
2330 [(set_attr "length" "4")
2331 (set_attr "cc" "none_0hit")
2332 (set_attr "type" "fpu")]
2333 )
2334
2335 (define_insn "fix_truncdfdi2"
2336 [(set (match_operand:DI 0 "register_operand" "=r")
2337 (fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
2338 "TARGET_USE_FPU"
2339 "trncf.dl %1, %0"
2340 [(set_attr "length" "4")
2341 (set_attr "cc" "none_0hit")
2342 (set_attr "type" "fpu")])
2343
2344 (define_insn "fixuns_truncdfdi2"
2345 [(set (match_operand:DI 0 "register_operand" "=r")
2346 (unsigned_fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
2347 "TARGET_USE_FPU"
2348 "trncf.dul %1, %0"
2349 [(set_attr "length" "4")
2350 (set_attr "cc" "none_0hit")
2351 (set_attr "type" "fpu")]
2352 )
1939 2353
1940 ;; int -> float 2354 ;; int -> float
1941 (define_insn "floatsisf2" 2355 (define_insn "floatsisf2"
1942 [(set (match_operand:SF 0 "register_operand" "=r") 2356 [(set (match_operand:SF 0 "register_operand" "=r")
1943 (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))] 2357 (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
1944 "TARGET_V850E2V3" 2358 "TARGET_USE_FPU"
1945 "cvtf.ws %z1, %0" 2359 "cvtf.ws %z1, %0"
2360 [(set_attr "length" "4")
2361 (set_attr "cc" "none_0hit")
2362 (set_attr "type" "fpu")])
2363
2364 (define_insn "unsfloatsisf2"
2365 [(set (match_operand:SF 0 "register_operand" "=r")
2366 (unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2367 "TARGET_USE_FPU"
2368 "cvtf.uws %z1, %0"
1946 [(set_attr "length" "4") 2369 [(set_attr "length" "4")
1947 (set_attr "cc" "none_0hit") 2370 (set_attr "cc" "none_0hit")
1948 (set_attr "type" "fpu")]) 2371 (set_attr "type" "fpu")])
1949 2372
1950 (define_insn "floatsidf2" 2373 (define_insn "floatsidf2"
1951 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2374 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1952 (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))] 2375 (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
1953 "TARGET_V850E2V3" 2376 "TARGET_USE_FPU"
1954 "cvtf.wd %z1,%0" 2377 "cvtf.wd %z1,%0"
2378 [(set_attr "length" "4")
2379 (set_attr "cc" "none_0hit")
2380 (set_attr "type" "fpu")])
2381
2382 (define_insn "unsfloatsidf2"
2383 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2384 (unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2385 "TARGET_USE_FPU"
2386 "cvtf.uwd %z1, %0"
2387 [(set_attr "length" "4")
2388 (set_attr "cc" "none_0hit")
2389 (set_attr "type" "fpu")])
2390
2391 (define_insn "floatdisf2"
2392 [(set (match_operand:SF 0 "even_reg_operand" "=r")
2393 (float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2394 "TARGET_USE_FPU"
2395 "cvtf.ls %z1, %0"
2396 [(set_attr "length" "4")
2397 (set_attr "cc" "none_0hit")
2398 (set_attr "type" "fpu")])
2399
2400 (define_insn "unsfloatdisf2"
2401 [(set (match_operand:SF 0 "even_reg_operand" "=r")
2402 (unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2403 "TARGET_USE_FPU"
2404 "cvtf.uls %z1, %0"
2405 [(set_attr "length" "4")
2406 (set_attr "cc" "none_0hit")
2407 (set_attr "type" "fpu")])
2408
2409 (define_insn "floatdidf2"
2410 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2411 (float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2412 "TARGET_USE_FPU"
2413 "cvtf.ld %z1, %0"
2414 [(set_attr "length" "4")
2415 (set_attr "cc" "none_0hit")
2416 (set_attr "type" "fpu")])
2417
2418 (define_insn "unsfloatdidf2"
2419 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2420 (unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2421 "TARGET_USE_FPU"
2422 "cvtf.uld %z1, %0"
1955 [(set_attr "length" "4") 2423 [(set_attr "length" "4")
1956 (set_attr "cc" "none_0hit") 2424 (set_attr "cc" "none_0hit")
1957 (set_attr "type" "fpu")]) 2425 (set_attr "type" "fpu")])
1958 2426
1959 ;; single-float -> double-float 2427 ;; single-float -> double-float
1960 (define_insn "extendsfdf2" 2428 (define_insn "extendsfdf2"
1961 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2429 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1962 (float_extend:DF 2430 (float_extend:DF
1963 (match_operand:SF 1 "reg_or_0_operand" "rI")))] 2431 (match_operand:SF 1 "reg_or_0_operand" "rI")))]
1964 "TARGET_V850E2V3" 2432 "TARGET_USE_FPU"
1965 "cvtf.sd %z1,%0" 2433 "cvtf.sd %z1,%0"
1966 [(set_attr "length" "4") 2434 [(set_attr "length" "4")
1967 (set_attr "cc" "none_0hit") 2435 (set_attr "cc" "none_0hit")
1968 (set_attr "type" "fpu")]) 2436 (set_attr "type" "fpu")])
1969 2437
1970 ;; double-float -> single-float 2438 ;; double-float -> single-float
1971 (define_insn "truncdfsf2" 2439 (define_insn "truncdfsf2"
1972 [(set (match_operand:SF 0 "register_operand" "=r") 2440 [(set (match_operand:SF 0 "register_operand" "=r")
1973 (float_truncate:SF 2441 (float_truncate:SF
1974 (match_operand:DF 1 "even_reg_operand" "r")))] 2442 (match_operand:DF 1 "even_reg_operand" "r")))]
1975 "TARGET_V850E2V3" 2443 "TARGET_USE_FPU"
1976 "cvtf.ds %1,%0" 2444 "cvtf.ds %1,%0"
1977 [(set_attr "length" "4") 2445 [(set_attr "length" "4")
1978 (set_attr "cc" "none_0hit") 2446 (set_attr "cc" "none_0hit")
1979 (set_attr "type" "fpu")]) 2447 (set_attr "type" "fpu")])
1980 2448
1985 ;;; reciprocal 2453 ;;; reciprocal
1986 (define_insn "recipsf2" 2454 (define_insn "recipsf2"
1987 [(set (match_operand:SF 0 "register_operand" "=r") 2455 [(set (match_operand:SF 0 "register_operand" "=r")
1988 (div:SF (match_operand:SF 1 "const_float_1_operand" "") 2456 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
1989 (match_operand:SF 2 "register_operand" "r")))] 2457 (match_operand:SF 2 "register_operand" "r")))]
1990 "TARGET_V850E2V3" 2458 "TARGET_USE_FPU"
1991 "recipf.s %2,%0" 2459 "recipf.s %2,%0"
1992 [(set_attr "length" "4") 2460 [(set_attr "length" "4")
1993 (set_attr "cc" "none_0hit") 2461 (set_attr "cc" "none_0hit")
1994 (set_attr "type" "fpu")]) 2462 (set_attr "type" "fpu")])
1995 2463
1996 (define_insn "recipdf2" 2464 (define_insn "recipdf2"
1997 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2465 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1998 (div:DF (match_operand:DF 1 "const_float_1_operand" "") 2466 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
1999 (match_operand:DF 2 "even_reg_operand" "r")))] 2467 (match_operand:DF 2 "even_reg_operand" "r")))]
2000 "TARGET_V850E2V3" 2468 "TARGET_USE_FPU"
2001 "recipf.d %2,%0" 2469 "recipf.d %2,%0"
2002 [(set_attr "length" "4") 2470 [(set_attr "length" "4")
2003 (set_attr "cc" "none_0hit") 2471 (set_attr "cc" "none_0hit")
2004 (set_attr "type" "fpu")]) 2472 (set_attr "type" "fpu")])
2005 2473
2006 ;;; reciprocal of square-root 2474 ;;; reciprocal of square-root
2007 (define_insn "rsqrtsf2" 2475 (define_insn "rsqrtsf2"
2008 [(set (match_operand:SF 0 "register_operand" "=r") 2476 [(set (match_operand:SF 0 "register_operand" "=r")
2009 (div:SF (match_operand:SF 1 "const_float_1_operand" "") 2477 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2010 (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))] 2478 (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))]
2011 "TARGET_V850E2V3" 2479 "TARGET_USE_FPU"
2012 "rsqrtf.s %2,%0" 2480 "rsqrtf.s %2,%0"
2013 [(set_attr "length" "4") 2481 [(set_attr "length" "4")
2014 (set_attr "cc" "none_0hit") 2482 (set_attr "cc" "none_0hit")
2015 (set_attr "type" "fpu")]) 2483 (set_attr "type" "fpu")])
2016 2484
2017 (define_insn "rsqrtdf2" 2485 (define_insn "rsqrtdf2"
2018 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2486 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2019 (div:DF (match_operand:DF 1 "const_float_1_operand" "") 2487 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2020 (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))] 2488 (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))]
2021 "TARGET_V850E2V3" 2489 "TARGET_USE_FPU"
2022 "rsqrtf.d %2,%0" 2490 "rsqrtf.d %2,%0"
2023 [(set_attr "length" "4") 2491 [(set_attr "length" "4")
2024 (set_attr "cc" "none_0hit") 2492 (set_attr "cc" "none_0hit")
2025 (set_attr "type" "fpu")]) 2493 (set_attr "type" "fpu")])
2494
2495 ;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually
2496 ;; need operand 4 to be the same as operand 0. But the FPU-2.0 versions are
2497 ;; also deprecated so the loss of flexibility is unimportant.
2026 2498
2027 ;;; multiply-add 2499 ;;; multiply-add
2028 (define_insn "fmasf4" 2500 (define_insn "fmasf4"
2029 [(set (match_operand:SF 0 "register_operand" "=r") 2501 [(set (match_operand:SF 0 "register_operand" "=r")
2030 (fma:SF (match_operand:SF 1 "register_operand" "r") 2502 (fma:SF (match_operand:SF 1 "register_operand" "r")
2031 (match_operand:SF 2 "register_operand" "r") 2503 (match_operand:SF 2 "register_operand" "r")
2032 (match_operand:SF 3 "register_operand" "r")))] 2504 (match_operand:SF 3 "register_operand" "0")))]
2033 "TARGET_V850E2V3" 2505 "TARGET_USE_FPU"
2034 "maddf.s %2,%1,%3,%0" 2506 { return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; }
2035 [(set_attr "length" "4") 2507 [(set_attr "length" "4")
2036 (set_attr "cc" "none_0hit") 2508 (set_attr "cc" "none_0hit")
2037 (set_attr "type" "fpu")]) 2509 (set_attr "type" "fpu")])
2038 2510
2039 ;;; multiply-subtract 2511 ;;; multiply-subtract
2040 (define_insn "fmssf4" 2512 (define_insn "fmssf4"
2041 [(set (match_operand:SF 0 "register_operand" "=r") 2513 [(set (match_operand:SF 0 "register_operand" "=r")
2042 (fma:SF (match_operand:SF 1 "register_operand" "r") 2514 (fma:SF (match_operand:SF 1 "register_operand" "r")
2043 (match_operand:SF 2 "register_operand" "r") 2515 (match_operand:SF 2 "register_operand" "r")
2044 (neg:SF (match_operand:SF 3 "register_operand" "r"))))] 2516 (neg:SF (match_operand:SF 3 "register_operand" "0"))))]
2045 "TARGET_V850E2V3" 2517 "TARGET_USE_FPU"
2046 "msubf.s %2,%1,%3,%0" 2518 { return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; }
2047 [(set_attr "length" "4") 2519 [(set_attr "length" "4")
2048 (set_attr "cc" "none_0hit") 2520 (set_attr "cc" "none_0hit")
2049 (set_attr "type" "fpu")]) 2521 (set_attr "type" "fpu")])
2050 2522
2051 ;;; negative-multiply-add 2523 ;;; negative-multiply-add
2052 (define_insn "fnmasf4" 2524 (define_insn "fnmasf4"
2053 [(set (match_operand:SF 0 "register_operand" "=r") 2525 [(set (match_operand:SF 0 "register_operand" "=r")
2054 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 2526 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
2055 (match_operand:SF 2 "register_operand" "r") 2527 (match_operand:SF 2 "register_operand" "r")
2056 (match_operand:SF 3 "register_operand" "r")))] 2528 (match_operand:SF 3 "register_operand" "0"))))]
2057 "TARGET_V850E2V3" 2529 "TARGET_USE_FPU"
2058 "nmaddf.s %2,%1,%3,%0" 2530 { return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; }
2059 [(set_attr "length" "4") 2531 [(set_attr "length" "4")
2060 (set_attr "cc" "none_0hit") 2532 (set_attr "cc" "none_0hit")
2061 (set_attr "type" "fpu")]) 2533 (set_attr "type" "fpu")])
2062 2534
2063 ;; negative-multiply-subtract 2535 ;; negative-multiply-subtract
2064 (define_insn "fnmssf4" 2536 (define_insn "fnmssf4"
2065 [(set (match_operand:SF 0 "register_operand" "=r") 2537 [(set (match_operand:SF 0 "register_operand" "=r")
2066 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 2538 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
2067 (match_operand:SF 2 "register_operand" "r") 2539 (match_operand:SF 2 "register_operand" "r")
2068 (neg:SF (match_operand:SF 3 "register_operand" "r"))))] 2540 (neg:SF (match_operand:SF 3 "register_operand" "0")))))]
2069 "TARGET_V850E2V3" 2541 "TARGET_USE_FPU"
2070 "nmsubf.s %2,%1,%3,%0" 2542 { return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; }
2071 [(set_attr "length" "4") 2543 [(set_attr "length" "4")
2072 (set_attr "cc" "none_0hit") 2544 (set_attr "cc" "none_0hit")
2073 (set_attr "type" "fpu")]) 2545 (set_attr "type" "fpu")])
2074 ; 2546 ;
2075 ; ---------------- comparison/conditionals 2547 ; ---------------- comparison/conditionals
2078 2550
2079 (define_insn "cmpsf_le_insn" 2551 (define_insn "cmpsf_le_insn"
2080 [(set (reg:CC_FPU_LE FCC_REGNUM) 2552 [(set (reg:CC_FPU_LE FCC_REGNUM)
2081 (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r") 2553 (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
2082 (match_operand:SF 1 "register_operand" "r")))] 2554 (match_operand:SF 1 "register_operand" "r")))]
2083 "TARGET_V850E2V3" 2555 "TARGET_USE_FPU"
2084 "cmpf.s le,%z0,%z1" 2556 "cmpf.s le, %z0, %z1"
2085 [(set_attr "length" "4") 2557 [(set_attr "length" "4")
2086 (set_attr "cc" "none_0hit") 2558 (set_attr "cc" "none_0hit")
2087 (set_attr "type" "fpu")]) 2559 (set_attr "type" "fpu")])
2088 2560
2089 (define_insn "cmpsf_lt_insn" 2561 (define_insn "cmpsf_lt_insn"
2090 [(set (reg:CC_FPU_LT FCC_REGNUM) 2562 [(set (reg:CC_FPU_LT FCC_REGNUM)
2091 (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r") 2563 (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
2092 (match_operand:SF 1 "register_operand" "r")))] 2564 (match_operand:SF 1 "register_operand" "r")))]
2093 "TARGET_V850E2V3" 2565 "TARGET_USE_FPU"
2094 "cmpf.s lt,%z0,%z1" 2566 "cmpf.s lt, %z0, %z1"
2095 [(set_attr "length" "4") 2567 [(set_attr "length" "4")
2096 (set_attr "cc" "none_0hit") 2568 (set_attr "cc" "none_0hit")
2097 (set_attr "type" "fpu")]) 2569 (set_attr "type" "fpu")])
2098 2570
2099 (define_insn "cmpsf_ge_insn" 2571 (define_insn "cmpsf_ge_insn"
2100 [(set (reg:CC_FPU_GE FCC_REGNUM) 2572 [(set (reg:CC_FPU_GE FCC_REGNUM)
2101 (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r") 2573 (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
2102 (match_operand:SF 1 "register_operand" "r")))] 2574 (match_operand:SF 1 "register_operand" "r")))]
2103 "TARGET_V850E2V3" 2575 "TARGET_USE_FPU"
2104 "cmpf.s ge,%z0,%z1" 2576 "cmpf.s le, %z1, %z0"
2105 [(set_attr "length" "4") 2577 [(set_attr "length" "4")
2106 (set_attr "cc" "none_0hit") 2578 (set_attr "cc" "none_0hit")
2107 (set_attr "type" "fpu")]) 2579 (set_attr "type" "fpu")])
2108 2580
2109 (define_insn "cmpsf_gt_insn" 2581 (define_insn "cmpsf_gt_insn"
2110 [(set (reg:CC_FPU_GT FCC_REGNUM) 2582 [(set (reg:CC_FPU_GT FCC_REGNUM)
2111 (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r") 2583 (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
2112 (match_operand:SF 1 "register_operand" "r")))] 2584 (match_operand:SF 1 "register_operand" "r")))]
2113 "TARGET_V850E2V3" 2585 "TARGET_USE_FPU"
2114 "cmpf.s gt,%z0,%z1" 2586 "cmpf.s lt, %z1, %z0"
2115 [(set_attr "length" "4") 2587 [(set_attr "length" "4")
2116 (set_attr "cc" "none_0hit") 2588 (set_attr "cc" "none_0hit")
2117 (set_attr "type" "fpu")]) 2589 (set_attr "type" "fpu")])
2118 2590
2119 (define_insn "cmpsf_eq_insn" 2591 (define_insn "cmpsf_eq_insn"
2120 [(set (reg:CC_FPU_EQ FCC_REGNUM) 2592 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2121 (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r") 2593 (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
2122 (match_operand:SF 1 "register_operand" "r")))] 2594 (match_operand:SF 1 "register_operand" "r")))]
2123 "TARGET_V850E2V3" 2595 "TARGET_USE_FPU"
2124 "cmpf.s eq,%z0,%z1" 2596 "cmpf.s eq, %z0, %z1"
2125 [(set_attr "length" "4")
2126 (set_attr "cc" "none_0hit")
2127 (set_attr "type" "fpu")])
2128
2129 (define_insn "cmpsf_ne_insn"
2130 [(set (reg:CC_FPU_NE FCC_REGNUM)
2131 (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
2132 (match_operand:SF 1 "register_operand" "r")))]
2133 "TARGET_V850E2V3"
2134 "cmpf.s neq,%z0,%z1"
2135 [(set_attr "length" "4") 2597 [(set_attr "length" "4")
2136 (set_attr "cc" "none_0hit") 2598 (set_attr "cc" "none_0hit")
2137 (set_attr "type" "fpu")]) 2599 (set_attr "type" "fpu")])
2138 2600
2139 ; DF 2601 ; DF
2140 2602
2141 (define_insn "cmpdf_le_insn" 2603 (define_insn "cmpdf_le_insn"
2142 [(set (reg:CC_FPU_LE FCC_REGNUM) 2604 [(set (reg:CC_FPU_LE FCC_REGNUM)
2143 (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r") 2605 (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
2144 (match_operand:DF 1 "even_reg_operand" "r")))] 2606 (match_operand:DF 1 "even_reg_operand" "r")))]
2145 "TARGET_V850E2V3" 2607 "TARGET_USE_FPU"
2146 "cmpf.d le,%z0,%z1" 2608 "cmpf.d le, %z0, %z1"
2147 [(set_attr "length" "4") 2609 [(set_attr "length" "4")
2148 (set_attr "cc" "none_0hit") 2610 (set_attr "cc" "none_0hit")
2149 (set_attr "type" "fpu")]) 2611 (set_attr "type" "fpu")])
2150 2612
2151 (define_insn "cmpdf_lt_insn" 2613 (define_insn "cmpdf_lt_insn"
2152 [(set (reg:CC_FPU_LT FCC_REGNUM) 2614 [(set (reg:CC_FPU_LT FCC_REGNUM)
2153 (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r") 2615 (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
2154 (match_operand:DF 1 "even_reg_operand" "r")))] 2616 (match_operand:DF 1 "even_reg_operand" "r")))]
2155 "TARGET_V850E2V3" 2617 "TARGET_USE_FPU"
2156 "cmpf.d lt,%z0,%z1" 2618 "cmpf.d lt, %z0, %z1"
2157 [(set_attr "length" "4") 2619 [(set_attr "length" "4")
2158 (set_attr "cc" "none_0hit") 2620 (set_attr "cc" "none_0hit")
2159 (set_attr "type" "fpu")]) 2621 (set_attr "type" "fpu")])
2160 2622
2161 (define_insn "cmpdf_ge_insn" 2623 (define_insn "cmpdf_ge_insn"
2162 [(set (reg:CC_FPU_GE FCC_REGNUM) 2624 [(set (reg:CC_FPU_GE FCC_REGNUM)
2163 (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r") 2625 (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
2164 (match_operand:DF 1 "even_reg_operand" "r")))] 2626 (match_operand:DF 1 "even_reg_operand" "r")))]
2165 "TARGET_V850E2V3" 2627 "TARGET_USE_FPU"
2166 "cmpf.d ge,%z0,%z1" 2628 "cmpf.d le, %z1, %z0"
2167 [(set_attr "length" "4") 2629 [(set_attr "length" "4")
2168 (set_attr "cc" "none_0hit") 2630 (set_attr "cc" "none_0hit")
2169 (set_attr "type" "fpu")]) 2631 (set_attr "type" "fpu")])
2170 2632
2171 (define_insn "cmpdf_gt_insn" 2633 (define_insn "cmpdf_gt_insn"
2172 [(set (reg:CC_FPU_GT FCC_REGNUM) 2634 [(set (reg:CC_FPU_GT FCC_REGNUM)
2173 (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r") 2635 (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
2174 (match_operand:DF 1 "even_reg_operand" "r")))] 2636 (match_operand:DF 1 "even_reg_operand" "r")))]
2175 "TARGET_V850E2V3" 2637 "TARGET_USE_FPU"
2176 "cmpf.d gt,%z0,%z1" 2638 "cmpf.d lt, %z1, %z0"
2177 [(set_attr "length" "4") 2639 [(set_attr "length" "4")
2178 (set_attr "cc" "none_0hit") 2640 (set_attr "cc" "none_0hit")
2179 (set_attr "type" "fpu")]) 2641 (set_attr "type" "fpu")])
2180 2642
2181 (define_insn "cmpdf_eq_insn" 2643 (define_insn "cmpdf_eq_insn"
2182 [(set (reg:CC_FPU_EQ FCC_REGNUM) 2644 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2183 (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r") 2645 (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
2184 (match_operand:DF 1 "even_reg_operand" "r")))] 2646 (match_operand:DF 1 "even_reg_operand" "r")))]
2185 "TARGET_V850E2V3" 2647 "TARGET_USE_FPU"
2186 "cmpf.d eq,%z0,%z1" 2648 "cmpf.d eq, %z0, %z1"
2187 [(set_attr "length" "4") 2649 [(set_attr "length" "4")
2188 (set_attr "cc" "none_0hit") 2650 (set_attr "cc" "none_0hit")
2189 (set_attr "type" "fpu")]) 2651 (set_attr "type" "fpu")])
2190
2191 (define_insn "cmpdf_ne_insn"
2192 [(set (reg:CC_FPU_NE FCC_REGNUM)
2193 (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
2194 (match_operand:DF 1 "even_reg_operand" "r")))]
2195 "TARGET_V850E2V3"
2196 "cmpf.d neq,%z0,%z1"
2197 [(set_attr "length" "4")
2198 (set_attr "cc" "none_0hit")
2199 (set_attr "type" "fpu")])
2200
2201 2652
2202 ;; 2653 ;;
2203 ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a 2654 ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a
2204 ;; conditional branch based on a floating-point compare) 2655 ;; conditional branch based on a floating-point compare)
2205 ;; 2656 ;;
2206 2657
2207 (define_insn "trfsr" 2658 (define_insn "trfsr"
2208 [(set (match_operand 0 "" "") (match_operand 1 "" ""))] 2659 [(set (match_operand 0 "" "") (match_operand 1 "" ""))]
2209 "TARGET_V850E2V3 2660 "TARGET_USE_FPU
2210 && GET_MODE(operands[0]) == GET_MODE(operands[1]) 2661 && GET_MODE(operands[0]) == GET_MODE(operands[1])
2211 && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM 2662 && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
2212 && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM 2663 && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
2213 && (GET_MODE(operands[0]) == CC_FPU_LEmode 2664 && (GET_MODE(operands[0]) == CC_FPU_LEmode
2214 || GET_MODE(operands[0]) == CC_FPU_GEmode 2665 || GET_MODE(operands[0]) == CC_FPU_GEmode
2231 [(set (match_operand:SF 0 "register_operand" "=r") 2682 [(set (match_operand:SF 0 "register_operand" "=r")
2232 (if_then_else:SF 2683 (if_then_else:SF
2233 (match_operand 3 "v850_float_z_comparison_operator" "") 2684 (match_operand 3 "v850_float_z_comparison_operator" "")
2234 (match_operand:SF 1 "reg_or_0_operand" "rIG") 2685 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2235 (match_operand:SF 2 "reg_or_0_operand" "rIG")))] 2686 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2236 "TARGET_V850E2V3" 2687 "TARGET_USE_FPU"
2237 "cmovf.s 0,%z1,%z2,%0" 2688 "cmovf.s 0,%z1,%z2,%0"
2238 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit 2689 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2239 2690
2240 (define_insn "movsfcc_nz_insn" 2691 (define_insn "movsfcc_nz_insn"
2241 [(set (match_operand:SF 0 "register_operand" "=r") 2692 [(set (match_operand:SF 0 "register_operand" "=r")
2242 (if_then_else:SF 2693 (if_then_else:SF
2243 (match_operand 3 "v850_float_nz_comparison_operator" "") 2694 (match_operand 3 "v850_float_nz_comparison_operator" "")
2244 (match_operand:SF 1 "reg_or_0_operand" "rIG") 2695 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2245 (match_operand:SF 2 "reg_or_0_operand" "rIG")))] 2696 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2246 "TARGET_V850E2V3" 2697 "TARGET_USE_FPU"
2247 "cmovf.s 0,%z2,%z1,%0" 2698 "cmovf.s 0,%z2,%z1,%0"
2248 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit 2699 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2249 2700
2250 (define_insn "movdfcc_z_insn" 2701 (define_insn "movdfcc_z_insn"
2251 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2702 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2252 (if_then_else:DF 2703 (if_then_else:DF
2253 (match_operand 3 "v850_float_z_comparison_operator" "") 2704 (match_operand 3 "v850_float_z_comparison_operator" "")
2254 (match_operand:DF 1 "even_reg_operand" "r") 2705 (match_operand:DF 1 "even_reg_operand" "r")
2255 (match_operand:DF 2 "even_reg_operand" "r")))] 2706 (match_operand:DF 2 "even_reg_operand" "r")))]
2256 "TARGET_V850E2V3" 2707 "TARGET_USE_FPU"
2257 "cmovf.d 0,%z1,%z2,%0" 2708 "cmovf.d 0,%z1,%z2,%0"
2258 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit 2709 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2259 2710
2260 (define_insn "movdfcc_nz_insn" 2711 (define_insn "movdfcc_nz_insn"
2261 [(set (match_operand:DF 0 "even_reg_operand" "=r") 2712 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2262 (if_then_else:DF 2713 (if_then_else:DF
2263 (match_operand 3 "v850_float_nz_comparison_operator" "") 2714 (match_operand 3 "v850_float_nz_comparison_operator" "")
2264 (match_operand:DF 1 "even_reg_operand" "r") 2715 (match_operand:DF 1 "even_reg_operand" "r")
2265 (match_operand:DF 2 "even_reg_operand" "r")))] 2716 (match_operand:DF 2 "even_reg_operand" "r")))]
2266 "TARGET_V850E2V3" 2717 "TARGET_USE_FPU"
2267 "cmovf.d 0,%z2,%z1,%0" 2718 "cmovf.d 0,%z2,%z1,%0"
2268 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit 2719 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2269 2720
2270 (define_insn "movedfcc_z_zero" 2721 (define_insn "movedfcc_z_zero"
2271 [(set (match_operand:DF 0 "register_operand" "=r") 2722 [(set (match_operand:DF 0 "register_operand" "=r")
2272 (if_then_else:DF 2723 (if_then_else:DF
2273 (match_operand 3 "v850_float_z_comparison_operator" "") 2724 (match_operand 3 "v850_float_z_comparison_operator" "")
2274 (match_operand:DF 1 "reg_or_0_operand" "rIG") 2725 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2275 (match_operand:DF 2 "reg_or_0_operand" "rIG")))] 2726 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2276 "TARGET_V850E2V3" 2727 "TARGET_USE_FPU"
2277 "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0" 2728 "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0"
2278 [(set_attr "length" "8") 2729 [(set_attr "length" "8")
2279 (set_attr "cc" "clobber")]) ;; ??? or none_0hit 2730 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2280 2731
2281 (define_insn "movedfcc_nz_zero" 2732 (define_insn "movedfcc_nz_zero"
2282 [(set (match_operand:DF 0 "register_operand" "=r") 2733 [(set (match_operand:DF 0 "register_operand" "=r")
2283 (if_then_else:DF 2734 (if_then_else:DF
2284 (match_operand 3 "v850_float_nz_comparison_operator" "") 2735 (match_operand 3 "v850_float_nz_comparison_operator" "")
2285 (match_operand:DF 1 "reg_or_0_operand" "rIG") 2736 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2286 (match_operand:DF 2 "reg_or_0_operand" "rIG")))] 2737 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2287 "TARGET_V850E2V3" 2738 "TARGET_USE_FPU"
2288 "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0" 2739 "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0"
2289 [(set_attr "length" "8") 2740 [(set_attr "length" "8")
2290 (set_attr "cc" "clobber")]) ;; ??? or none_0hit 2741 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2291 2742
2292 2743
2307 [(set (reg:SI 3) 2758 [(set (reg:SI 3)
2308 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2759 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2309 (set (mem:SI (plus:SI (reg:SI 3) 2760 (set (mem:SI (plus:SI (reg:SI 3)
2310 (match_operand:SI 2 "immediate_operand" "i"))) 2761 (match_operand:SI 2 "immediate_operand" "i")))
2311 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] 2762 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
2312 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" 2763 "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)"
2313 "* return construct_prepare_instruction (operands[0]); 2764 {
2314 " 2765 return construct_prepare_instruction (operands[0]);
2766 }
2315 [(set_attr "length" "4") 2767 [(set_attr "length" "4")
2316 (set_attr "cc" "clobber")]) 2768 (set_attr "cc" "clobber")])
2317 2769
2318 (define_insn "" 2770 (define_insn ""
2319 [(match_parallel 0 "pattern_is_ok_for_prologue" 2771 [(match_parallel 0 "pattern_is_ok_for_prologue"
2321 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2773 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2322 (set (mem:SI (plus:SI (reg:SI 3) 2774 (set (mem:SI (plus:SI (reg:SI 3)
2323 (match_operand:SI 2 "immediate_operand" "i"))) 2775 (match_operand:SI 2 "immediate_operand" "i")))
2324 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] 2776 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
2325 "TARGET_PROLOG_FUNCTION" 2777 "TARGET_PROLOG_FUNCTION"
2326 "* return construct_save_jarl (operands[0]); 2778 {
2327 " 2779 return construct_save_jarl (operands[0]);
2780 }
2328 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") 2781 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
2329 (const_string "16") 2782 (const_string "16")
2330 (const_string "4"))) 2783 (const_string "4")))
2331 (set_attr "cc" "clobber")]) 2784 (set_attr "cc" "clobber")])
2332 2785
2339 (set (reg:SI 3) 2792 (set (reg:SI 3)
2340 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2793 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2341 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") 2794 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
2342 (mem:SI (plus:SI (reg:SI 3) 2795 (mem:SI (plus:SI (reg:SI 3)
2343 (match_operand:SI 3 "immediate_operand" "i"))))])] 2796 (match_operand:SI 3 "immediate_operand" "i"))))])]
2344 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" 2797 "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)"
2345 "* return construct_dispose_instruction (operands[0]); 2798 {
2346 " 2799 return construct_dispose_instruction (operands[0]);
2800 }
2347 [(set_attr "length" "4") 2801 [(set_attr "length" "4")
2348 (set_attr "cc" "clobber")]) 2802 (set_attr "cc" "clobber")])
2349 2803
2350 ;; This pattern will match a return RTX followed by any number of pop RTXs 2804 ;; This pattern will match a return RTX followed by any number of pop RTXs
2351 ;; and possible a stack adjustment as well. These RTXs will be turned into 2805 ;; and possible a stack adjustment as well. These RTXs will be turned into
2358 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2812 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2359 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") 2813 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
2360 (mem:SI (plus:SI (reg:SI 3) 2814 (mem:SI (plus:SI (reg:SI 3)
2361 (match_operand:SI 3 "immediate_operand" "i"))))])] 2815 (match_operand:SI 3 "immediate_operand" "i"))))])]
2362 "TARGET_PROLOG_FUNCTION" 2816 "TARGET_PROLOG_FUNCTION"
2363 "* return construct_restore_jr (operands[0]); 2817 {
2364 " 2818 return construct_restore_jr (operands[0]);
2819 }
2365 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") 2820 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
2366 (const_string "12") 2821 (const_string "12")
2367 (const_string "4"))) 2822 (const_string "4")))
2368 (set_attr "cc" "clobber")]) 2823 (set_attr "cc" "clobber")])
2369 2824
2370 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION. 2825 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION.
2371 (define_insn "callt_save_interrupt" 2826 (define_insn "callt_save_interrupt"
2372 [(unspec_volatile [(const_int 0)] 2)] 2827 [(unspec_volatile [(const_int 0)] 2)]
2373 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" 2828 "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
2374 ;; The CALLT instruction stores the next address of CALLT to CTPC register 2829 ;; The CALLT instruction stores the next address of CALLT to CTPC register
2375 ;; without saving its previous value. So if the interrupt handler 2830 ;; without saving its previous value. So if the interrupt handler
2376 ;; or its caller could possibly execute the CALLT insn, save_interrupt 2831 ;; or its caller could possibly execute the CALLT insn, save_interrupt
2377 ;; MUST NOT be called via CALLT. 2832 ;; MUST NOT be called via CALLT.
2378 "* 2833 {
2379 { 2834 output_asm_insn ("addi -28, sp, sp", operands);
2380 output_asm_insn (\"addi -28, sp, sp\", operands); 2835 output_asm_insn ("st.w r1, 24[sp]", operands);
2381 output_asm_insn (\"st.w r1, 24[sp]\", operands); 2836 output_asm_insn ("st.w r10, 12[sp]", operands);
2382 output_asm_insn (\"st.w r10, 12[sp]\", operands); 2837 output_asm_insn ("st.w r11, 16[sp]", operands);
2383 output_asm_insn (\"st.w r11, 16[sp]\", operands); 2838 output_asm_insn ("stsr ctpc, r10", operands);
2384 output_asm_insn (\"stsr ctpc, r10\", operands); 2839 output_asm_insn ("st.w r10, 20[sp]", operands);
2385 output_asm_insn (\"st.w r10, 20[sp]\", operands); 2840 output_asm_insn ("stsr ctpsw, r10", operands);
2386 output_asm_insn (\"stsr ctpsw, r10\", operands); 2841 output_asm_insn ("st.w r10, 24[sp]", operands);
2387 output_asm_insn (\"st.w r10, 24[sp]\", operands); 2842 output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands);
2388 output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands); 2843 return "";
2389 return \"\"; 2844 }
2390 }"
2391 [(set_attr "length" "26") 2845 [(set_attr "length" "26")
2392 (set_attr "cc" "clobber")]) 2846 (set_attr "cc" "clobber")])
2393 2847
2394 (define_insn "callt_return_interrupt" 2848 (define_insn "callt_return_interrupt"
2395 [(unspec_volatile [(const_int 0)] 3)] 2849 [(unspec_volatile [(const_int 0)] 3)]
2396 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" 2850 "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
2397 "callt ctoff(__callt_return_interrupt)" 2851 "callt ctoff(__callt_return_interrupt)"
2398 [(set_attr "length" "2") 2852 [(set_attr "length" "2")
2399 (set_attr "cc" "clobber")]) 2853 (set_attr "cc" "clobber")])
2400 2854
2401 (define_insn "save_interrupt" 2855 (define_insn "save_interrupt"
2404 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4)) 2858 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4))
2405 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1)) 2859 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))
2406 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10)) 2860 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
2407 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))] 2861 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
2408 "" 2862 ""
2409 "*
2410 { 2863 {
2411 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) 2864 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2412 return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\"; 2865 return "addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10";
2413 else 2866 else
2414 { 2867 {
2415 output_asm_insn (\"addi -20, sp, sp\", operands); 2868 output_asm_insn ("addi -20, sp, sp", operands);
2416 output_asm_insn (\"st.w r11, 16[sp]\", operands); 2869 output_asm_insn ("st.w r11, 16[sp]", operands);
2417 output_asm_insn (\"st.w r10, 12[sp]\", operands); 2870 output_asm_insn ("st.w r10, 12[sp]", operands);
2418 output_asm_insn (\"st.w ep, 0[sp]\", operands); 2871 output_asm_insn ("st.w ep, 0[sp]", operands);
2419 output_asm_insn (\"st.w gp, 4[sp]\", operands); 2872 output_asm_insn ("st.w gp, 4[sp]", operands);
2420 output_asm_insn (\"st.w r1, 8[sp]\", operands); 2873 output_asm_insn ("st.w r1, 8[sp]", operands);
2421 output_asm_insn (\"movhi hi(__ep), r0, ep\", operands); 2874 output_asm_insn ("movhi hi(__ep), r0, ep", operands);
2422 output_asm_insn (\"movea lo(__ep), ep, ep\", operands); 2875 output_asm_insn ("movea lo(__ep), ep, ep", operands);
2423 output_asm_insn (\"movhi hi(__gp), r0, gp\", operands); 2876 output_asm_insn ("movhi hi(__gp), r0, gp", operands);
2424 output_asm_insn (\"movea lo(__gp), gp, gp\", operands); 2877 output_asm_insn ("movea lo(__gp), gp, gp", operands);
2425 return \"\"; 2878 return "";
2426 } 2879 }
2427 }" 2880 }
2428 [(set (attr "length") 2881 [(set (attr "length")
2429 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) 2882 (if_then_else (match_test "TARGET_LONG_CALLS")
2430 (const_int 10) 2883 (const_int 10)
2431 (const_int 34))) 2884 (const_int 34)))
2432 (set_attr "cc" "clobber")]) 2885 (set_attr "cc" "clobber")])
2433 2886
2434 ;; Restore r1, r4, r10, and return from the interrupt 2887 ;; Restore r1, r4, r10, and return from the interrupt
2439 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12)))) 2892 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
2440 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8)))) 2893 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
2441 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4)))) 2894 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
2442 (set (reg:SI 30) (mem:SI (reg:SI 3)))] 2895 (set (reg:SI 30) (mem:SI (reg:SI 3)))]
2443 "" 2896 ""
2444 "*
2445 { 2897 {
2446 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) 2898 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2447 return \"jr __return_interrupt\"; 2899 return "jr __return_interrupt";
2448 else 2900 else
2449 { 2901 {
2450 output_asm_insn (\"ld.w 0[sp], ep\", operands); 2902 output_asm_insn ("ld.w 0[sp], ep", operands);
2451 output_asm_insn (\"ld.w 4[sp], gp\", operands); 2903 output_asm_insn ("ld.w 4[sp], gp", operands);
2452 output_asm_insn (\"ld.w 8[sp], r1\", operands); 2904 output_asm_insn ("ld.w 8[sp], r1", operands);
2453 output_asm_insn (\"ld.w 12[sp], r10\", operands); 2905 output_asm_insn ("ld.w 12[sp], r10", operands);
2454 output_asm_insn (\"ld.w 16[sp], r11\", operands); 2906 output_asm_insn ("ld.w 16[sp], r11", operands);
2455 output_asm_insn (\"addi 20, sp, sp\", operands); 2907 output_asm_insn ("addi 20, sp, sp", operands);
2456 output_asm_insn (\"reti\", operands); 2908 output_asm_insn ("reti", operands);
2457 return \"\"; 2909 return "";
2458 } 2910 }
2459 }" 2911 }
2460 [(set (attr "length") 2912 [(set (attr "length")
2461 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) 2913 (if_then_else (match_test "TARGET_LONG_CALLS")
2462 (const_int 4) 2914 (const_int 4)
2463 (const_int 24))) 2915 (const_int 24)))
2464 (set_attr "cc" "clobber")]) 2916 (set_attr "cc" "clobber")])
2465 2917
2466 ;; Save all registers except for the registers saved in save_interrupt when 2918 ;; Save all registers except for the registers saved in save_interrupt when
2470 ;; This is needed because the rest of the compiler is not ready to handle 2922 ;; This is needed because the rest of the compiler is not ready to handle
2471 ;; insns this complicated. 2923 ;; insns this complicated.
2472 2924
2473 (define_insn "callt_save_all_interrupt" 2925 (define_insn "callt_save_all_interrupt"
2474 [(unspec_volatile [(const_int 0)] 0)] 2926 [(unspec_volatile [(const_int 0)] 0)]
2475 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" 2927 "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
2476 "callt ctoff(__callt_save_all_interrupt)" 2928 "callt ctoff(__callt_save_all_interrupt)"
2477 [(set_attr "length" "2") 2929 [(set_attr "length" "2")
2478 (set_attr "cc" "none")]) 2930 (set_attr "cc" "none")])
2479 2931
2480 (define_insn "save_all_interrupt" 2932 (define_insn "save_all_interrupt"
2481 [(unspec_volatile [(const_int 0)] 0)] 2933 [(unspec_volatile [(const_int 0)] 0)]
2482 "" 2934 ""
2483 "*
2484 { 2935 {
2485 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) 2936 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2486 return \"jarl __save_all_interrupt,r10\"; 2937 return "jarl __save_all_interrupt,r10";
2487 2938
2488 output_asm_insn (\"addi -120, sp, sp\", operands); 2939 output_asm_insn ("addi -120, sp, sp", operands);
2489 2940
2490 if (TARGET_EP) 2941 if (TARGET_EP)
2491 { 2942 {
2492 output_asm_insn (\"mov ep, r1\", operands); 2943 output_asm_insn ("mov ep, r1", operands);
2493 output_asm_insn (\"mov sp, ep\", operands); 2944 output_asm_insn ("mov sp, ep", operands);
2494 output_asm_insn (\"sst.w r31, 116[ep]\", operands); 2945 output_asm_insn ("sst.w r31, 116[ep]", operands);
2495 output_asm_insn (\"sst.w r2, 112[ep]\", operands); 2946 output_asm_insn ("sst.w r2, 112[ep]", operands);
2496 output_asm_insn (\"sst.w gp, 108[ep]\", operands); 2947 output_asm_insn ("sst.w gp, 108[ep]", operands);
2497 output_asm_insn (\"sst.w r6, 104[ep]\", operands); 2948 output_asm_insn ("sst.w r6, 104[ep]", operands);
2498 output_asm_insn (\"sst.w r7, 100[ep]\", operands); 2949 output_asm_insn ("sst.w r7, 100[ep]", operands);
2499 output_asm_insn (\"sst.w r8, 96[ep]\", operands); 2950 output_asm_insn ("sst.w r8, 96[ep]", operands);
2500 output_asm_insn (\"sst.w r9, 92[ep]\", operands); 2951 output_asm_insn ("sst.w r9, 92[ep]", operands);
2501 output_asm_insn (\"sst.w r11, 88[ep]\", operands); 2952 output_asm_insn ("sst.w r11, 88[ep]", operands);
2502 output_asm_insn (\"sst.w r12, 84[ep]\", operands); 2953 output_asm_insn ("sst.w r12, 84[ep]", operands);
2503 output_asm_insn (\"sst.w r13, 80[ep]\", operands); 2954 output_asm_insn ("sst.w r13, 80[ep]", operands);
2504 output_asm_insn (\"sst.w r14, 76[ep]\", operands); 2955 output_asm_insn ("sst.w r14, 76[ep]", operands);
2505 output_asm_insn (\"sst.w r15, 72[ep]\", operands); 2956 output_asm_insn ("sst.w r15, 72[ep]", operands);
2506 output_asm_insn (\"sst.w r16, 68[ep]\", operands); 2957 output_asm_insn ("sst.w r16, 68[ep]", operands);
2507 output_asm_insn (\"sst.w r17, 64[ep]\", operands); 2958 output_asm_insn ("sst.w r17, 64[ep]", operands);
2508 output_asm_insn (\"sst.w r18, 60[ep]\", operands); 2959 output_asm_insn ("sst.w r18, 60[ep]", operands);
2509 output_asm_insn (\"sst.w r19, 56[ep]\", operands); 2960 output_asm_insn ("sst.w r19, 56[ep]", operands);
2510 output_asm_insn (\"sst.w r20, 52[ep]\", operands); 2961 output_asm_insn ("sst.w r20, 52[ep]", operands);
2511 output_asm_insn (\"sst.w r21, 48[ep]\", operands); 2962 output_asm_insn ("sst.w r21, 48[ep]", operands);
2512 output_asm_insn (\"sst.w r22, 44[ep]\", operands); 2963 output_asm_insn ("sst.w r22, 44[ep]", operands);
2513 output_asm_insn (\"sst.w r23, 40[ep]\", operands); 2964 output_asm_insn ("sst.w r23, 40[ep]", operands);
2514 output_asm_insn (\"sst.w r24, 36[ep]\", operands); 2965 output_asm_insn ("sst.w r24, 36[ep]", operands);
2515 output_asm_insn (\"sst.w r25, 32[ep]\", operands); 2966 output_asm_insn ("sst.w r25, 32[ep]", operands);
2516 output_asm_insn (\"sst.w r26, 28[ep]\", operands); 2967 output_asm_insn ("sst.w r26, 28[ep]", operands);
2517 output_asm_insn (\"sst.w r27, 24[ep]\", operands); 2968 output_asm_insn ("sst.w r27, 24[ep]", operands);
2518 output_asm_insn (\"sst.w r28, 20[ep]\", operands); 2969 output_asm_insn ("sst.w r28, 20[ep]", operands);
2519 output_asm_insn (\"sst.w r29, 16[ep]\", operands); 2970 output_asm_insn ("sst.w r29, 16[ep]", operands);
2520 output_asm_insn (\"mov r1, ep\", operands); 2971 output_asm_insn ("mov r1, ep", operands);
2521 } 2972 }
2522 else 2973 else
2523 { 2974 {
2524 output_asm_insn (\"st.w r31, 116[sp]\", operands); 2975 output_asm_insn ("st.w r31, 116[sp]", operands);
2525 output_asm_insn (\"st.w r2, 112[sp]\", operands); 2976 output_asm_insn ("st.w r2, 112[sp]", operands);
2526 output_asm_insn (\"st.w gp, 108[sp]\", operands); 2977 output_asm_insn ("st.w gp, 108[sp]", operands);
2527 output_asm_insn (\"st.w r6, 104[sp]\", operands); 2978 output_asm_insn ("st.w r6, 104[sp]", operands);
2528 output_asm_insn (\"st.w r7, 100[sp]\", operands); 2979 output_asm_insn ("st.w r7, 100[sp]", operands);
2529 output_asm_insn (\"st.w r8, 96[sp]\", operands); 2980 output_asm_insn ("st.w r8, 96[sp]", operands);
2530 output_asm_insn (\"st.w r9, 92[sp]\", operands); 2981 output_asm_insn ("st.w r9, 92[sp]", operands);
2531 output_asm_insn (\"st.w r11, 88[sp]\", operands); 2982 output_asm_insn ("st.w r11, 88[sp]", operands);
2532 output_asm_insn (\"st.w r12, 84[sp]\", operands); 2983 output_asm_insn ("st.w r12, 84[sp]", operands);
2533 output_asm_insn (\"st.w r13, 80[sp]\", operands); 2984 output_asm_insn ("st.w r13, 80[sp]", operands);
2534 output_asm_insn (\"st.w r14, 76[sp]\", operands); 2985 output_asm_insn ("st.w r14, 76[sp]", operands);
2535 output_asm_insn (\"st.w r15, 72[sp]\", operands); 2986 output_asm_insn ("st.w r15, 72[sp]", operands);
2536 output_asm_insn (\"st.w r16, 68[sp]\", operands); 2987 output_asm_insn ("st.w r16, 68[sp]", operands);
2537 output_asm_insn (\"st.w r17, 64[sp]\", operands); 2988 output_asm_insn ("st.w r17, 64[sp]", operands);
2538 output_asm_insn (\"st.w r18, 60[sp]\", operands); 2989 output_asm_insn ("st.w r18, 60[sp]", operands);
2539 output_asm_insn (\"st.w r19, 56[sp]\", operands); 2990 output_asm_insn ("st.w r19, 56[sp]", operands);
2540 output_asm_insn (\"st.w r20, 52[sp]\", operands); 2991 output_asm_insn ("st.w r20, 52[sp]", operands);
2541 output_asm_insn (\"st.w r21, 48[sp]\", operands); 2992 output_asm_insn ("st.w r21, 48[sp]", operands);
2542 output_asm_insn (\"st.w r22, 44[sp]\", operands); 2993 output_asm_insn ("st.w r22, 44[sp]", operands);
2543 output_asm_insn (\"st.w r23, 40[sp]\", operands); 2994 output_asm_insn ("st.w r23, 40[sp]", operands);
2544 output_asm_insn (\"st.w r24, 36[sp]\", operands); 2995 output_asm_insn ("st.w r24, 36[sp]", operands);
2545 output_asm_insn (\"st.w r25, 32[sp]\", operands); 2996 output_asm_insn ("st.w r25, 32[sp]", operands);
2546 output_asm_insn (\"st.w r26, 28[sp]\", operands); 2997 output_asm_insn ("st.w r26, 28[sp]", operands);
2547 output_asm_insn (\"st.w r27, 24[sp]\", operands); 2998 output_asm_insn ("st.w r27, 24[sp]", operands);
2548 output_asm_insn (\"st.w r28, 20[sp]\", operands); 2999 output_asm_insn ("st.w r28, 20[sp]", operands);
2549 output_asm_insn (\"st.w r29, 16[sp]\", operands); 3000 output_asm_insn ("st.w r29, 16[sp]", operands);
2550 } 3001 }
2551 3002
2552 return \"\"; 3003 return "";
2553 }" 3004 }
2554 [(set (attr "length") 3005 [(set (attr "length")
2555 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) 3006 (if_then_else (match_test "TARGET_LONG_CALLS")
2556 (const_int 4) 3007 (const_int 4)
2557 (const_int 62) 3008 (const_int 62)
2558 )) 3009 ))
2559 (set_attr "cc" "clobber")]) 3010 (set_attr "cc" "clobber")])
2560 3011
2571 ;; This is needed because the rest of the compiler is not ready to handle 3022 ;; This is needed because the rest of the compiler is not ready to handle
2572 ;; insns this complicated. 3023 ;; insns this complicated.
2573 3024
2574 (define_insn "callt_restore_all_interrupt" 3025 (define_insn "callt_restore_all_interrupt"
2575 [(unspec_volatile [(const_int 0)] 1)] 3026 [(unspec_volatile [(const_int 0)] 1)]
2576 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" 3027 "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
2577 "callt ctoff(__callt_restore_all_interrupt)" 3028 "callt ctoff(__callt_restore_all_interrupt)"
2578 [(set_attr "length" "2") 3029 [(set_attr "length" "2")
2579 (set_attr "cc" "none")]) 3030 (set_attr "cc" "none")])
2580 3031
2581 (define_insn "restore_all_interrupt" 3032 (define_insn "restore_all_interrupt"
2582 [(unspec_volatile [(const_int 0)] 1)] 3033 [(unspec_volatile [(const_int 0)] 1)]
2583 "" 3034 ""
2584 "*
2585 { 3035 {
2586 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) 3036 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2587 return \"jarl __restore_all_interrupt,r10\"; 3037 return "jarl __restore_all_interrupt,r10";
2588 3038
2589 if (TARGET_EP) 3039 if (TARGET_EP)
2590 { 3040 {
2591 output_asm_insn (\"mov ep, r1\", operands); 3041 output_asm_insn ("mov ep, r1", operands);
2592 output_asm_insn (\"mov sp, ep\", operands); 3042 output_asm_insn ("mov sp, ep", operands);
2593 output_asm_insn (\"sld.w 116[ep], r31\", operands); 3043 output_asm_insn ("sld.w 116[ep], r31", operands);
2594 output_asm_insn (\"sld.w 112[ep], r2\", operands); 3044 output_asm_insn ("sld.w 112[ep], r2", operands);
2595 output_asm_insn (\"sld.w 108[ep], gp\", operands); 3045 output_asm_insn ("sld.w 108[ep], gp", operands);
2596 output_asm_insn (\"sld.w 104[ep], r6\", operands); 3046 output_asm_insn ("sld.w 104[ep], r6", operands);
2597 output_asm_insn (\"sld.w 100[ep], r7\", operands); 3047 output_asm_insn ("sld.w 100[ep], r7", operands);
2598 output_asm_insn (\"sld.w 96[ep], r8\", operands); 3048 output_asm_insn ("sld.w 96[ep], r8", operands);
2599 output_asm_insn (\"sld.w 92[ep], r9\", operands); 3049 output_asm_insn ("sld.w 92[ep], r9", operands);
2600 output_asm_insn (\"sld.w 88[ep], r11\", operands); 3050 output_asm_insn ("sld.w 88[ep], r11", operands);
2601 output_asm_insn (\"sld.w 84[ep], r12\", operands); 3051 output_asm_insn ("sld.w 84[ep], r12", operands);
2602 output_asm_insn (\"sld.w 80[ep], r13\", operands); 3052 output_asm_insn ("sld.w 80[ep], r13", operands);
2603 output_asm_insn (\"sld.w 76[ep], r14\", operands); 3053 output_asm_insn ("sld.w 76[ep], r14", operands);
2604 output_asm_insn (\"sld.w 72[ep], r15\", operands); 3054 output_asm_insn ("sld.w 72[ep], r15", operands);
2605 output_asm_insn (\"sld.w 68[ep], r16\", operands); 3055 output_asm_insn ("sld.w 68[ep], r16", operands);
2606 output_asm_insn (\"sld.w 64[ep], r17\", operands); 3056 output_asm_insn ("sld.w 64[ep], r17", operands);
2607 output_asm_insn (\"sld.w 60[ep], r18\", operands); 3057 output_asm_insn ("sld.w 60[ep], r18", operands);
2608 output_asm_insn (\"sld.w 56[ep], r19\", operands); 3058 output_asm_insn ("sld.w 56[ep], r19", operands);
2609 output_asm_insn (\"sld.w 52[ep], r20\", operands); 3059 output_asm_insn ("sld.w 52[ep], r20", operands);
2610 output_asm_insn (\"sld.w 48[ep], r21\", operands); 3060 output_asm_insn ("sld.w 48[ep], r21", operands);
2611 output_asm_insn (\"sld.w 44[ep], r22\", operands); 3061 output_asm_insn ("sld.w 44[ep], r22", operands);
2612 output_asm_insn (\"sld.w 40[ep], r23\", operands); 3062 output_asm_insn ("sld.w 40[ep], r23", operands);
2613 output_asm_insn (\"sld.w 36[ep], r24\", operands); 3063 output_asm_insn ("sld.w 36[ep], r24", operands);
2614 output_asm_insn (\"sld.w 32[ep], r25\", operands); 3064 output_asm_insn ("sld.w 32[ep], r25", operands);
2615 output_asm_insn (\"sld.w 28[ep], r26\", operands); 3065 output_asm_insn ("sld.w 28[ep], r26", operands);
2616 output_asm_insn (\"sld.w 24[ep], r27\", operands); 3066 output_asm_insn ("sld.w 24[ep], r27", operands);
2617 output_asm_insn (\"sld.w 20[ep], r28\", operands); 3067 output_asm_insn ("sld.w 20[ep], r28", operands);
2618 output_asm_insn (\"sld.w 16[ep], r29\", operands); 3068 output_asm_insn ("sld.w 16[ep], r29", operands);
2619 output_asm_insn (\"mov r1, ep\", operands); 3069 output_asm_insn ("mov r1, ep", operands);
2620 } 3070 }
2621 else 3071 else
2622 { 3072 {
2623 output_asm_insn (\"ld.w 116[sp], r31\", operands); 3073 output_asm_insn ("ld.w 116[sp], r31", operands);
2624 output_asm_insn (\"ld.w 112[sp], r2\", operands); 3074 output_asm_insn ("ld.w 112[sp], r2", operands);
2625 output_asm_insn (\"ld.w 108[sp], gp\", operands); 3075 output_asm_insn ("ld.w 108[sp], gp", operands);
2626 output_asm_insn (\"ld.w 104[sp], r6\", operands); 3076 output_asm_insn ("ld.w 104[sp], r6", operands);
2627 output_asm_insn (\"ld.w 100[sp], r7\", operands); 3077 output_asm_insn ("ld.w 100[sp], r7", operands);
2628 output_asm_insn (\"ld.w 96[sp], r8\", operands); 3078 output_asm_insn ("ld.w 96[sp], r8", operands);
2629 output_asm_insn (\"ld.w 92[sp], r9\", operands); 3079 output_asm_insn ("ld.w 92[sp], r9", operands);
2630 output_asm_insn (\"ld.w 88[sp], r11\", operands); 3080 output_asm_insn ("ld.w 88[sp], r11", operands);
2631 output_asm_insn (\"ld.w 84[sp], r12\", operands); 3081 output_asm_insn ("ld.w 84[sp], r12", operands);
2632 output_asm_insn (\"ld.w 80[sp], r13\", operands); 3082 output_asm_insn ("ld.w 80[sp], r13", operands);
2633 output_asm_insn (\"ld.w 76[sp], r14\", operands); 3083 output_asm_insn ("ld.w 76[sp], r14", operands);
2634 output_asm_insn (\"ld.w 72[sp], r15\", operands); 3084 output_asm_insn ("ld.w 72[sp], r15", operands);
2635 output_asm_insn (\"ld.w 68[sp], r16\", operands); 3085 output_asm_insn ("ld.w 68[sp], r16", operands);
2636 output_asm_insn (\"ld.w 64[sp], r17\", operands); 3086 output_asm_insn ("ld.w 64[sp], r17", operands);
2637 output_asm_insn (\"ld.w 60[sp], r18\", operands); 3087 output_asm_insn ("ld.w 60[sp], r18", operands);
2638 output_asm_insn (\"ld.w 56[sp], r19\", operands); 3088 output_asm_insn ("ld.w 56[sp], r19", operands);
2639 output_asm_insn (\"ld.w 52[sp], r20\", operands); 3089 output_asm_insn ("ld.w 52[sp], r20", operands);
2640 output_asm_insn (\"ld.w 48[sp], r21\", operands); 3090 output_asm_insn ("ld.w 48[sp], r21", operands);
2641 output_asm_insn (\"ld.w 44[sp], r22\", operands); 3091 output_asm_insn ("ld.w 44[sp], r22", operands);
2642 output_asm_insn (\"ld.w 40[sp], r23\", operands); 3092 output_asm_insn ("ld.w 40[sp], r23", operands);
2643 output_asm_insn (\"ld.w 36[sp], r24\", operands); 3093 output_asm_insn ("ld.w 36[sp], r24", operands);
2644 output_asm_insn (\"ld.w 32[sp], r25\", operands); 3094 output_asm_insn ("ld.w 32[sp], r25", operands);
2645 output_asm_insn (\"ld.w 28[sp], r26\", operands); 3095 output_asm_insn ("ld.w 28[sp], r26", operands);
2646 output_asm_insn (\"ld.w 24[sp], r27\", operands); 3096 output_asm_insn ("ld.w 24[sp], r27", operands);
2647 output_asm_insn (\"ld.w 20[sp], r28\", operands); 3097 output_asm_insn ("ld.w 20[sp], r28", operands);
2648 output_asm_insn (\"ld.w 16[sp], r29\", operands); 3098 output_asm_insn ("ld.w 16[sp], r29", operands);
2649 } 3099 }
2650 output_asm_insn (\"addi 120, sp, sp\", operands); 3100 output_asm_insn ("addi 120, sp, sp", operands);
2651 return \"\"; 3101 return "";
2652 }" 3102 }
2653 [(set (attr "length") 3103 [(set (attr "length")
2654 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) 3104 (if_then_else (match_test "TARGET_LONG_CALLS")
2655 (const_int 4) 3105 (const_int 4)
2656 (const_int 62) 3106 (const_int 62)
2657 )) 3107 ))
2658 (set_attr "cc" "clobber")]) 3108 (set_attr "cc" "clobber")])
2659 3109
2661 [(unspec_volatile [(const_int 0)] 1)] 3111 [(unspec_volatile [(const_int 0)] 1)]
2662 "TARGET_V850 && ! TARGET_LONG_CALLS" 3112 "TARGET_V850 && ! TARGET_LONG_CALLS"
2663 "jarl __restore_all_interrupt,r10" 3113 "jarl __restore_all_interrupt,r10"
2664 [(set_attr "length" "4") 3114 [(set_attr "length" "4")
2665 (set_attr "cc" "clobber")]) 3115 (set_attr "cc" "clobber")])
2666
2667