Mercurial > hg > CbC > CbC_gcc
diff gcc/config/v850/v850.md @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
line wrap: on
line diff
--- a/gcc/config/v850/v850.md Sun Aug 21 07:07:55 2011 +0900 +++ b/gcc/config/v850/v850.md Fri Oct 27 22:46:09 2017 +0900 @@ -1,6 +1,5 @@ ;; GCC machine description for NEC V850 -;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010 -;; Free Software Foundation, Inc. +;; Copyright (C) 1996-2017 Free Software Foundation, Inc. ;; Contributed by Jeff Law (law@cygnus.com). ;; This file is part of GCC. @@ -40,10 +39,12 @@ [(ZERO_REGNUM 0) ; constant zero (SP_REGNUM 3) ; Stack Pointer (GP_REGNUM 4) ; GP Pointer + (RV_REGNUM 10) ; Return value register (EP_REGNUM 30) ; EP pointer (LP_REGNUM 31) ; Return address register (CC_REGNUM 32) ; Condition code pseudo register (FCC_REGNUM 33) ; Floating Condition code pseudo register + (UNSPEC_LOOP 200) ; loop counter ] ) @@ -60,18 +61,20 @@ (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other" (const_string "other")) -(define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3" - (cond [(ne (symbol_ref "TARGET_V850") (const_int 0)) - (const_string "v850") - (ne (symbol_ref "TARGET_V850E") (const_int 0)) - (const_string "v850e") - (ne (symbol_ref "TARGET_V850E1") (const_int 0)) - (const_string "v850e1") - (ne (symbol_ref "TARGET_V850E2") (const_int 0)) - (const_string "v850e2") - (ne (symbol_ref "TARGET_V850E2") (const_int 0)) - (const_string "v850e2v3")] - (const_string "none"))) +(define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3,v850e3v5" + (cond [(match_test "TARGET_V850") + (const_string "v850") + (match_test "TARGET_V850E") + (const_string "v850e") + (match_test "TARGET_V850E1") + (const_string "v850e1") + (match_test "TARGET_V850E2") + (const_string "v850e2") + (match_test "TARGET_V850E2V3") + (const_string "v850e2v3") + (match_test "TARGET_V850E3V5") + (const_string "v850e3v5")] + (const_string "none"))) ;; Condition code settings. ;; none - insn does not affect cc @@ -110,7 +113,7 @@ (sign_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand 2 "disp23_operand" "W")))))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "ld.b %2[%1],%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -120,7 +123,7 @@ (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand 2 "disp23_operand" "W")))))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "ld.bu %2[%1],%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -130,7 +133,7 @@ (sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand 2 "disp23_operand" "W")))))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "ld.h %2[%1],%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -140,7 +143,7 @@ (zero_extend:SI (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand 2 "disp23_operand" "W")))))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "ld.hu %2[%1],%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -149,7 +152,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand 2 "disp23_operand" "W"))))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "ld.w %2[%1],%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -158,7 +161,7 @@ [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r") (match_operand 1 "disp23_operand" "W"))) (match_operand:QI 2 "register_operand" "r"))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "st.b %2,%1[%0]" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -167,7 +170,7 @@ [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r") (match_operand 1 "disp23_operand" "W"))) (match_operand:HI 2 "register_operand" "r"))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "st.h %2,%1[%0]" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -176,30 +179,68 @@ [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") (match_operand 1 "disp23_operand" "W"))) (match_operand:SI 2 "register_operand" "r"))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "st.w %2,%1[%0]" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) + +;; movdi + +(define_expand "movdi" + [(set (match_operand:DI 0 "general_operand") + (match_operand:DI 1 "general_operand"))] + "TARGET_V850E3V5_UP" + { + /* One of the ops has to be in a register or 0. */ + if (!register_operand (operand0, DImode) + && !register_operand (operand1, DImode)) + operands[1] = copy_to_mode_reg (DImode, operand1); + + if (register_operand (operand0, DImode) + && (CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1]))) + { + int i; + + for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD) + emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i), + simplify_gen_subreg (SImode, operands[1], DImode, i)); + DONE; + } + } +) + +(define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,e!r,m") + (match_operand:DI 1 "nonimmediate_operand" "r,m,e!r"))] + "TARGET_V850E3V5_UP + || (register_operand (operands[0], DImode) && register_operand (operands[1], DImode))" + { return v850_gen_movdi (operands); } + [(set_attr "length" "4,12,12") + (set_attr "cc" "none_0hit") + (set_attr "type" "other,load,store")] +) + ;; movqi (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" - " -{ - /* One of the ops has to be in a register or 0 */ - if (!register_operand (operand0, QImode) - && !reg_or_0_operand (operand1, QImode)) - operands[1] = copy_to_mode_reg (QImode, operand1); -}") + { + /* One of the ops has to be in a register or 0 */ + if (!register_operand (operand0, QImode) + && !reg_or_0_operand (operand1, QImode)) + operands[1] = copy_to_mode_reg (QImode, operand1); + }) (define_insn "*movqi_internal" - [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m") + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m") (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)" - "* return output_move_single (operands);" +{ + return output_move_single (operands); +} [(set_attr "length" "2,4,2,2,4,4,4") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,load,other,load,store,store")]) @@ -210,20 +251,21 @@ [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" - " { /* One of the ops has to be in a register or 0 */ if (!register_operand (operand0, HImode) && !reg_or_0_operand (operand1, HImode)) operands[1] = copy_to_mode_reg (HImode, operand1); -}") +}) (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m") (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)" - "* return output_move_single (operands);" +{ + return output_move_single (operands); +} [(set_attr "length" "2,4,2,2,4,4,4") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,load,other,load,store,store")]) @@ -232,7 +274,7 @@ (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (match_operand 1 "" "")))] + (high:SI (match_operand 1 "immediate_operand" "i")))] "" "movhi hi(%1),%.,%0" [(set_attr "length" "4") @@ -253,38 +295,36 @@ [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" - " -{ - /* One of the ops has to be in a register or 0 */ - if (!register_operand (operand0, SImode) - && !reg_or_0_operand (operand1, SImode)) - operands[1] = copy_to_mode_reg (SImode, operand1); + { + /* One of the ops has to be in a register or 0 */ + if (!register_operand (operand0, SImode) + && !reg_or_0_operand (operand1, SImode)) + operands[1] = copy_to_mode_reg (SImode, operand1); - /* Some constants, as well as symbolic operands - must be done with HIGH & LO_SUM patterns. */ - if (CONSTANT_P (operands[1]) - && GET_CODE (operands[1]) != HIGH - && ! (TARGET_V850E || TARGET_V850E2_ALL) - && !special_symbolref_operand (operands[1], VOIDmode) - && !(GET_CODE (operands[1]) == CONST_INT - && (CONST_OK_FOR_J (INTVAL (operands[1])) - || CONST_OK_FOR_K (INTVAL (operands[1])) - || CONST_OK_FOR_L (INTVAL (operands[1]))))) - { - rtx temp; + /* Some constants, as well as symbolic operands + must be done with HIGH & LO_SUM patterns. */ + if (CONSTANT_P (operands[1]) + && GET_CODE (operands[1]) != HIGH + && ! (TARGET_V850E_UP) + && !special_symbolref_operand (operands[1], VOIDmode) + && !(GET_CODE (operands[1]) == CONST_INT + && (CONST_OK_FOR_J (INTVAL (operands[1])) + || CONST_OK_FOR_K (INTVAL (operands[1])) + || CONST_OK_FOR_L (INTVAL (operands[1]))))) + { + rtx temp; - if (reload_in_progress || reload_completed) - temp = operands[0]; - else - temp = gen_reg_rtx (SImode); + if (reload_in_progress || reload_completed) + temp = operands[0]; + else + temp = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (SImode, temp, - gen_rtx_HIGH (SImode, operand1))); - emit_insn (gen_rtx_SET (SImode, operand0, - gen_rtx_LO_SUM (SImode, temp, operand1))); - DONE; - } -}") + emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (SImode, operand1))); + emit_insn (gen_rtx_SET (operand0, + gen_rtx_LO_SUM (SImode, temp, operand1))); + DONE; + } + }) ;; This is the same as the following pattern, except that it includes ;; support for arbitrary 32-bit immediates. @@ -294,32 +334,38 @@ ;; upper part with hi, and then put the lower part in the load/store insn. (define_insn "*movsi_internal_v850e" - [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m,r") (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))] - "(TARGET_V850E || TARGET_V850E2_ALL) + "(TARGET_V850E_UP) && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" - "* return output_move_single (operands);" +{ + return output_move_single (operands); +} [(set_attr "length" "2,4,4,2,2,4,4,4,4,6") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,load,other,load,other,store,store,other")]) (define_insn "*movsi_internal" - [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m") (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))] "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)" - "* return output_move_single (operands);" +{ + return output_move_single (operands); +} [(set_attr "length" "2,4,4,2,2,4,4,4,4") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,load,other,load,store,store,other")]) (define_insn "*movsf_internal" - [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r") + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,Q,r,m,m,r") (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))] "register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)" - "* return output_move_single (operands);" +{ + return output_move_single (operands); +} [(set_attr "length" "2,4,4,8,2,2,4,4,4,8") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,other,load,other,load,store,store,other")]) @@ -380,12 +426,11 @@ (compare (match_operand:SI 0 "register_operand" "r,r") (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] "" - " -{ - v850_compare_op0 = operands[0]; - v850_compare_op1 = operands[1]; - DONE; -}") + { + v850_compare_op0 = operands[0]; + v850_compare_op1 = operands[1]; + DONE; + }) (define_insn "cmpsi_insn" [(set (cc0) @@ -398,29 +443,135 @@ [(set_attr "length" "2,2") (set_attr "cc" "compare")]) +(define_expand "cbranchsf4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SF 1 "register_operand") + (match_operand:SF 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc))) + (clobber (cc0))] + "TARGET_USE_FPU" +{ + enum rtx_code cond = GET_CODE (operands[0]); + machine_mode mode; + rtx fcc_reg; + rtx cc_reg; + rtx tmp; + + v850_compare_op0 = operands[1]; + v850_compare_op1 = operands[2]; + + if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT) + FAIL; + + mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1); + fcc_reg = gen_rtx_REG (mode, FCC_REGNUM); + cc_reg = gen_rtx_REG (mode, CC_REGNUM); + emit_insn (gen_rtx_SET (cc_reg, fcc_reg)); + tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx); + tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, + gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx); + emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)); + DONE; +}) + +(define_insn "cstoresf4" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:SF 2 "register_operand" "r") + (match_operand:SF 3 "register_operand" "r")]))] + "TARGET_USE_FPU" +{ + if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE) + return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf nz, %0"; + if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE) + return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf z, %0"; + if (GET_CODE (operands[1]) == EQ) + return "cmpf.s eq, %z2, %z3 ; trfsr ; setf z, %0"; + if (GET_CODE (operands[1]) == NE) + return "cmpf.s neq, %z2, %z3 ; trfsr ; setf nz, %0"; + gcc_unreachable (); +} + [(set_attr "length" "12") + (set_attr "type" "fpu")] +) + +(define_expand "cbranchdf4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:DF 1 "even_reg_operand") + (match_operand:DF 2 "even_reg_operand")]) + (label_ref (match_operand 3 "")) + (pc))) + (clobber (cc0))] + "TARGET_USE_FPU" +{ + enum rtx_code cond = GET_CODE (operands[0]); + machine_mode mode; + rtx fcc_reg; + rtx cc_reg; + rtx tmp; + + v850_compare_op0 = operands[1]; + v850_compare_op1 = operands[2]; + + if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT) + FAIL; + + mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1); + fcc_reg = gen_rtx_REG (mode, FCC_REGNUM); + cc_reg = gen_rtx_REG (mode, CC_REGNUM); + emit_insn (gen_rtx_SET (cc_reg, fcc_reg)); + tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx); + tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, + gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx); + emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)); + DONE; +}) + +(define_insn "cstoredf4" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:DF 2 "even_reg_operand" "r") + (match_operand:DF 3 "even_reg_operand" "r")]))] + "TARGET_USE_FPU" +{ + if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE) + return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf nz, %0"; + if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE) + return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf z, %0"; + if (GET_CODE (operands[1]) == EQ) + return "cmpf.d eq, %z2, %z3 ; trfsr ; setf z ,%0"; + if (GET_CODE (operands[1]) == NE) + return "cmpf.d neq, %z2, %z3 ; trfsr ; setf nz, %0"; + gcc_unreachable (); +} + [(set_attr "length" "12") + (set_attr "type" "fpu")] +) + (define_expand "cmpsf" [(set (reg:CC CC_REGNUM) (compare (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - " -{ - v850_compare_op0 = operands[0]; - v850_compare_op1 = operands[1]; - DONE; -}") + "TARGET_USE_FPU" + { + v850_compare_op0 = operands[0]; + v850_compare_op1 = operands[1]; + DONE; + }) (define_expand "cmpdf" [(set (reg:CC CC_REGNUM) (compare (match_operand:DF 0 "even_reg_operand" "r") (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - " -{ - v850_compare_op0 = operands[0]; - v850_compare_op1 = operands[1]; - DONE; -}") + "TARGET_USE_FPU" + { + v850_compare_op0 = operands[0]; + v850_compare_op1 = operands[1]; + DONE; + }) ;; ---------------------------------------------------------------------- ;; ADD INSTRUCTIONS @@ -475,11 +626,13 @@ (sign_extend:SI (match_operand:HI 1 "register_operand" "")) (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))] "" - "if (GET_CODE (operands[2]) == CONST_INT) - { - emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2])); - DONE; - }") + { + if (GET_CODE (operands[2]) == CONST_INT) + { + emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2])); + DONE; + } + }) (define_insn "*mulhisi3_internal1" [(set (match_operand:SI 0 "register_operand" "=r") @@ -519,7 +672,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "reg_or_int9_operand" "rO")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "mul %2,%1,%." [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -543,8 +696,13 @@ (mod:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E" - "div %2,%0,%3" + "TARGET_V850E_UP" +{ + if (TARGET_V850E2_UP) + return "divq %2,%0,%3"; + else + return "div %2,%0,%3"; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "div")]) @@ -557,8 +715,13 @@ (umod:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E" - "divu %2,%0,%3" + "TARGET_V850E_UP" +{ + if (TARGET_V850E2_UP) + return "divqu %2,%0,%3"; + else + return "divu %2,%0,%3"; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "div")]) @@ -574,7 +737,7 @@ (mod:HI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E" + "TARGET_V850E_UP" "divh %2,%0,%3" [(set_attr "length" "4") (set_attr "cc" "clobber") @@ -591,7 +754,7 @@ (umod:HI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E" + "TARGET_V850E_UP" "zxh %0 ; divhu %2,%0,%3" [(set_attr "length" "4") (set_attr "cc" "clobber") @@ -608,14 +771,13 @@ (match_operand:QI 1 "not_power_of_two_operand" "")) 0)) (clobber (reg:CC CC_REGNUM))] "" - "* { rtx xoperands[2]; xoperands[0] = operands[0]; xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff); - output_asm_insn (\"clr1 %M1,%0\", xoperands); - return \"\"; -}" + output_asm_insn ("clr1 %M1,%0", xoperands); + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -627,17 +789,17 @@ (match_operand:HI 1 "not_power_of_two_operand" "")) 0)) (clobber (reg:CC CC_REGNUM))] "" - "* { int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff); rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), log2 / 8)); + plus_constant (Pmode, XEXP (operands[0], 0), + log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"clr1 %1,%0\", xoperands); - return \"\"; -}" + output_asm_insn ("clr1 %1,%0", xoperands); + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -648,17 +810,17 @@ (match_operand:SI 1 "not_power_of_two_operand" ""))) (clobber (reg:CC CC_REGNUM))] "" - "* { int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff); rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), log2 / 8)); + plus_constant (Pmode, XEXP (operands[0], 0), + log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"clr1 %1,%0\", xoperands); - return \"\"; -}" + output_asm_insn ("clr1 %1,%0", xoperands); + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -696,23 +858,22 @@ (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0) (match_operand 1 "power_of_two_operand" "")) 0))] "" - "* { int log2 = exact_log2 (INTVAL (operands[1])); if (log2 < 8) - return \"set1 %M1,%0\"; + return "set1 %M1,%0"; else { rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), + plus_constant (Pmode, XEXP (operands[0], 0), log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"set1 %1,%0\", xoperands); + output_asm_insn ("set1 %1,%0", xoperands); } - return \"\"; -}" + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -723,23 +884,22 @@ (match_operand 1 "power_of_two_operand" ""))) (clobber (reg:CC CC_REGNUM))] "" - "* { int log2 = exact_log2 (INTVAL (operands[1])); if (log2 < 8) - return \"set1 %M1,%0\"; + return "set1 %M1,%0"; else { rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), + plus_constant (Pmode, XEXP (operands[0], 0), log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"set1 %1,%0\", xoperands); + output_asm_insn ("set1 %1,%0", xoperands); } - return \"\"; -}" + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -777,23 +937,22 @@ (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0) (match_operand 1 "power_of_two_operand" "")) 0))] "" - "* { int log2 = exact_log2 (INTVAL (operands[1])); if (log2 < 8) - return \"not1 %M1,%0\"; + return "not1 %M1,%0"; else { rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), + plus_constant (Pmode, XEXP (operands[0], 0), log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"not1 %1,%0\", xoperands); + output_asm_insn ("not1 %1,%0", xoperands); } - return \"\"; -}" + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -804,23 +963,22 @@ (match_operand 1 "power_of_two_operand" ""))) (clobber (reg:CC CC_REGNUM))] "" - "* { int log2 = exact_log2 (INTVAL (operands[1])); if (log2 < 8) - return \"not1 %M1,%0\"; + return "not1 %M1,%0"; else { rtx xoperands[2]; xoperands[0] = gen_rtx_MEM (QImode, - plus_constant (XEXP (operands[0], 0), + plus_constant (Pmode, XEXP (operands[0], 0), log2 / 8)); xoperands[1] = GEN_INT (log2 % 8); - output_asm_insn (\"not1 %1,%0\", xoperands); + output_asm_insn ("not1 %1,%0", xoperands); } - return \"\"; -}" + return ""; +} [(set_attr "length" "4") (set_attr "cc" "clobber") (set_attr "type" "bit1")]) @@ -865,6 +1023,17 @@ ;; optimize_bitfield_compare in fold-const usually converts single ;; bit extracts into an AND with a mask. +(define_insn "insv" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") + (match_operand:SI 1 "immediate_operand" "n") + (match_operand:SI 2 "immediate_operand" "n")) + (match_operand:SI 3 "register_operand" "r"))] + "TARGET_V850E3V5_UP" + "bins %3, %2, %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "set_zn")] +) + ;; ----------------------------------------------------------------- ;; Scc INSTRUCTIONS ;; ----------------------------------------------------------------- @@ -874,7 +1043,6 @@ (match_operator:SI 1 "comparison_operator" [(cc0) (const_int 0)]))] "" - "* { if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 && (GET_CODE (operands[1]) == GT @@ -883,8 +1051,8 @@ || GET_CODE (operands[1]) == LT)) return 0; - return \"setf %c1,%0\"; -}" + return "setf %c1,%0"; +} [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -900,7 +1068,7 @@ (define_insn "set_z_insn" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand 1 "v850_float_z_comparison_operator" ""))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "setf z,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -908,7 +1076,7 @@ (define_insn "set_nz_insn" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand 1 "v850_float_nz_comparison_operator" ""))] - "TARGET_V850E2V3" + "TARGET_V850E2V3_UP" "setf nz,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit")]) @@ -927,36 +1095,40 @@ (match_operand 1 "comparison_operator") (match_operand:SI 2 "reg_or_const_operand" "rJ") (match_operand:SI 3 "reg_or_const_operand" "rI")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" - " -{ - if ( (GET_CODE (operands[2]) == CONST_INT - && GET_CODE (operands[3]) == CONST_INT)) - { - int o2 = INTVAL (operands[2]); - int o3 = INTVAL (operands[3]); + "(TARGET_V850E_UP)" + { + /* Make sure that we have an integer comparison... */ + if (GET_MODE (XEXP (operands[1], 0)) != CCmode + && GET_MODE (XEXP (operands[1], 0)) != SImode) + FAIL; + + if ((GET_CODE (operands[2]) == CONST_INT + && GET_CODE (operands[3]) == CONST_INT)) + { + int o2 = INTVAL (operands[2]); + int o3 = INTVAL (operands[3]); - if (o2 == 1 && o3 == 0) - FAIL; /* setf */ - if (o3 == 1 && o2 == 0) - FAIL; /* setf */ - if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0) - FAIL; /* setf + shift */ - if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0) - FAIL; /* setf + shift */ - if (o2 != 0) - operands[2] = copy_to_mode_reg (SImode, operands[2]); - if (o3 !=0 ) - operands[3] = copy_to_mode_reg (SImode, operands[3]); - } - else - { - if (GET_CODE (operands[2]) != REG) - operands[2] = copy_to_mode_reg (SImode,operands[2]); - if (GET_CODE (operands[3]) != REG) - operands[3] = copy_to_mode_reg (SImode, operands[3]); - } -}") + if (o2 == 1 && o3 == 0) + FAIL; /* setf */ + if (o3 == 1 && o2 == 0) + FAIL; /* setf */ + if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0) + FAIL; /* setf + shift */ + if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0) + FAIL; /* setf + shift */ + if (o2 != 0) + operands[2] = copy_to_mode_reg (SImode, operands[2]); + if (o3 !=0 ) + operands[3] = copy_to_mode_reg (SImode, operands[3]); + } + else + { + if (GET_CODE (operands[2]) != REG) + operands[2] = copy_to_mode_reg (SImode,operands[2]); + if (GET_CODE (operands[3]) != REG) + operands[3] = copy_to_mode_reg (SImode, operands[3]); + } + }) ;; ??? Clobbering the condition codes is overkill. @@ -971,7 +1143,7 @@ [(reg:CC CC_REGNUM) (const_int 0)]) (match_operand:SI 2 "reg_or_int5_operand" "rJ") (match_operand:SI 3 "reg_or_0_operand" "rI")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "cmov %c1,%2,%z3,%0"; [(set_attr "length" "6") (set_attr "cc" "compare")]) @@ -983,7 +1155,7 @@ [(reg:CC CC_REGNUM) (const_int 0)]) (match_operand:SI 2 "reg_or_0_operand" "rI") (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "cmov %C1,%3,%z2,%0" [(set_attr "length" "6") (set_attr "cc" "compare")]) @@ -996,7 +1168,7 @@ (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) (match_operand:SI 2 "reg_or_int5_operand" "rJ") (match_operand:SI 3 "reg_or_0_operand" "rI")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "cmp %5,%4 ; cmov %c1,%2,%z3,%0" [(set_attr "length" "6") (set_attr "cc" "clobber")]) @@ -1009,7 +1181,7 @@ (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) (match_operand:SI 2 "reg_or_0_operand" "rI") (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "cmp %5,%4 ; cmov %C1,%3,%z2,%0" [(set_attr "length" "6") (set_attr "cc" "clobber")]) @@ -1025,7 +1197,7 @@ (const_int 0)]) (match_operand:SI 4 "reg_or_int5_operand" "rJ") (match_operand:SI 5 "reg_or_0_operand" "rI")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "tst1 %3,%2 ; cmov %c1,%4,%z5,%0" [(set_attr "length" "8") (set_attr "cc" "clobber")]) @@ -1041,7 +1213,7 @@ (const_int 0)]) (match_operand:SI 4 "reg_or_0_operand" "rI") (match_operand:SI 5 "reg_or_int5_operand" "rJ")))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "tst1 %3,%2 ; cmov %C1,%5,%z4,%0" [(set_attr "length" "8") (set_attr "cc" "clobber")]) @@ -1060,7 +1232,7 @@ (ashift:SI (match_operand:SI 2 "register_operand" "0") (const_int 1)))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "cmp %4,%3 ; sasf %c1,%0" [(set_attr "length" "6") (set_attr "cc" "clobber")]) @@ -1074,7 +1246,7 @@ (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" ""))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL) + "(TARGET_V850E_UP) && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1) && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1) && (GET_CODE (operands[5]) == CONST_INT @@ -1085,16 +1257,15 @@ (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)]) (ashift:SI (match_dup 0) (const_int 1)))) (clobber (reg:CC CC_REGNUM))])] - " -{ - operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); - if (INTVAL (operands[2]) & 0x1) - operands[7] = operands[1]; - else - operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), - GET_MODE (operands[1]), - XEXP (operands[1], 0), XEXP (operands[1], 1)); -}") + { + operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); + if (INTVAL (operands[2]) & 0x1) + operands[7] = operands[1]; + else + operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), + GET_MODE (operands[1]), + XEXP (operands[1], 0), XEXP (operands[1], 1)); + }) ;; --------------------------------------------------------------------- ;; BYTE SWAP INSTRUCTIONS @@ -1104,19 +1275,18 @@ (rotate:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "const_int_operand" ""))) (clobber (reg:CC CC_REGNUM))])] - "(TARGET_V850E || TARGET_V850E2_ALL)" - " -{ - if (INTVAL (operands[2]) != 8) - FAIL; -}") + "(TARGET_V850E_UP)" + { + if (INTVAL (operands[2]) != 8) + FAIL; + }) (define_insn "*rotlhi3_8" [(set (match_operand:HI 0 "register_operand" "=r") (rotate:HI (match_operand:HI 1 "register_operand" "r") (const_int 8))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "bsh %1,%0" [(set_attr "length" "4") (set_attr "cc" "clobber")]) @@ -1126,19 +1296,55 @@ (rotate:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" ""))) (clobber (reg:CC CC_REGNUM))])] - "(TARGET_V850E || TARGET_V850E2_ALL)" - " -{ - if (INTVAL (operands[2]) != 16) - FAIL; -}") + "(TARGET_V850E_UP)" + { + if (INTVAL (operands[2]) != 16) + FAIL; + }) + +(define_insn "rotlsi3_a" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 4 "ior_operator" + [(ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "n")) + (lshiftrt:SI (match_dup 1) + (match_operand:SI 3 "const_int_operand" "n"))]))] + "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)" + "rotl %2, %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "set_zn")] +) + +(define_insn "rotlsi3_b" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 4 "ior_operator" + [(lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "const_int_operand" "n")) + (ashift:SI (match_dup 1) + (match_operand:SI 2 "const_int_operand" "n"))]))] + "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)" + "rotl %2, %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "set_zn")] +) + +(define_insn "rotlsi3_v850e3v5" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotate:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "e3v5_shift_operand" "rn"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_V850E3V5_UP" + "rotl %2, %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "set_zn")] +) (define_insn "*rotlsi3_16" [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "hsw %1,%0" [(set_attr "length" "4") (set_attr "cc" "clobber")]) @@ -1147,6 +1353,83 @@ ;; JUMP INSTRUCTIONS ;; ---------------------------------------------------------------------- +;; Doloop + +(define_expand "doloop_begin" + [(use (match_operand 0 "" "")) ; loop pseudo + (use (match_operand 1 "" ""))] ; doloop_end pattern + "TARGET_V850E3V5_UP && TARGET_LOOP" + { + rtx loop_cnt = operands[0]; + gcc_assert (GET_MODE (loop_cnt) == SImode); + emit_insn (gen_fix_loop_counter (loop_cnt)); + DONE; + } +) + +(define_insn "fix_loop_counter" + [(unspec:SI [(match_operand:SI 0 "register_operand" "+r,!m") + (clobber (match_scratch:SI 1 "=X,r"))] UNSPEC_LOOP)] + "TARGET_V850E3V5_UP && TARGET_LOOP" + { + switch (which_alternative) + { + case 0: return "add 1, %0 # LOOP_BEGIN"; + case 1: return "ld.w %0, %1; add 1, %1; st.w %1, %0 # LOOP_BEGIN"; + default: gcc_unreachable (); + } + } + [(set_attr "length" "2,6") + (set_attr "cc" "none")] +) + +(define_expand "doloop_end" + [(use (match_operand 0 "" "")) ; loop pseudo + (use (match_operand 1 "" ""))] ; label + "TARGET_V850E3V5_UP && TARGET_LOOP" + { + rtx loop_cnt = operands[0]; + rtx label = operands[1]; + + if (GET_MODE (loop_cnt) != SImode) + FAIL; + + emit_jump_insn (gen_doloop_end_internal_loop (label, loop_cnt)); + DONE; + } +) + +(define_insn "doloop_end_internal_loop" + [(set (pc) + (if_then_else (ne (match_operand:SI 1 "register_operand" "+r,!m") + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1))) + (clobber (match_scratch:SI 2 "=X,r")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_V850E3V5_UP && TARGET_LOOP" + { + switch (which_alternative) + { + case 0: + if (get_attr_length (insn) == 4) + return "loop %1, %0 # LOOP.1.0"; + + return "add -1, %1; bne %l0 # LOOP.1.1"; + case 1: + return "ld.w %1, %2; add -1, %2; st.w %2, %1; bne %l0 # LOOP.2.1"; + default: + gcc_unreachable (); + } + } + [(set (attr "length") + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65534)) + (const_int 4) + (const_int 14))) + (set_attr "cc" "none")]) + ;; Conditional jump instructions (define_insn "*branch_normal" @@ -1156,7 +1439,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "* { if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 && (GET_CODE (operands[1]) == GT @@ -1166,15 +1448,19 @@ return 0; if (get_attr_length (insn) == 2) - return \"b%b1 %l0\"; - else - return \"b%B1 .+6 ; jr %l0\"; -}" + return "b%b1 %l0"; + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "b%b1 %l0"; + return "b%B1 .+6 ; jr %l0"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) (define_insn "*branch_invert" @@ -1184,24 +1470,30 @@ (pc) (label_ref (match_operand 0 "" ""))))] "" - "* { if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 && (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LT)) - return 0; + return NULL; + if (get_attr_length (insn) == 2) - return \"b%B1 %l0\"; - else - return \"b%b1 .+6 ; jr %l0\"; -}" + return "b%B1 %l0"; + + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "b%B1 %l0"; + + return "b%b1 .+6 ; jr %l0"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) (define_insn "branch_z_normal" @@ -1209,19 +1501,24 @@ (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_V850E2V3" - "* + "TARGET_V850E2V3_UP" { if (get_attr_length (insn) == 2) - return \"bz %l0\"; - else - return \"bnz 1f ; jr %l0 ; 1:\"; -}" + return "bz %l0"; + + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "bz %l0"; + + return "bnz 1f ; jr %l0 ; 1:"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) (define_insn "*branch_z_invert" @@ -1229,19 +1526,24 @@ (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") (pc) (label_ref (match_operand 0 "" ""))))] - "TARGET_V850E2V3" - "* + "TARGET_V850E2V3_UP" { if (get_attr_length (insn) == 2) - return \"bnz %l0\"; - else - return \"bz 1f ; jr %l0 ; 1:\"; -}" + return "bnz %l0"; + + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "bnz %l0"; + + return "bz 1f ; jr %l0 ; 1:"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) (define_insn "branch_nz_normal" @@ -1249,19 +1551,24 @@ (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_V850E2V3" - "* + "TARGET_V850E2V3_UP" { if (get_attr_length (insn) == 2) - return \"bnz %l0\"; - else - return \"bz 1f ; jr %l0 ; 1:\"; -}" + return "bnz %l0"; + + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "bnz %l0"; + + return "bz 1f ; jr %l0 ; 1:"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) (define_insn "*branch_nz_invert" @@ -1269,19 +1576,24 @@ (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") (pc) (label_ref (match_operand 0 "" ""))))] - "TARGET_V850E2V3" - "* + "TARGET_V850E2V3_UP" { if (get_attr_length (insn) == 2) - return \"bz %l0\"; - else - return \"bnz 1f ; jr %l0 ; 1:\"; -}" + return "bz %l0"; + + if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) + return "bz %l0"; + + return "bnz 1f ; jr %l0 ; 1:"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 6))) + (if_then_else (lt (abs (minus (match_dup 0) (pc))) + (const_int 65536)) + (const_int 4) + (const_int 6)))) (set_attr "cc" "none")]) ;; Unconditional and other jump instructions. @@ -1290,13 +1602,12 @@ [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "* { if (get_attr_length (insn) == 2) - return \"br %0\"; + return "br %0"; else - return \"jr %0\"; -}" + return "jr %0"; +} [(set (attr "length") (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) @@ -1328,7 +1639,7 @@ (const_int 1)) (label_ref (match_operand 1 "" ""))))) (label_ref (match_dup 1))))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "switch %0" [(set_attr "length" "2") (set_attr "cc" "none")]) @@ -1339,44 +1650,43 @@ (match_operand:SI 2 "register_operand" "") (match_operand 3 "" "") (match_operand 4 "" "")] "" - " -{ - rtx reg = gen_reg_rtx (SImode); - rtx tableaddress = gen_reg_rtx (SImode); - rtx test; - rtx mem; + { + rtx reg = gen_reg_rtx (SImode); + rtx tableaddress = gen_reg_rtx (SImode); + rtx test; + rtx mem; - /* Subtract the lower bound from the index. */ - emit_insn (gen_subsi3 (reg, operands[0], operands[1])); + /* Subtract the lower bound from the index. */ + emit_insn (gen_subsi3 (reg, operands[0], operands[1])); - /* Compare the result against the number of table entries; - branch to the default label if out of range of the table. */ - test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]); - emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4])); + /* Compare the result against the number of table entries; + branch to the default label if out of range of the table. */ + test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]); + emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4])); - /* Shift index for the table array access. */ - emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1))); - /* Load the table address into a pseudo. */ - emit_insn (gen_movsi (tableaddress, - gen_rtx_LABEL_REF (Pmode, operands[3]))); - /* Add the table address to the index. */ - emit_insn (gen_addsi3 (reg, reg, tableaddress)); - /* Load the table entry. */ - mem = gen_const_mem (CASE_VECTOR_MODE, reg); - if (! TARGET_BIG_SWITCH) - { - rtx reg2 = gen_reg_rtx (HImode); - emit_insn (gen_movhi (reg2, mem)); - emit_insn (gen_extendhisi2 (reg, reg2)); - } - else - emit_insn (gen_movsi (reg, mem)); - /* Add the table address. */ - emit_insn (gen_addsi3 (reg, reg, tableaddress)); - /* Branch to the switch label. */ - emit_jump_insn (gen_tablejump (reg, operands[3])); - DONE; -}") + /* Shift index for the table array access. */ + emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1))); + /* Load the table address into a pseudo. */ + emit_insn (gen_movsi (tableaddress, + gen_rtx_LABEL_REF (Pmode, operands[3]))); + /* Add the table address to the index. */ + emit_insn (gen_addsi3 (reg, reg, tableaddress)); + /* Load the table entry. */ + mem = gen_const_mem (CASE_VECTOR_MODE, reg); + if (! TARGET_BIG_SWITCH) + { + rtx reg2 = gen_reg_rtx (HImode); + emit_insn (gen_movhi (reg2, mem)); + emit_insn (gen_extendhisi2 (reg, reg2)); + } + else + emit_insn (gen_movsi (reg, mem)); + /* Add the table address. */ + emit_insn (gen_addsi3 (reg, reg, tableaddress)); + /* Branch to the switch label. */ + emit_jump_insn (gen_tablejump (reg, operands[3])); + DONE; + }) ;; Call subroutine with no return value. @@ -1384,27 +1694,34 @@ [(call (match_operand:QI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" - " -{ - if (! call_address_operand (XEXP (operands[0], 0), QImode) - || TARGET_LONG_CALLS) - XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); - if (TARGET_LONG_CALLS) - emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1])); - else - emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1])); + { + if (! call_address_operand (XEXP (operands[0], 0), QImode) + || TARGET_LONG_CALLS) + XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); + if (TARGET_LONG_CALLS) + emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1])); + else + emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1])); - DONE; -}") + DONE; + }) (define_insn "call_internal_short" [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) (match_operand:SI 1 "general_operand" "g,g")) (clobber (reg:SI 31))] "! TARGET_LONG_CALLS" - "@ - jarl %0,r31 - jarl .+4,r31 ; add 4,r31 ; jmp %0" + { + if (which_alternative == 1) + { + if (TARGET_V850E3V5_UP) + return "jarl [%0], r31"; + + return "jarl .+4, r31 ; add 4, r31 ; jmp %0"; + } + + return "jarl %0, r31"; + } [(set_attr "length" "4,8") (set_attr "cc" "clobber,clobber")] ) @@ -1414,18 +1731,23 @@ (match_operand:SI 1 "general_operand" "g,g")) (clobber (reg:SI 31))] "TARGET_LONG_CALLS" - "* - { +{ if (which_alternative == 0) { if (GET_CODE (operands[0]) == REG) - return \"jarl %0,r31\"; - else - return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\"; + return "jarl %0,r31"; + + if (TARGET_V850E3V5_UP) + return "mov hilo(%0), r11 ; jarl [r11], r31"; + + return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11"; } - else - return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\"; - }" + + if (TARGET_V850E3V5_UP) + return "jarl [%0], r31"; + + return "jarl .+4,r31 ; add 4,r31 ; jmp %0"; +} [(set_attr "length" "16,8") (set_attr "cc" "clobber,clobber")] ) @@ -1438,21 +1760,20 @@ (call (match_operand:QI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" - " -{ - if (! call_address_operand (XEXP (operands[1], 0), QImode) - || TARGET_LONG_CALLS) - XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); - if (TARGET_LONG_CALLS) - emit_call_insn (gen_call_value_internal_long (operands[0], - XEXP (operands[1], 0), - operands[2])); - else - emit_call_insn (gen_call_value_internal_short (operands[0], - XEXP (operands[1], 0), - operands[2])); - DONE; -}") + { + if (! call_address_operand (XEXP (operands[1], 0), QImode) + || TARGET_LONG_CALLS) + XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); + if (TARGET_LONG_CALLS) + emit_call_insn (gen_call_value_internal_long (operands[0], + XEXP (operands[1], 0), + operands[2])); + else + emit_call_insn (gen_call_value_internal_short (operands[0], + XEXP (operands[1], 0), + operands[2])); + DONE; + }) (define_insn "call_value_internal_short" [(set (match_operand 0 "" "=r,r") @@ -1460,9 +1781,17 @@ (match_operand:SI 2 "general_operand" "g,g"))) (clobber (reg:SI 31))] "! TARGET_LONG_CALLS" - "@ - jarl %1,r31 - jarl .+4,r31 ; add 4,r31 ; jmp %1" + { + if (which_alternative == 1) + { + if (TARGET_V850E3V5_UP) + return "jarl [%1], r31"; + + return "jarl .+4, r31 ; add 4, r31 ; jmp %1"; + } + + return "jarl %1, r31"; + } [(set_attr "length" "4,8") (set_attr "cc" "clobber,clobber")] ) @@ -1473,19 +1802,24 @@ (match_operand:SI 2 "general_operand" "g,g"))) (clobber (reg:SI 31))] "TARGET_LONG_CALLS" - "* - { +{ if (which_alternative == 0) { if (GET_CODE (operands[1]) == REG) - return \"jarl %1, r31\"; - else + return "jarl %1, r31"; + /* Reload can generate this pattern.... */ - return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\"; + if (TARGET_V850E3V5_UP) + return "mov hilo(%1), r11 ; jarl [r11], r31"; + + return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11"; } - else - return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\"; - }" + + if (TARGET_V850E3V5_UP) + return "jarl [%1], r31"; + + return "jarl .+4, r31 ; add 4, r31 ; jmp %1"; +} [(set_attr "length" "16,8") (set_attr "cc" "clobber,clobber")] ) @@ -1501,12 +1835,12 @@ ;; EXTEND INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "" +(define_insn "*zero_extendhisi2_v850e" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m"))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "@ zxh %0 andi 65535,%1,%0 @@ -1515,22 +1849,33 @@ [(set_attr "length" "2,4,2,4") (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) -(define_insn "zero_extendhisi2" +(define_insn "*zero_extendhisi2_v850" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))) - (clobber (reg:CC CC_REGNUM))] + (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander "" "andi 65535,%1,%0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) -(define_insn "" +(define_expand "zero_extendhisi2" + [(parallel [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand"))) + (clobber (reg:CC CC_REGNUM))])] + "" + { + if (! (TARGET_V850E_UP)) + operands[1] = force_reg (HImode, operands[1]); + }) + +(define_insn "*zero_extendqisi2_v850e" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m"))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "@ zxb %0 andi 255,%1,%0 @@ -1539,16 +1884,27 @@ [(set_attr "length" "2,4,2,4") (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) -(define_insn "zero_extendqisi2" +(define_insn "*zero_extendqisi2_v850" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI - (match_operand:QI 1 "register_operand" "r"))) - (clobber (reg:CC CC_REGNUM))] + (match_operand:QI 1 "register_operand" "r"))) + (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander "" "andi 255,%1,%0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) +(define_expand "zero_extendqisi2" + [(parallel [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI + (match_operand:QI 1 "nonimmediate_operand"))) + (clobber (reg:CC CC_REGNUM))])] + "" + { + if (! (TARGET_V850E_UP)) + operands[1] = force_reg (QImode, operands[1]); + }) + ;;- sign extension instructions ;; ??? The extendhisi2 pattern should not emit shifts for v850e? @@ -1557,7 +1913,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r,r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m"))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "@ sxh %0 sld.h %1,%0 @@ -1578,11 +1934,10 @@ (const_int 16))) (clobber (reg:CC CC_REGNUM))])] "" - " -{ - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); -}") + { + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_reg_rtx (SImode); + }) ;; ??? The extendqisi2 pattern should not emit shifts for v850e? @@ -1590,7 +1945,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r,r") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m"))) (clobber (reg:CC CC_REGNUM))] - "(TARGET_V850E || TARGET_V850E2_ALL)" + "(TARGET_V850E_UP)" "@ sxb %0 sld.b %1,%0 @@ -1611,11 +1966,10 @@ (const_int 24))) (clobber (reg:CC CC_REGNUM))])] "" - " -{ - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_reg_rtx (SImode); -}") + { + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_reg_rtx (SImode); + }) ;; ---------------------------------------------------------------------- ;; SHIFTS @@ -1640,7 +1994,7 @@ (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "nonmemory_operand" "r"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E2_ALL" + "TARGET_V850E2_UP" "shl %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "set_znv")]) @@ -1664,7 +2018,7 @@ (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "nonmemory_operand" "r"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E2_ALL" + "TARGET_V850E2_UP" "shr %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) @@ -1688,7 +2042,7 @@ (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "nonmemory_operand" "r"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E2_ALL" + "TARGET_V850E2_UP" "sar %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) @@ -1701,7 +2055,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ffs:SI (match_operand:SI 1 "register_operand" "r"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_V850E2_ALL" + "TARGET_V850E2_UP" "sch1r %1,%0" [(set_attr "length" "4") (set_attr "cc" "clobber")]) @@ -1712,16 +2066,18 @@ (define_expand "prologue" [(const_int 0)] "" - "expand_prologue (); DONE;") + { + expand_prologue (); + DONE; + }) (define_expand "epilogue" [(return)] "" - " -{ - expand_epilogue (); - DONE; -}") + { + expand_epilogue (); + DONE; + }) (define_insn "return_simple" [(return)] @@ -1747,7 +2103,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (plus:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "addf.s %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1757,7 +2113,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (plus:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "addf.d %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1767,7 +2123,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (minus:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "subf.s %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1777,7 +2133,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (minus:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "subf.d %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1787,7 +2143,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (mult:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "mulf.s %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1797,7 +2153,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (mult:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "mulf.d %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1807,7 +2163,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "divf.s %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1817,7 +2173,7 @@ [(set (match_operand:DF 0 "register_operand" "=r") (div:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "divf.d %2,%1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1827,7 +2183,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r") (match_operand:SF 2 "reg_or_0_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "minf.s %z1,%z2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1837,7 +2193,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (smin:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "minf.d %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1847,7 +2203,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r") (match_operand:SF 2 "reg_or_0_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "maxf.s %z1,%z2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1857,7 +2213,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (smax:DF (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "maxf.d %1,%2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1866,7 +2222,7 @@ (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=r") (abs:SF (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "absf.s %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1875,7 +2231,7 @@ (define_insn "absdf2" [(set (match_operand:DF 0 "even_reg_operand" "=r") (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "absf.d %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1884,7 +2240,7 @@ (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "negf.s %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1893,7 +2249,7 @@ (define_insn "negdf2" [(set (match_operand:DF 0 "even_reg_operand" "=r") (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "negf.d %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1903,7 +2259,7 @@ (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=r") (sqrt:SF (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "sqrtf.s %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1912,7 +2268,7 @@ (define_insn "sqrtdf2" [(set (match_operand:DF 0 "even_reg_operand" "=r") (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "sqrtf.d %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1921,47 +2277,159 @@ ;; float -> int (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "r"))))] - "TARGET_V850E2V3" + (fix:SI (match_operand:SF 1 "register_operand" "r")))] + "TARGET_USE_FPU" "trncf.sw %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +(define_insn "fixuns_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] + "TARGET_USE_FPU" + "trncf.suw %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")] +) + (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (fix:SI (fix:DF (match_operand:DF 1 "even_reg_operand" "r"))))] - "TARGET_V850E2V3" + (fix:SI (match_operand:DF 1 "even_reg_operand" "r")))] + "TARGET_USE_FPU" "trncf.dw %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +(define_insn "fixuns_truncdfsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (unsigned_fix:SI (match_operand:DF 1 "even_reg_operand" "r")))] + "TARGET_USE_FPU" + "trncf.duw %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")] +) + +(define_insn "fix_truncsfdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (fix:DI (match_operand:SF 1 "register_operand" "r")))] + "TARGET_USE_FPU" + "trncf.sl %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "fixuns_truncsfdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))] + "TARGET_USE_FPU" + "trncf.sul %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")] +) + +(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (fix:DI (match_operand:DF 1 "even_reg_operand" "r")))] + "TARGET_USE_FPU" + "trncf.dl %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "fixuns_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unsigned_fix:DI (match_operand:DF 1 "even_reg_operand" "r")))] + "TARGET_USE_FPU" + "trncf.dul %1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")] +) + ;; int -> float (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r") (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cvtf.ws %z1, %0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +(define_insn "unsfloatsisf2" + [(set (match_operand:SF 0 "register_operand" "=r") + (unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.uws %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + (define_insn "floatsidf2" [(set (match_operand:DF 0 "even_reg_operand" "=r") (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cvtf.wd %z1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +(define_insn "unsfloatsidf2" + [(set (match_operand:DF 0 "even_reg_operand" "=r") + (unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.uwd %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "floatdisf2" + [(set (match_operand:SF 0 "even_reg_operand" "=r") + (float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.ls %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "unsfloatdisf2" + [(set (match_operand:SF 0 "even_reg_operand" "=r") + (unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.uls %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "floatdidf2" + [(set (match_operand:DF 0 "even_reg_operand" "=r") + (float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.ld %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + +(define_insn "unsfloatdidf2" + [(set (match_operand:DF 0 "even_reg_operand" "=r") + (unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))] + "TARGET_USE_FPU" + "cvtf.uld %z1, %0" + [(set_attr "length" "4") + (set_attr "cc" "none_0hit") + (set_attr "type" "fpu")]) + ;; single-float -> double-float (define_insn "extendsfdf2" [(set (match_operand:DF 0 "even_reg_operand" "=r") (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "rI")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cvtf.sd %z1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1972,7 +2440,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cvtf.ds %1,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1987,7 +2455,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "const_float_1_operand" "") (match_operand:SF 2 "register_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "recipf.s %2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -1997,7 +2465,7 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (div:DF (match_operand:DF 1 "const_float_1_operand" "") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "recipf.d %2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -2008,7 +2476,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "const_float_1_operand" "") (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "rsqrtf.s %2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") @@ -2018,20 +2486,24 @@ [(set (match_operand:DF 0 "even_reg_operand" "=r") (div:DF (match_operand:DF 1 "const_float_1_operand" "") (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "rsqrtf.d %2,%0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually +;; need operand 4 to be the same as operand 0. But the FPU-2.0 versions are +;; also deprecated so the loss of flexibility is unimportant. + ;;; multiply-add (define_insn "fmasf4" [(set (match_operand:SF 0 "register_operand" "=r") (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (match_operand:SF 3 "register_operand" "r")))] - "TARGET_V850E2V3" - "maddf.s %2,%1,%3,%0" + (match_operand:SF 3 "register_operand" "0")))] + "TARGET_USE_FPU" + { return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2041,9 +2513,9 @@ [(set (match_operand:SF 0 "register_operand" "=r") (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (neg:SF (match_operand:SF 3 "register_operand" "r"))))] - "TARGET_V850E2V3" - "msubf.s %2,%1,%3,%0" + (neg:SF (match_operand:SF 3 "register_operand" "0"))))] + "TARGET_USE_FPU" + { return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2051,23 +2523,23 @@ ;;; negative-multiply-add (define_insn "fnmasf4" [(set (match_operand:SF 0 "register_operand" "=r") - (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) - (match_operand:SF 2 "register_operand" "r") - (match_operand:SF 3 "register_operand" "r")))] - "TARGET_V850E2V3" - "nmaddf.s %2,%1,%3,%0" + (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") + (match_operand:SF 2 "register_operand" "r") + (match_operand:SF 3 "register_operand" "0"))))] + "TARGET_USE_FPU" + { return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; negative-multiply-subtract (define_insn "fnmssf4" - [(set (match_operand:SF 0 "register_operand" "=r") - (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) - (match_operand:SF 2 "register_operand" "r") - (neg:SF (match_operand:SF 3 "register_operand" "r"))))] - "TARGET_V850E2V3" - "nmsubf.s %2,%1,%3,%0" + [(set (match_operand:SF 0 "register_operand" "=r") + (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") + (match_operand:SF 2 "register_operand" "r") + (neg:SF (match_operand:SF 3 "register_operand" "0")))))] + "TARGET_USE_FPU" + { return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2080,8 +2552,8 @@ [(set (reg:CC_FPU_LE FCC_REGNUM) (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s le,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.s le, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2090,8 +2562,8 @@ [(set (reg:CC_FPU_LT FCC_REGNUM) (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s lt,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.s lt, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2100,8 +2572,8 @@ [(set (reg:CC_FPU_GE FCC_REGNUM) (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s ge,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.s le, %z1, %z0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2110,8 +2582,8 @@ [(set (reg:CC_FPU_GT FCC_REGNUM) (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s gt,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.s lt, %z1, %z0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2120,18 +2592,8 @@ [(set (reg:CC_FPU_EQ FCC_REGNUM) (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s eq,%z0,%z1" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")]) - -(define_insn "cmpsf_ne_insn" - [(set (reg:CC_FPU_NE FCC_REGNUM) - (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r") - (match_operand:SF 1 "register_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.s neq,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.s eq, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2142,8 +2604,8 @@ [(set (reg:CC_FPU_LE FCC_REGNUM) (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r") (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d le,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.d le, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2152,8 +2614,8 @@ [(set (reg:CC_FPU_LT FCC_REGNUM) (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r") (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d lt,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.d lt, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2162,8 +2624,8 @@ [(set (reg:CC_FPU_GE FCC_REGNUM) (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r") (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d ge,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.d le, %z1, %z0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2171,9 +2633,9 @@ (define_insn "cmpdf_gt_insn" [(set (reg:CC_FPU_GT FCC_REGNUM) (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r") - (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d gt,%z0,%z1" + (match_operand:DF 1 "even_reg_operand" "r")))] + "TARGET_USE_FPU" + "cmpf.d lt, %z1, %z0" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2182,23 +2644,12 @@ [(set (reg:CC_FPU_EQ FCC_REGNUM) (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r") (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d eq,%z0,%z1" + "TARGET_USE_FPU" + "cmpf.d eq, %z0, %z1" [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) -(define_insn "cmpdf_ne_insn" - [(set (reg:CC_FPU_NE FCC_REGNUM) - (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r") - (match_operand:DF 1 "even_reg_operand" "r")))] - "TARGET_V850E2V3" - "cmpf.d neq,%z0,%z1" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")]) - - ;; ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a ;; conditional branch based on a floating-point compare) @@ -2206,7 +2657,7 @@ (define_insn "trfsr" [(set (match_operand 0 "" "") (match_operand 1 "" ""))] - "TARGET_V850E2V3 + "TARGET_USE_FPU && GET_MODE(operands[0]) == GET_MODE(operands[1]) && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM @@ -2233,7 +2684,7 @@ (match_operand 3 "v850_float_z_comparison_operator" "") (match_operand:SF 1 "reg_or_0_operand" "rIG") (match_operand:SF 2 "reg_or_0_operand" "rIG")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.s 0,%z1,%z2,%0" [(set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2243,7 +2694,7 @@ (match_operand 3 "v850_float_nz_comparison_operator" "") (match_operand:SF 1 "reg_or_0_operand" "rIG") (match_operand:SF 2 "reg_or_0_operand" "rIG")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.s 0,%z2,%z1,%0" [(set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2253,7 +2704,7 @@ (match_operand 3 "v850_float_z_comparison_operator" "") (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.d 0,%z1,%z2,%0" [(set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2263,7 +2714,7 @@ (match_operand 3 "v850_float_nz_comparison_operator" "") (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.d 0,%z2,%z1,%0" [(set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2273,7 +2724,7 @@ (match_operand 3 "v850_float_z_comparison_operator" "") (match_operand:DF 1 "reg_or_0_operand" "rIG") (match_operand:DF 2 "reg_or_0_operand" "rIG")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0" [(set_attr "length" "8") (set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2284,7 +2735,7 @@ (match_operand 3 "v850_float_nz_comparison_operator" "") (match_operand:DF 1 "reg_or_0_operand" "rIG") (match_operand:DF 2 "reg_or_0_operand" "rIG")))] - "TARGET_V850E2V3" + "TARGET_USE_FPU" "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0" [(set_attr "length" "8") (set_attr "cc" "clobber")]) ;; ??? or none_0hit @@ -2309,9 +2760,10 @@ (set (mem:SI (plus:SI (reg:SI 3) (match_operand:SI 2 "immediate_operand" "i"))) (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] - "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" - "* return construct_prepare_instruction (operands[0]); - " + "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)" +{ + return construct_prepare_instruction (operands[0]); +} [(set_attr "length" "4") (set_attr "cc" "clobber")]) @@ -2323,8 +2775,9 @@ (match_operand:SI 2 "immediate_operand" "i"))) (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] "TARGET_PROLOG_FUNCTION" - "* return construct_save_jarl (operands[0]); - " +{ + return construct_save_jarl (operands[0]); +} [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") (const_string "16") (const_string "4"))) @@ -2341,9 +2794,10 @@ (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") (mem:SI (plus:SI (reg:SI 3) (match_operand:SI 3 "immediate_operand" "i"))))])] - "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" - "* return construct_dispose_instruction (operands[0]); - " + "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)" +{ + return construct_dispose_instruction (operands[0]); +} [(set_attr "length" "4") (set_attr "cc" "clobber")]) @@ -2360,8 +2814,9 @@ (mem:SI (plus:SI (reg:SI 3) (match_operand:SI 3 "immediate_operand" "i"))))])] "TARGET_PROLOG_FUNCTION" - "* return construct_restore_jr (operands[0]); - " +{ + return construct_restore_jr (operands[0]); +} [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") (const_string "12") (const_string "4"))) @@ -2370,30 +2825,29 @@ ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION. (define_insn "callt_save_interrupt" [(unspec_volatile [(const_int 0)] 2)] - "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" + "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" ;; The CALLT instruction stores the next address of CALLT to CTPC register ;; without saving its previous value. So if the interrupt handler ;; or its caller could possibly execute the CALLT insn, save_interrupt ;; MUST NOT be called via CALLT. - "* { - output_asm_insn (\"addi -28, sp, sp\", operands); - output_asm_insn (\"st.w r1, 24[sp]\", operands); - output_asm_insn (\"st.w r10, 12[sp]\", operands); - output_asm_insn (\"st.w r11, 16[sp]\", operands); - output_asm_insn (\"stsr ctpc, r10\", operands); - output_asm_insn (\"st.w r10, 20[sp]\", operands); - output_asm_insn (\"stsr ctpsw, r10\", operands); - output_asm_insn (\"st.w r10, 24[sp]\", operands); - output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands); - return \"\"; -}" + output_asm_insn ("addi -28, sp, sp", operands); + output_asm_insn ("st.w r1, 24[sp]", operands); + output_asm_insn ("st.w r10, 12[sp]", operands); + output_asm_insn ("st.w r11, 16[sp]", operands); + output_asm_insn ("stsr ctpc, r10", operands); + output_asm_insn ("st.w r10, 20[sp]", operands); + output_asm_insn ("stsr ctpsw, r10", operands); + output_asm_insn ("st.w r10, 24[sp]", operands); + output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands); + return ""; +} [(set_attr "length" "26") (set_attr "cc" "clobber")]) (define_insn "callt_return_interrupt" [(unspec_volatile [(const_int 0)] 3)] - "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" + "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_return_interrupt)" [(set_attr "length" "2") (set_attr "cc" "clobber")]) @@ -2406,27 +2860,26 @@ (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10)) (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))] "" - "* { if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) - return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\"; + return "addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10"; else { - output_asm_insn (\"addi -20, sp, sp\", operands); - output_asm_insn (\"st.w r11, 16[sp]\", operands); - output_asm_insn (\"st.w r10, 12[sp]\", operands); - output_asm_insn (\"st.w ep, 0[sp]\", operands); - output_asm_insn (\"st.w gp, 4[sp]\", operands); - output_asm_insn (\"st.w r1, 8[sp]\", operands); - output_asm_insn (\"movhi hi(__ep), r0, ep\", operands); - output_asm_insn (\"movea lo(__ep), ep, ep\", operands); - output_asm_insn (\"movhi hi(__gp), r0, gp\", operands); - output_asm_insn (\"movea lo(__gp), gp, gp\", operands); - return \"\"; + output_asm_insn ("addi -20, sp, sp", operands); + output_asm_insn ("st.w r11, 16[sp]", operands); + output_asm_insn ("st.w r10, 12[sp]", operands); + output_asm_insn ("st.w ep, 0[sp]", operands); + output_asm_insn ("st.w gp, 4[sp]", operands); + output_asm_insn ("st.w r1, 8[sp]", operands); + output_asm_insn ("movhi hi(__ep), r0, ep", operands); + output_asm_insn ("movea lo(__ep), ep, ep", operands); + output_asm_insn ("movhi hi(__gp), r0, gp", operands); + output_asm_insn ("movea lo(__gp), gp, gp", operands); + return ""; } -}" +} [(set (attr "length") - (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) + (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 10) (const_int 34))) (set_attr "cc" "clobber")]) @@ -2441,24 +2894,23 @@ (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4)))) (set (reg:SI 30) (mem:SI (reg:SI 3)))] "" - "* { if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) - return \"jr __return_interrupt\"; + return "jr __return_interrupt"; else { - output_asm_insn (\"ld.w 0[sp], ep\", operands); - output_asm_insn (\"ld.w 4[sp], gp\", operands); - output_asm_insn (\"ld.w 8[sp], r1\", operands); - output_asm_insn (\"ld.w 12[sp], r10\", operands); - output_asm_insn (\"ld.w 16[sp], r11\", operands); - output_asm_insn (\"addi 20, sp, sp\", operands); - output_asm_insn (\"reti\", operands); - return \"\"; + output_asm_insn ("ld.w 0[sp], ep", operands); + output_asm_insn ("ld.w 4[sp], gp", operands); + output_asm_insn ("ld.w 8[sp], r1", operands); + output_asm_insn ("ld.w 12[sp], r10", operands); + output_asm_insn ("ld.w 16[sp], r11", operands); + output_asm_insn ("addi 20, sp, sp", operands); + output_asm_insn ("reti", operands); + return ""; } -}" +} [(set (attr "length") - (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) + (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) (const_int 24))) (set_attr "cc" "clobber")]) @@ -2472,7 +2924,7 @@ (define_insn "callt_save_all_interrupt" [(unspec_volatile [(const_int 0)] 0)] - "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" + "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_save_all_interrupt)" [(set_attr "length" "2") (set_attr "cc" "none")]) @@ -2480,79 +2932,78 @@ (define_insn "save_all_interrupt" [(unspec_volatile [(const_int 0)] 0)] "" - "* { if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) - return \"jarl __save_all_interrupt,r10\"; + return "jarl __save_all_interrupt,r10"; - output_asm_insn (\"addi -120, sp, sp\", operands); + output_asm_insn ("addi -120, sp, sp", operands); if (TARGET_EP) { - output_asm_insn (\"mov ep, r1\", operands); - output_asm_insn (\"mov sp, ep\", operands); - output_asm_insn (\"sst.w r31, 116[ep]\", operands); - output_asm_insn (\"sst.w r2, 112[ep]\", operands); - output_asm_insn (\"sst.w gp, 108[ep]\", operands); - output_asm_insn (\"sst.w r6, 104[ep]\", operands); - output_asm_insn (\"sst.w r7, 100[ep]\", operands); - output_asm_insn (\"sst.w r8, 96[ep]\", operands); - output_asm_insn (\"sst.w r9, 92[ep]\", operands); - output_asm_insn (\"sst.w r11, 88[ep]\", operands); - output_asm_insn (\"sst.w r12, 84[ep]\", operands); - output_asm_insn (\"sst.w r13, 80[ep]\", operands); - output_asm_insn (\"sst.w r14, 76[ep]\", operands); - output_asm_insn (\"sst.w r15, 72[ep]\", operands); - output_asm_insn (\"sst.w r16, 68[ep]\", operands); - output_asm_insn (\"sst.w r17, 64[ep]\", operands); - output_asm_insn (\"sst.w r18, 60[ep]\", operands); - output_asm_insn (\"sst.w r19, 56[ep]\", operands); - output_asm_insn (\"sst.w r20, 52[ep]\", operands); - output_asm_insn (\"sst.w r21, 48[ep]\", operands); - output_asm_insn (\"sst.w r22, 44[ep]\", operands); - output_asm_insn (\"sst.w r23, 40[ep]\", operands); - output_asm_insn (\"sst.w r24, 36[ep]\", operands); - output_asm_insn (\"sst.w r25, 32[ep]\", operands); - output_asm_insn (\"sst.w r26, 28[ep]\", operands); - output_asm_insn (\"sst.w r27, 24[ep]\", operands); - output_asm_insn (\"sst.w r28, 20[ep]\", operands); - output_asm_insn (\"sst.w r29, 16[ep]\", operands); - output_asm_insn (\"mov r1, ep\", operands); + output_asm_insn ("mov ep, r1", operands); + output_asm_insn ("mov sp, ep", operands); + output_asm_insn ("sst.w r31, 116[ep]", operands); + output_asm_insn ("sst.w r2, 112[ep]", operands); + output_asm_insn ("sst.w gp, 108[ep]", operands); + output_asm_insn ("sst.w r6, 104[ep]", operands); + output_asm_insn ("sst.w r7, 100[ep]", operands); + output_asm_insn ("sst.w r8, 96[ep]", operands); + output_asm_insn ("sst.w r9, 92[ep]", operands); + output_asm_insn ("sst.w r11, 88[ep]", operands); + output_asm_insn ("sst.w r12, 84[ep]", operands); + output_asm_insn ("sst.w r13, 80[ep]", operands); + output_asm_insn ("sst.w r14, 76[ep]", operands); + output_asm_insn ("sst.w r15, 72[ep]", operands); + output_asm_insn ("sst.w r16, 68[ep]", operands); + output_asm_insn ("sst.w r17, 64[ep]", operands); + output_asm_insn ("sst.w r18, 60[ep]", operands); + output_asm_insn ("sst.w r19, 56[ep]", operands); + output_asm_insn ("sst.w r20, 52[ep]", operands); + output_asm_insn ("sst.w r21, 48[ep]", operands); + output_asm_insn ("sst.w r22, 44[ep]", operands); + output_asm_insn ("sst.w r23, 40[ep]", operands); + output_asm_insn ("sst.w r24, 36[ep]", operands); + output_asm_insn ("sst.w r25, 32[ep]", operands); + output_asm_insn ("sst.w r26, 28[ep]", operands); + output_asm_insn ("sst.w r27, 24[ep]", operands); + output_asm_insn ("sst.w r28, 20[ep]", operands); + output_asm_insn ("sst.w r29, 16[ep]", operands); + output_asm_insn ("mov r1, ep", operands); } else { - output_asm_insn (\"st.w r31, 116[sp]\", operands); - output_asm_insn (\"st.w r2, 112[sp]\", operands); - output_asm_insn (\"st.w gp, 108[sp]\", operands); - output_asm_insn (\"st.w r6, 104[sp]\", operands); - output_asm_insn (\"st.w r7, 100[sp]\", operands); - output_asm_insn (\"st.w r8, 96[sp]\", operands); - output_asm_insn (\"st.w r9, 92[sp]\", operands); - output_asm_insn (\"st.w r11, 88[sp]\", operands); - output_asm_insn (\"st.w r12, 84[sp]\", operands); - output_asm_insn (\"st.w r13, 80[sp]\", operands); - output_asm_insn (\"st.w r14, 76[sp]\", operands); - output_asm_insn (\"st.w r15, 72[sp]\", operands); - output_asm_insn (\"st.w r16, 68[sp]\", operands); - output_asm_insn (\"st.w r17, 64[sp]\", operands); - output_asm_insn (\"st.w r18, 60[sp]\", operands); - output_asm_insn (\"st.w r19, 56[sp]\", operands); - output_asm_insn (\"st.w r20, 52[sp]\", operands); - output_asm_insn (\"st.w r21, 48[sp]\", operands); - output_asm_insn (\"st.w r22, 44[sp]\", operands); - output_asm_insn (\"st.w r23, 40[sp]\", operands); - output_asm_insn (\"st.w r24, 36[sp]\", operands); - output_asm_insn (\"st.w r25, 32[sp]\", operands); - output_asm_insn (\"st.w r26, 28[sp]\", operands); - output_asm_insn (\"st.w r27, 24[sp]\", operands); - output_asm_insn (\"st.w r28, 20[sp]\", operands); - output_asm_insn (\"st.w r29, 16[sp]\", operands); + output_asm_insn ("st.w r31, 116[sp]", operands); + output_asm_insn ("st.w r2, 112[sp]", operands); + output_asm_insn ("st.w gp, 108[sp]", operands); + output_asm_insn ("st.w r6, 104[sp]", operands); + output_asm_insn ("st.w r7, 100[sp]", operands); + output_asm_insn ("st.w r8, 96[sp]", operands); + output_asm_insn ("st.w r9, 92[sp]", operands); + output_asm_insn ("st.w r11, 88[sp]", operands); + output_asm_insn ("st.w r12, 84[sp]", operands); + output_asm_insn ("st.w r13, 80[sp]", operands); + output_asm_insn ("st.w r14, 76[sp]", operands); + output_asm_insn ("st.w r15, 72[sp]", operands); + output_asm_insn ("st.w r16, 68[sp]", operands); + output_asm_insn ("st.w r17, 64[sp]", operands); + output_asm_insn ("st.w r18, 60[sp]", operands); + output_asm_insn ("st.w r19, 56[sp]", operands); + output_asm_insn ("st.w r20, 52[sp]", operands); + output_asm_insn ("st.w r21, 48[sp]", operands); + output_asm_insn ("st.w r22, 44[sp]", operands); + output_asm_insn ("st.w r23, 40[sp]", operands); + output_asm_insn ("st.w r24, 36[sp]", operands); + output_asm_insn ("st.w r25, 32[sp]", operands); + output_asm_insn ("st.w r26, 28[sp]", operands); + output_asm_insn ("st.w r27, 24[sp]", operands); + output_asm_insn ("st.w r28, 20[sp]", operands); + output_asm_insn ("st.w r29, 16[sp]", operands); } - return \"\"; -}" + return ""; +} [(set (attr "length") - (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) + (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) (const_int 62) )) @@ -2573,7 +3024,7 @@ (define_insn "callt_restore_all_interrupt" [(unspec_volatile [(const_int 0)] 1)] - "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" + "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_restore_all_interrupt)" [(set_attr "length" "2") (set_attr "cc" "none")]) @@ -2581,77 +3032,76 @@ (define_insn "restore_all_interrupt" [(unspec_volatile [(const_int 0)] 1)] "" - "* { if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) - return \"jarl __restore_all_interrupt,r10\"; + return "jarl __restore_all_interrupt,r10"; if (TARGET_EP) { - output_asm_insn (\"mov ep, r1\", operands); - output_asm_insn (\"mov sp, ep\", operands); - output_asm_insn (\"sld.w 116[ep], r31\", operands); - output_asm_insn (\"sld.w 112[ep], r2\", operands); - output_asm_insn (\"sld.w 108[ep], gp\", operands); - output_asm_insn (\"sld.w 104[ep], r6\", operands); - output_asm_insn (\"sld.w 100[ep], r7\", operands); - output_asm_insn (\"sld.w 96[ep], r8\", operands); - output_asm_insn (\"sld.w 92[ep], r9\", operands); - output_asm_insn (\"sld.w 88[ep], r11\", operands); - output_asm_insn (\"sld.w 84[ep], r12\", operands); - output_asm_insn (\"sld.w 80[ep], r13\", operands); - output_asm_insn (\"sld.w 76[ep], r14\", operands); - output_asm_insn (\"sld.w 72[ep], r15\", operands); - output_asm_insn (\"sld.w 68[ep], r16\", operands); - output_asm_insn (\"sld.w 64[ep], r17\", operands); - output_asm_insn (\"sld.w 60[ep], r18\", operands); - output_asm_insn (\"sld.w 56[ep], r19\", operands); - output_asm_insn (\"sld.w 52[ep], r20\", operands); - output_asm_insn (\"sld.w 48[ep], r21\", operands); - output_asm_insn (\"sld.w 44[ep], r22\", operands); - output_asm_insn (\"sld.w 40[ep], r23\", operands); - output_asm_insn (\"sld.w 36[ep], r24\", operands); - output_asm_insn (\"sld.w 32[ep], r25\", operands); - output_asm_insn (\"sld.w 28[ep], r26\", operands); - output_asm_insn (\"sld.w 24[ep], r27\", operands); - output_asm_insn (\"sld.w 20[ep], r28\", operands); - output_asm_insn (\"sld.w 16[ep], r29\", operands); - output_asm_insn (\"mov r1, ep\", operands); + output_asm_insn ("mov ep, r1", operands); + output_asm_insn ("mov sp, ep", operands); + output_asm_insn ("sld.w 116[ep], r31", operands); + output_asm_insn ("sld.w 112[ep], r2", operands); + output_asm_insn ("sld.w 108[ep], gp", operands); + output_asm_insn ("sld.w 104[ep], r6", operands); + output_asm_insn ("sld.w 100[ep], r7", operands); + output_asm_insn ("sld.w 96[ep], r8", operands); + output_asm_insn ("sld.w 92[ep], r9", operands); + output_asm_insn ("sld.w 88[ep], r11", operands); + output_asm_insn ("sld.w 84[ep], r12", operands); + output_asm_insn ("sld.w 80[ep], r13", operands); + output_asm_insn ("sld.w 76[ep], r14", operands); + output_asm_insn ("sld.w 72[ep], r15", operands); + output_asm_insn ("sld.w 68[ep], r16", operands); + output_asm_insn ("sld.w 64[ep], r17", operands); + output_asm_insn ("sld.w 60[ep], r18", operands); + output_asm_insn ("sld.w 56[ep], r19", operands); + output_asm_insn ("sld.w 52[ep], r20", operands); + output_asm_insn ("sld.w 48[ep], r21", operands); + output_asm_insn ("sld.w 44[ep], r22", operands); + output_asm_insn ("sld.w 40[ep], r23", operands); + output_asm_insn ("sld.w 36[ep], r24", operands); + output_asm_insn ("sld.w 32[ep], r25", operands); + output_asm_insn ("sld.w 28[ep], r26", operands); + output_asm_insn ("sld.w 24[ep], r27", operands); + output_asm_insn ("sld.w 20[ep], r28", operands); + output_asm_insn ("sld.w 16[ep], r29", operands); + output_asm_insn ("mov r1, ep", operands); } else { - output_asm_insn (\"ld.w 116[sp], r31\", operands); - output_asm_insn (\"ld.w 112[sp], r2\", operands); - output_asm_insn (\"ld.w 108[sp], gp\", operands); - output_asm_insn (\"ld.w 104[sp], r6\", operands); - output_asm_insn (\"ld.w 100[sp], r7\", operands); - output_asm_insn (\"ld.w 96[sp], r8\", operands); - output_asm_insn (\"ld.w 92[sp], r9\", operands); - output_asm_insn (\"ld.w 88[sp], r11\", operands); - output_asm_insn (\"ld.w 84[sp], r12\", operands); - output_asm_insn (\"ld.w 80[sp], r13\", operands); - output_asm_insn (\"ld.w 76[sp], r14\", operands); - output_asm_insn (\"ld.w 72[sp], r15\", operands); - output_asm_insn (\"ld.w 68[sp], r16\", operands); - output_asm_insn (\"ld.w 64[sp], r17\", operands); - output_asm_insn (\"ld.w 60[sp], r18\", operands); - output_asm_insn (\"ld.w 56[sp], r19\", operands); - output_asm_insn (\"ld.w 52[sp], r20\", operands); - output_asm_insn (\"ld.w 48[sp], r21\", operands); - output_asm_insn (\"ld.w 44[sp], r22\", operands); - output_asm_insn (\"ld.w 40[sp], r23\", operands); - output_asm_insn (\"ld.w 36[sp], r24\", operands); - output_asm_insn (\"ld.w 32[sp], r25\", operands); - output_asm_insn (\"ld.w 28[sp], r26\", operands); - output_asm_insn (\"ld.w 24[sp], r27\", operands); - output_asm_insn (\"ld.w 20[sp], r28\", operands); - output_asm_insn (\"ld.w 16[sp], r29\", operands); + output_asm_insn ("ld.w 116[sp], r31", operands); + output_asm_insn ("ld.w 112[sp], r2", operands); + output_asm_insn ("ld.w 108[sp], gp", operands); + output_asm_insn ("ld.w 104[sp], r6", operands); + output_asm_insn ("ld.w 100[sp], r7", operands); + output_asm_insn ("ld.w 96[sp], r8", operands); + output_asm_insn ("ld.w 92[sp], r9", operands); + output_asm_insn ("ld.w 88[sp], r11", operands); + output_asm_insn ("ld.w 84[sp], r12", operands); + output_asm_insn ("ld.w 80[sp], r13", operands); + output_asm_insn ("ld.w 76[sp], r14", operands); + output_asm_insn ("ld.w 72[sp], r15", operands); + output_asm_insn ("ld.w 68[sp], r16", operands); + output_asm_insn ("ld.w 64[sp], r17", operands); + output_asm_insn ("ld.w 60[sp], r18", operands); + output_asm_insn ("ld.w 56[sp], r19", operands); + output_asm_insn ("ld.w 52[sp], r20", operands); + output_asm_insn ("ld.w 48[sp], r21", operands); + output_asm_insn ("ld.w 44[sp], r22", operands); + output_asm_insn ("ld.w 40[sp], r23", operands); + output_asm_insn ("ld.w 36[sp], r24", operands); + output_asm_insn ("ld.w 32[sp], r25", operands); + output_asm_insn ("ld.w 28[sp], r26", operands); + output_asm_insn ("ld.w 24[sp], r27", operands); + output_asm_insn ("ld.w 20[sp], r28", operands); + output_asm_insn ("ld.w 16[sp], r29", operands); } - output_asm_insn (\"addi 120, sp, sp\", operands); - return \"\"; -}" + output_asm_insn ("addi 120, sp, sp", operands); + return ""; +} [(set (attr "length") - (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) + (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) (const_int 62) )) @@ -2663,5 +3113,3 @@ "jarl __restore_all_interrupt,r10" [(set_attr "length" "4") (set_attr "cc" "clobber")]) - -