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comparison gcc/config/aarch64/aarch64-simd-builtins.def @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
equal deleted inserted replaced
131:84e7813d76e9 145:1830386684a0
1 /* Machine description for AArch64 architecture. 1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2012-2018 Free Software Foundation, Inc. 2 Copyright (C) 2012-2020 Free Software Foundation, Inc.
3 Contributed by ARM Ltd. 3 Contributed by ARM Ltd.
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify it 7 GCC is free software; you can redistribute it and/or modify it
210 BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0) 210 BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
211 211
212 /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */ 212 /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */
213 BUILTIN_VB (TERNOP, sdot, 0) 213 BUILTIN_VB (TERNOP, sdot, 0)
214 BUILTIN_VB (TERNOPU, udot, 0) 214 BUILTIN_VB (TERNOPU, udot, 0)
215 BUILTIN_VB (TERNOP_SSUS, usdot, 0)
215 BUILTIN_VB (QUADOP_LANE, sdot_lane, 0) 216 BUILTIN_VB (QUADOP_LANE, sdot_lane, 0)
216 BUILTIN_VB (QUADOPU_LANE, udot_lane, 0) 217 BUILTIN_VB (QUADOPU_LANE, udot_lane, 0)
217 BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0) 218 BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0)
218 BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0) 219 BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0)
220 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0)
221 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0)
222 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0)
223 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0)
224
225 /* Implemented by aarch64_fcadd<rot><mode>. */
226 BUILTIN_VHSDF (BINOP, fcadd90, 0)
227 BUILTIN_VHSDF (BINOP, fcadd270, 0)
228
229 /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>. */
230 BUILTIN_VHSDF (TERNOP, fcmla0, 0)
231 BUILTIN_VHSDF (TERNOP, fcmla90, 0)
232 BUILTIN_VHSDF (TERNOP, fcmla180, 0)
233 BUILTIN_VHSDF (TERNOP, fcmla270, 0)
234 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0)
235 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0)
236 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0)
237 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0)
238
239 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0)
240 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0)
241 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0)
242 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0)
219 243
220 BUILTIN_VDQ_I (SHIFTIMM, ashr, 3) 244 BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
221 VAR1 (SHIFTIMM, ashr_simd, 0, di) 245 VAR1 (SHIFTIMM, ashr_simd, 0, di)
222 BUILTIN_VDQ_I (SHIFTIMM, lshr, 3) 246 BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
223 VAR1 (USHIFTIMM, lshr_simd, 0, di) 247 VAR1 (USHIFTIMM, lshr_simd, 0, di)
403 VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di) 427 VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
404 428
405 BUILTIN_VB (UNOP, rbit, 0) 429 BUILTIN_VB (UNOP, rbit, 0)
406 430
407 /* Implemented by 431 /* Implemented by
408 aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ 432 aarch64_<PERMUTE:perm_insn><mode>. */
409 BUILTIN_VALL (BINOP, zip1, 0) 433 BUILTIN_VALL (BINOP, zip1, 0)
410 BUILTIN_VALL (BINOP, zip2, 0) 434 BUILTIN_VALL (BINOP, zip2, 0)
411 BUILTIN_VALL (BINOP, uzp1, 0) 435 BUILTIN_VALL (BINOP, uzp1, 0)
412 BUILTIN_VALL (BINOP, uzp2, 0) 436 BUILTIN_VALL (BINOP, uzp2, 0)
413 BUILTIN_VALL (BINOP, trn1, 0) 437 BUILTIN_VALL (BINOP, trn1, 0)
444 VAR1(STORE1P, st1, 0, v2di) 468 VAR1(STORE1P, st1, 0, v2di)
445 469
446 /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */ 470 /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */
447 BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0) 471 BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0)
448 472
473 /* Implemented by aarch64_ld1x4<VALLDIF:mode>. */
474 BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0)
475
449 /* Implemented by aarch64_st1x2<VALLDIF:mode>. */ 476 /* Implemented by aarch64_st1x2<VALLDIF:mode>. */
450 BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0) 477 BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0)
451 478
452 /* Implemented by aarch64_st1x3<VALLDIF:mode>. */ 479 /* Implemented by aarch64_st1x3<VALLDIF:mode>. */
453 BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0) 480 BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0)
481
482 /* Implemented by aarch64_st1x4<VALLDIF:mode>. */
483 BUILTIN_VALLDIF (STORESTRUCT, st1x4, 0)
454 484
455 /* Implemented by fma<mode>4. */ 485 /* Implemented by fma<mode>4. */
456 BUILTIN_VHSDF (TERNOP, fma, 4) 486 BUILTIN_VHSDF (TERNOP, fma, 4)
457 VAR1 (TERNOP, fma, 4, hf) 487 VAR1 (TERNOP, fma, 4, hf)
458 /* Implemented by fnma<mode>4. */ 488 /* Implemented by fnma<mode>4. */
649 VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, v4sf) 679 VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, v4sf)
650 VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, v4sf) 680 VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, v4sf)
651 /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */ 681 /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */
652 VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, v4sf) 682 VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, v4sf)
653 VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, v4sf) 683 VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, v4sf)
684
685 /* Implemented by aarch64_<frintnzs_op><mode>. */
686 BUILTIN_VSFDF (UNOP, frint32z, 0)
687 BUILTIN_VSFDF (UNOP, frint32x, 0)
688 BUILTIN_VSFDF (UNOP, frint64z, 0)
689 BUILTIN_VSFDF (UNOP, frint64x, 0)
690
691 /* Implemented by aarch64_bfdot{_lane}{q}<mode>. */
692 VAR2 (TERNOP, bfdot, 0, v2sf, v4sf)
693 VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, v2sf, v4sf)
694 VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, v2sf, v4sf)
695
696 /* Implemented by aarch64_bfmmlaqv4sf */
697 VAR1 (TERNOP, bfmmlaq, 0, v4sf)
698
699 /* Implemented by aarch64_bfmlal<bt>{_lane{q}}v4sf */
700 VAR1 (TERNOP, bfmlalb, 0, v4sf)
701 VAR1 (TERNOP, bfmlalt, 0, v4sf)
702 VAR1 (QUADOP_LANE, bfmlalb_lane, 0, v4sf)
703 VAR1 (QUADOP_LANE, bfmlalt_lane, 0, v4sf)
704 VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, v4sf)
705 VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, v4sf)
706
707 /* Implemented by aarch64_simd_<sur>mmlav16qi. */
708 VAR1 (TERNOP, simd_smmla, 0, v16qi)
709 VAR1 (TERNOPU, simd_ummla, 0, v16qi)
710 VAR1 (TERNOP_SSUS, simd_usmmla, 0, v16qi)