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111
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1 /* Machine description for AArch64 architecture.
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145
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2 Copyright (C) 2012-2020 Free Software Foundation, Inc.
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111
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3 Contributed by ARM Ltd.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but
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13 WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
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22 builtins for each of the modes described by <ITERATOR>. When adding
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23 new builtins to this list, a helpful idiom to follow is to add
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24 a line for each pattern in the md file. Thus, ADDP, which has one
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25 pattern defined for the VD_BHSI iterator, and one for DImode, has two
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26 entries below.
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27
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28 Parameter 1 is the 'type' of the intrinsic. This is used to
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29 describe the type modifiers (for example; unsigned) applied to
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30 each of the parameters to the intrinsic function.
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31
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32 Parameter 2 is the name of the intrinsic. This is appended
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33 to `__builtin_aarch64_<name><mode>` to give the intrinsic name
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34 as exported to the front-ends.
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35
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36 Parameter 3 describes how to map from the name to the CODE_FOR_
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37 macro holding the RTL pattern for the intrinsic. This mapping is:
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38 0 - CODE_FOR_aarch64_<name><mode>
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39 1-9 - CODE_FOR_<name><mode><1-9>
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40 10 - CODE_FOR_<name><mode>. */
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41
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42 BUILTIN_VDC (COMBINE, combine, 0)
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43 VAR1 (COMBINEP, combine, 0, di)
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44 BUILTIN_VB (BINOP, pmul, 0)
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45 BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
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46 BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
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47 BUILTIN_VD_BHSI (BINOP, addp, 0)
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48 VAR1 (UNOP, addp, 0, di)
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49 BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
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50 BUILTIN_VDQ_BHSI (UNOP, clz, 2)
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51 BUILTIN_VS (UNOP, ctz, 2)
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52 BUILTIN_VB (UNOP, popcount, 2)
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53
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54 /* Implemented by aarch64_<sur>q<r>shl<mode>. */
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55 BUILTIN_VSDQ_I (BINOP, sqshl, 0)
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56 BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
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57 BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
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58 BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
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59 /* Implemented by aarch64_<su_optab><optab><mode>. */
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60 BUILTIN_VSDQ_I (BINOP, sqadd, 0)
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61 BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
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62 BUILTIN_VSDQ_I (BINOP, sqsub, 0)
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63 BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
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64 /* Implemented by aarch64_<sur>qadd<mode>. */
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65 BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
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66 BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
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67
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68 /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */
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69 BUILTIN_VDC (GETREG, get_dregoi, 0)
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70 BUILTIN_VDC (GETREG, get_dregci, 0)
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71 BUILTIN_VDC (GETREG, get_dregxi, 0)
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72 VAR1 (GETREGP, get_dregoi, 0, di)
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73 VAR1 (GETREGP, get_dregci, 0, di)
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74 VAR1 (GETREGP, get_dregxi, 0, di)
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75 /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */
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76 BUILTIN_VQ (GETREG, get_qregoi, 0)
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77 BUILTIN_VQ (GETREG, get_qregci, 0)
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78 BUILTIN_VQ (GETREG, get_qregxi, 0)
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79 VAR1 (GETREGP, get_qregoi, 0, v2di)
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80 VAR1 (GETREGP, get_qregci, 0, v2di)
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81 VAR1 (GETREGP, get_qregxi, 0, v2di)
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82 /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */
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83 BUILTIN_VQ (SETREG, set_qregoi, 0)
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84 BUILTIN_VQ (SETREG, set_qregci, 0)
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85 BUILTIN_VQ (SETREG, set_qregxi, 0)
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86 VAR1 (SETREGP, set_qregoi, 0, v2di)
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87 VAR1 (SETREGP, set_qregci, 0, v2di)
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88 VAR1 (SETREGP, set_qregxi, 0, v2di)
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131
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89 /* Implemented by aarch64_ld1x2<VQ:mode>. */
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90 BUILTIN_VQ (LOADSTRUCT, ld1x2, 0)
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91 /* Implemented by aarch64_ld1x2<VDC:mode>. */
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92 BUILTIN_VDC (LOADSTRUCT, ld1x2, 0)
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111
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93 /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
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94 BUILTIN_VDC (LOADSTRUCT, ld2, 0)
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95 BUILTIN_VDC (LOADSTRUCT, ld3, 0)
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96 BUILTIN_VDC (LOADSTRUCT, ld4, 0)
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97 /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */
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98 BUILTIN_VQ (LOADSTRUCT, ld2, 0)
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99 BUILTIN_VQ (LOADSTRUCT, ld3, 0)
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100 BUILTIN_VQ (LOADSTRUCT, ld4, 0)
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101 /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */
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102 BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
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103 BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
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104 BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
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105 /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */
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106 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
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107 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
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108 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
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109 /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */
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110 BUILTIN_VDC (STORESTRUCT, st2, 0)
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111 BUILTIN_VDC (STORESTRUCT, st3, 0)
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112 BUILTIN_VDC (STORESTRUCT, st4, 0)
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113 /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */
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114 BUILTIN_VQ (STORESTRUCT, st2, 0)
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115 BUILTIN_VQ (STORESTRUCT, st3, 0)
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116 BUILTIN_VQ (STORESTRUCT, st4, 0)
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117
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118 BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
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119 BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
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120 BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
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121
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122 BUILTIN_VQW (BINOP, saddl2, 0)
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123 BUILTIN_VQW (BINOP, uaddl2, 0)
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124 BUILTIN_VQW (BINOP, ssubl2, 0)
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125 BUILTIN_VQW (BINOP, usubl2, 0)
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126 BUILTIN_VQW (BINOP, saddw2, 0)
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127 BUILTIN_VQW (BINOP, uaddw2, 0)
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128 BUILTIN_VQW (BINOP, ssubw2, 0)
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129 BUILTIN_VQW (BINOP, usubw2, 0)
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130 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */
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131 BUILTIN_VD_BHSI (BINOP, saddl, 0)
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132 BUILTIN_VD_BHSI (BINOP, uaddl, 0)
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133 BUILTIN_VD_BHSI (BINOP, ssubl, 0)
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134 BUILTIN_VD_BHSI (BINOP, usubl, 0)
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135 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */
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136 BUILTIN_VD_BHSI (BINOP, saddw, 0)
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137 BUILTIN_VD_BHSI (BINOP, uaddw, 0)
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138 BUILTIN_VD_BHSI (BINOP, ssubw, 0)
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139 BUILTIN_VD_BHSI (BINOP, usubw, 0)
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140 /* Implemented by aarch64_<sur>h<addsub><mode>. */
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141 BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
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142 BUILTIN_VDQ_BHSI (BINOP, shsub, 0)
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143 BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
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144 BUILTIN_VDQ_BHSI (BINOP, uhsub, 0)
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145 BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
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146 BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
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147 /* Implemented by aarch64_<sur><addsub>hn<mode>. */
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148 BUILTIN_VQN (BINOP, addhn, 0)
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149 BUILTIN_VQN (BINOP, subhn, 0)
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150 BUILTIN_VQN (BINOP, raddhn, 0)
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151 BUILTIN_VQN (BINOP, rsubhn, 0)
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152 /* Implemented by aarch64_<sur><addsub>hn2<mode>. */
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153 BUILTIN_VQN (TERNOP, addhn2, 0)
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154 BUILTIN_VQN (TERNOP, subhn2, 0)
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155 BUILTIN_VQN (TERNOP, raddhn2, 0)
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156 BUILTIN_VQN (TERNOP, rsubhn2, 0)
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157
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158 BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
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159 /* Implemented by aarch64_<sur>qmovn<mode>. */
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160 BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
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161 BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
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162 /* Implemented by aarch64_s<optab><mode>. */
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163 BUILTIN_VSDQ_I (UNOP, sqabs, 0)
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164 BUILTIN_VSDQ_I (UNOP, sqneg, 0)
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165
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166 /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */
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167 BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
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168 BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
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169 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */
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170 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
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171 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
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172 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */
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173 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
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174 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
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175 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */
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176 BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
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177 BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
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178
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179 BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
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180 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
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181 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
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182 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
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183 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
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184 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
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185 BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
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186 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
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187
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188 BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
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189 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
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190 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
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191 BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
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192 BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
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193 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
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194 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
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195 BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
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196 /* Implemented by aarch64_sq<r>dmulh<mode>. */
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197 BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
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198 BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
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199 /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */
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200 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
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201 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
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202 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
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203 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
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204
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205 BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
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206 /* Implemented by aarch64_<sur>shl<mode>. */
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207 BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
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208 BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
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209 BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
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210 BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
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211
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212 /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */
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213 BUILTIN_VB (TERNOP, sdot, 0)
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214 BUILTIN_VB (TERNOPU, udot, 0)
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215 BUILTIN_VB (TERNOP_SSUS, usdot, 0)
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111
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216 BUILTIN_VB (QUADOP_LANE, sdot_lane, 0)
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217 BUILTIN_VB (QUADOPU_LANE, udot_lane, 0)
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218 BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0)
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219 BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0)
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145
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220 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0)
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221 BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0)
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222 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0)
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223 BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0)
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224
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225 /* Implemented by aarch64_fcadd<rot><mode>. */
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226 BUILTIN_VHSDF (BINOP, fcadd90, 0)
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227 BUILTIN_VHSDF (BINOP, fcadd270, 0)
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228
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229 /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>. */
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230 BUILTIN_VHSDF (TERNOP, fcmla0, 0)
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231 BUILTIN_VHSDF (TERNOP, fcmla90, 0)
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232 BUILTIN_VHSDF (TERNOP, fcmla180, 0)
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233 BUILTIN_VHSDF (TERNOP, fcmla270, 0)
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234 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0)
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235 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0)
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236 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0)
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237 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0)
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238
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239 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0)
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240 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0)
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241 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0)
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242 BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0)
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111
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243
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244 BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
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245 VAR1 (SHIFTIMM, ashr_simd, 0, di)
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246 BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
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247 VAR1 (USHIFTIMM, lshr_simd, 0, di)
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248 /* Implemented by aarch64_<sur>shr_n<mode>. */
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249 BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
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250 BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
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251 /* Implemented by aarch64_<sur>sra_n<mode>. */
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252 BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
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253 BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
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254 BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
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255 BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
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256 /* Implemented by aarch64_<sur>shll_n<mode>. */
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257 BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
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258 BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
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259 /* Implemented by aarch64_<sur>shll2_n<mode>. */
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260 BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
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261 BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
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262 /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */
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263 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
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264 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
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265 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
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266 BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
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267 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
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268 BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
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|
|
269 /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */
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|
|
270 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
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|
271 BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
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|
|
272 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
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|
|
273 VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
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|
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274 BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
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|
|
275 /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */
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|
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276 BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
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277 BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
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|
|
278 BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
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|
|
279
|
|
|
280 /* Implemented by aarch64_reduc_plus_<mode>. */
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|
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281 BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
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|
282
|
|
|
283 /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */
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|
|
284 BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10)
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|
|
285 BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10)
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|
|
286 BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
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|
|
287 BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
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|
|
288 BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10)
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|
|
289 BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10)
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|
|
290
|
|
|
291 /* Implemented by <maxmin_uns><mode>3.
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|
|
292 smax variants map to fmaxnm,
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|
|
293 smax_nan variants map to fmax. */
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|
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294 BUILTIN_VDQ_BHSI (BINOP, smax, 3)
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|
|
295 BUILTIN_VDQ_BHSI (BINOP, smin, 3)
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|
|
296 BUILTIN_VDQ_BHSI (BINOP, umax, 3)
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|
|
297 BUILTIN_VDQ_BHSI (BINOP, umin, 3)
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|
|
298 BUILTIN_VHSDF_DF (BINOP, smax_nan, 3)
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|
|
299 BUILTIN_VHSDF_DF (BINOP, smin_nan, 3)
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|
|
300
|
|
|
301 /* Implemented by <maxmin_uns><mode>3. */
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|
|
302 BUILTIN_VHSDF_HSDF (BINOP, fmax, 3)
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|
|
303 BUILTIN_VHSDF_HSDF (BINOP, fmin, 3)
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|
|
304
|
|
|
305 /* Implemented by aarch64_<maxmin_uns>p<mode>. */
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|
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306 BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
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|
|
307 BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
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|
|
308 BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
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|
|
309 BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
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|
|
310 BUILTIN_VHSDF (BINOP, smaxp, 0)
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|
|
311 BUILTIN_VHSDF (BINOP, sminp, 0)
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|
|
312 BUILTIN_VHSDF (BINOP, smax_nanp, 0)
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|
|
313 BUILTIN_VHSDF (BINOP, smin_nanp, 0)
|
|
|
314
|
|
|
315 /* Implemented by <frint_pattern><mode>2. */
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|
|
316 BUILTIN_VHSDF (UNOP, btrunc, 2)
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|
|
317 BUILTIN_VHSDF (UNOP, ceil, 2)
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|
|
318 BUILTIN_VHSDF (UNOP, floor, 2)
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|
|
319 BUILTIN_VHSDF (UNOP, nearbyint, 2)
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|
|
320 BUILTIN_VHSDF (UNOP, rint, 2)
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|
|
321 BUILTIN_VHSDF (UNOP, round, 2)
|
|
|
322 BUILTIN_VHSDF_DF (UNOP, frintn, 2)
|
|
|
323
|
|
|
324 VAR1 (UNOP, btrunc, 2, hf)
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|
|
325 VAR1 (UNOP, ceil, 2, hf)
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|
|
326 VAR1 (UNOP, floor, 2, hf)
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|
|
327 VAR1 (UNOP, frintn, 2, hf)
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|
|
328 VAR1 (UNOP, nearbyint, 2, hf)
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|
|
329 VAR1 (UNOP, rint, 2, hf)
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|
|
330 VAR1 (UNOP, round, 2, hf)
|
|
|
331
|
|
|
332 /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
|
|
|
333 VAR1 (UNOP, lbtruncv4hf, 2, v4hi)
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|
|
334 VAR1 (UNOP, lbtruncv8hf, 2, v8hi)
|
|
|
335 VAR1 (UNOP, lbtruncv2sf, 2, v2si)
|
|
|
336 VAR1 (UNOP, lbtruncv4sf, 2, v4si)
|
|
|
337 VAR1 (UNOP, lbtruncv2df, 2, v2di)
|
|
|
338
|
|
|
339 VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi)
|
|
|
340 VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi)
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|
|
341 VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
|
|
|
342 VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
|
|
|
343 VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
|
|
|
344
|
|
|
345 VAR1 (UNOP, lroundv4hf, 2, v4hi)
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|
|
346 VAR1 (UNOP, lroundv8hf, 2, v8hi)
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|
|
347 VAR1 (UNOP, lroundv2sf, 2, v2si)
|
|
|
348 VAR1 (UNOP, lroundv4sf, 2, v4si)
|
|
|
349 VAR1 (UNOP, lroundv2df, 2, v2di)
|
|
|
350 /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2. */
|
|
|
351 BUILTIN_GPI_I16 (UNOP, lroundhf, 2)
|
|
|
352 VAR1 (UNOP, lroundsf, 2, si)
|
|
|
353 VAR1 (UNOP, lrounddf, 2, di)
|
|
|
354
|
|
|
355 VAR1 (UNOPUS, lrounduv4hf, 2, v4hi)
|
|
|
356 VAR1 (UNOPUS, lrounduv8hf, 2, v8hi)
|
|
|
357 VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
|
|
|
358 VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
|
|
|
359 VAR1 (UNOPUS, lrounduv2df, 2, v2di)
|
|
|
360 BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2)
|
|
|
361 VAR1 (UNOPUS, lroundusf, 2, si)
|
|
|
362 VAR1 (UNOPUS, lroundudf, 2, di)
|
|
|
363
|
|
|
364 VAR1 (UNOP, lceilv4hf, 2, v4hi)
|
|
|
365 VAR1 (UNOP, lceilv8hf, 2, v8hi)
|
|
|
366 VAR1 (UNOP, lceilv2sf, 2, v2si)
|
|
|
367 VAR1 (UNOP, lceilv4sf, 2, v4si)
|
|
|
368 VAR1 (UNOP, lceilv2df, 2, v2di)
|
|
|
369 BUILTIN_GPI_I16 (UNOP, lceilhf, 2)
|
|
|
370
|
|
|
371 VAR1 (UNOPUS, lceiluv4hf, 2, v4hi)
|
|
|
372 VAR1 (UNOPUS, lceiluv8hf, 2, v8hi)
|
|
|
373 VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
|
|
|
374 VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
|
|
|
375 VAR1 (UNOPUS, lceiluv2df, 2, v2di)
|
|
|
376 BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2)
|
|
|
377 VAR1 (UNOPUS, lceilusf, 2, si)
|
|
|
378 VAR1 (UNOPUS, lceiludf, 2, di)
|
|
|
379
|
|
|
380 VAR1 (UNOP, lfloorv4hf, 2, v4hi)
|
|
|
381 VAR1 (UNOP, lfloorv8hf, 2, v8hi)
|
|
|
382 VAR1 (UNOP, lfloorv2sf, 2, v2si)
|
|
|
383 VAR1 (UNOP, lfloorv4sf, 2, v4si)
|
|
|
384 VAR1 (UNOP, lfloorv2df, 2, v2di)
|
|
|
385 BUILTIN_GPI_I16 (UNOP, lfloorhf, 2)
|
|
|
386
|
|
|
387 VAR1 (UNOPUS, lflooruv4hf, 2, v4hi)
|
|
|
388 VAR1 (UNOPUS, lflooruv8hf, 2, v8hi)
|
|
|
389 VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
|
|
|
390 VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
|
|
|
391 VAR1 (UNOPUS, lflooruv2df, 2, v2di)
|
|
|
392 BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2)
|
|
|
393 VAR1 (UNOPUS, lfloorusf, 2, si)
|
|
|
394 VAR1 (UNOPUS, lfloorudf, 2, di)
|
|
|
395
|
|
|
396 VAR1 (UNOP, lfrintnv4hf, 2, v4hi)
|
|
|
397 VAR1 (UNOP, lfrintnv8hf, 2, v8hi)
|
|
|
398 VAR1 (UNOP, lfrintnv2sf, 2, v2si)
|
|
|
399 VAR1 (UNOP, lfrintnv4sf, 2, v4si)
|
|
|
400 VAR1 (UNOP, lfrintnv2df, 2, v2di)
|
|
|
401 BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2)
|
|
|
402 VAR1 (UNOP, lfrintnsf, 2, si)
|
|
|
403 VAR1 (UNOP, lfrintndf, 2, di)
|
|
|
404
|
|
|
405 VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi)
|
|
|
406 VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi)
|
|
|
407 VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
|
|
|
408 VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
|
|
|
409 VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
|
|
|
410 BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2)
|
|
|
411 VAR1 (UNOPUS, lfrintnusf, 2, si)
|
|
|
412 VAR1 (UNOPUS, lfrintnudf, 2, di)
|
|
|
413
|
|
|
414 /* Implemented by <optab><fcvt_target><VDQF:mode>2. */
|
|
|
415 VAR1 (UNOP, floatv4hi, 2, v4hf)
|
|
|
416 VAR1 (UNOP, floatv8hi, 2, v8hf)
|
|
|
417 VAR1 (UNOP, floatv2si, 2, v2sf)
|
|
|
418 VAR1 (UNOP, floatv4si, 2, v4sf)
|
|
|
419 VAR1 (UNOP, floatv2di, 2, v2df)
|
|
|
420
|
|
|
421 VAR1 (UNOP, floatunsv4hi, 2, v4hf)
|
|
|
422 VAR1 (UNOP, floatunsv8hi, 2, v8hf)
|
|
|
423 VAR1 (UNOP, floatunsv2si, 2, v2sf)
|
|
|
424 VAR1 (UNOP, floatunsv4si, 2, v4sf)
|
|
|
425 VAR1 (UNOP, floatunsv2di, 2, v2df)
|
|
|
426
|
|
|
427 VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
|
|
|
428
|
|
|
429 BUILTIN_VB (UNOP, rbit, 0)
|
|
|
430
|
|
|
431 /* Implemented by
|
|
145
|
432 aarch64_<PERMUTE:perm_insn><mode>. */
|
|
111
|
433 BUILTIN_VALL (BINOP, zip1, 0)
|
|
|
434 BUILTIN_VALL (BINOP, zip2, 0)
|
|
|
435 BUILTIN_VALL (BINOP, uzp1, 0)
|
|
|
436 BUILTIN_VALL (BINOP, uzp2, 0)
|
|
|
437 BUILTIN_VALL (BINOP, trn1, 0)
|
|
|
438 BUILTIN_VALL (BINOP, trn2, 0)
|
|
|
439
|
|
|
440 BUILTIN_GPF_F16 (UNOP, frecpe, 0)
|
|
|
441 BUILTIN_GPF_F16 (UNOP, frecpx, 0)
|
|
|
442
|
|
|
443 BUILTIN_VDQ_SI (UNOP, urecpe, 0)
|
|
|
444
|
|
|
445 BUILTIN_VHSDF (UNOP, frecpe, 0)
|
|
|
446 BUILTIN_VHSDF_HSDF (BINOP, frecps, 0)
|
|
|
447
|
|
|
448 /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is
|
|
|
449 only ever used for the int64x1_t intrinsic, there is no scalar version. */
|
|
|
450 BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
|
|
|
451 BUILTIN_VHSDF (UNOP, abs, 2)
|
|
|
452 VAR1 (UNOP, abs, 2, hf)
|
|
|
453
|
|
|
454 BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
|
|
|
455 VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
|
|
|
456 VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
|
|
|
457
|
|
|
458 VAR1 (UNOP, float_extend_lo_, 0, v2df)
|
|
|
459 VAR1 (UNOP, float_extend_lo_, 0, v4sf)
|
|
|
460 BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
|
|
|
461
|
|
|
462 /* Implemented by aarch64_ld1<VALL_F16:mode>. */
|
|
|
463 BUILTIN_VALL_F16 (LOAD1, ld1, 0)
|
|
|
464 VAR1(STORE1P, ld1, 0, v2di)
|
|
|
465
|
|
|
466 /* Implemented by aarch64_st1<VALL_F16:mode>. */
|
|
|
467 BUILTIN_VALL_F16 (STORE1, st1, 0)
|
|
|
468 VAR1(STORE1P, st1, 0, v2di)
|
|
|
469
|
|
131
|
470 /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */
|
|
|
471 BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0)
|
|
|
472
|
|
145
|
473 /* Implemented by aarch64_ld1x4<VALLDIF:mode>. */
|
|
|
474 BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0)
|
|
|
475
|
|
131
|
476 /* Implemented by aarch64_st1x2<VALLDIF:mode>. */
|
|
|
477 BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0)
|
|
|
478
|
|
|
479 /* Implemented by aarch64_st1x3<VALLDIF:mode>. */
|
|
|
480 BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0)
|
|
|
481
|
|
145
|
482 /* Implemented by aarch64_st1x4<VALLDIF:mode>. */
|
|
|
483 BUILTIN_VALLDIF (STORESTRUCT, st1x4, 0)
|
|
|
484
|
|
111
|
485 /* Implemented by fma<mode>4. */
|
|
|
486 BUILTIN_VHSDF (TERNOP, fma, 4)
|
|
|
487 VAR1 (TERNOP, fma, 4, hf)
|
|
|
488 /* Implemented by fnma<mode>4. */
|
|
|
489 BUILTIN_VHSDF (TERNOP, fnma, 4)
|
|
|
490 VAR1 (TERNOP, fnma, 4, hf)
|
|
|
491
|
|
|
492 /* Implemented by aarch64_simd_bsl<mode>. */
|
|
|
493 BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
|
|
|
494 VAR2 (BSL_P, simd_bsl,0, di, v2di)
|
|
|
495 BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
|
|
|
496 BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
|
|
|
497
|
|
|
498 /* Implemented by aarch64_crypto_aes<op><mode>. */
|
|
|
499 VAR1 (BINOPU, crypto_aese, 0, v16qi)
|
|
|
500 VAR1 (BINOPU, crypto_aesd, 0, v16qi)
|
|
|
501 VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
|
|
|
502 VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
|
|
|
503
|
|
|
504 /* Implemented by aarch64_crypto_sha1<op><mode>. */
|
|
|
505 VAR1 (UNOPU, crypto_sha1h, 0, si)
|
|
|
506 VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
|
|
|
507 VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
|
|
|
508 VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
|
|
|
509 VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
|
|
|
510 VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
|
|
|
511
|
|
|
512 /* Implemented by aarch64_crypto_sha256<op><mode>. */
|
|
|
513 VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
|
|
|
514 VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
|
|
|
515 VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
|
|
|
516 VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
|
|
|
517
|
|
|
518 /* Implemented by aarch64_crypto_pmull<mode>. */
|
|
|
519 VAR1 (BINOPP, crypto_pmull, 0, di)
|
|
|
520 VAR1 (BINOPP, crypto_pmull, 0, v2di)
|
|
|
521
|
|
|
522 /* Implemented by aarch64_tbl3<mode>. */
|
|
|
523 VAR1 (BINOP, tbl3, 0, v8qi)
|
|
|
524 VAR1 (BINOP, tbl3, 0, v16qi)
|
|
|
525
|
|
|
526 /* Implemented by aarch64_qtbl3<mode>. */
|
|
|
527 VAR1 (BINOP, qtbl3, 0, v8qi)
|
|
|
528 VAR1 (BINOP, qtbl3, 0, v16qi)
|
|
|
529
|
|
|
530 /* Implemented by aarch64_qtbl4<mode>. */
|
|
|
531 VAR1 (BINOP, qtbl4, 0, v8qi)
|
|
|
532 VAR1 (BINOP, qtbl4, 0, v16qi)
|
|
|
533
|
|
|
534 /* Implemented by aarch64_tbx4<mode>. */
|
|
|
535 VAR1 (TERNOP, tbx4, 0, v8qi)
|
|
|
536 VAR1 (TERNOP, tbx4, 0, v16qi)
|
|
|
537
|
|
|
538 /* Implemented by aarch64_qtbx3<mode>. */
|
|
|
539 VAR1 (TERNOP, qtbx3, 0, v8qi)
|
|
|
540 VAR1 (TERNOP, qtbx3, 0, v16qi)
|
|
|
541
|
|
|
542 /* Implemented by aarch64_qtbx4<mode>. */
|
|
|
543 VAR1 (TERNOP, qtbx4, 0, v8qi)
|
|
|
544 VAR1 (TERNOP, qtbx4, 0, v16qi)
|
|
|
545
|
|
|
546 /* Builtins for ARMv8.1-A Adv.SIMD instructions. */
|
|
|
547
|
|
|
548 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */
|
|
|
549 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
|
|
|
550 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
|
|
|
551
|
|
|
552 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */
|
|
|
553 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
|
|
|
554 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
|
|
|
555
|
|
|
556 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */
|
|
|
557 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
|
|
|
558 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
|
|
|
559
|
|
|
560 /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */
|
|
|
561 BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
|
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562 BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
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563 BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3)
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564 BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3)
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565 VAR1 (SHIFTIMM, scvtfsi, 3, hf)
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566 VAR1 (SHIFTIMM, scvtfdi, 3, hf)
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567 VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf)
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568 VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf)
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569 BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3)
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570 BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3)
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571
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572 /* Implemented by aarch64_rsqrte<mode>. */
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573 BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0)
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574
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575 /* Implemented by aarch64_rsqrts<mode>. */
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576 BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0)
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577
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578 /* Implemented by fabd<mode>3. */
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579 BUILTIN_VHSDF_HSDF (BINOP, fabd, 3)
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580
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581 /* Implemented by aarch64_faddp<mode>. */
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582 BUILTIN_VHSDF (BINOP, faddp, 0)
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583
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584 /* Implemented by aarch64_cm<optab><mode>. */
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585 BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0)
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586 BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0)
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587 BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0)
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588 BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0)
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589 BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0)
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590
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591 /* Implemented by neg<mode>2. */
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592 BUILTIN_VHSDF_HSDF (UNOP, neg, 2)
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593
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594 /* Implemented by aarch64_fac<optab><mode>. */
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595 BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0)
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596 BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0)
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597 BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0)
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598 BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0)
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599
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600 /* Implemented by sqrt<mode>2. */
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601 VAR1 (UNOP, sqrt, 2, hf)
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602
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603 /* Implemented by <optab><mode>hf2. */
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604 VAR1 (UNOP, floatdi, 2, hf)
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605 VAR1 (UNOP, floatsi, 2, hf)
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606 VAR1 (UNOP, floathi, 2, hf)
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607 VAR1 (UNOPUS, floatunsdi, 2, hf)
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608 VAR1 (UNOPUS, floatunssi, 2, hf)
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609 VAR1 (UNOPUS, floatunshi, 2, hf)
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610 BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2)
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611 BUILTIN_GPI (UNOP, fix_truncsf, 2)
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612 BUILTIN_GPI (UNOP, fix_truncdf, 2)
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613 BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
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614 BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
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131
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615 BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
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616
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617 /* Implemented by aarch64_sm3ss1qv4si. */
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618 VAR1 (TERNOPU, sm3ss1q, 0, v4si)
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619 /* Implemented by aarch64_sm3tt<sm3tt_op>qv4si. */
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620 VAR1 (QUADOPUI, sm3tt1aq, 0, v4si)
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621 VAR1 (QUADOPUI, sm3tt1bq, 0, v4si)
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622 VAR1 (QUADOPUI, sm3tt2aq, 0, v4si)
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623 VAR1 (QUADOPUI, sm3tt2bq, 0, v4si)
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624 /* Implemented by aarch64_sm3partw<sm3part_op>qv4si. */
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625 VAR1 (TERNOPU, sm3partw1q, 0, v4si)
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626 VAR1 (TERNOPU, sm3partw2q, 0, v4si)
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627 /* Implemented by aarch64_sm4eqv4si. */
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628 VAR1 (BINOPU, sm4eq, 0, v4si)
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629 /* Implemented by aarch64_sm4ekeyqv4si. */
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630 VAR1 (BINOPU, sm4ekeyq, 0, v4si)
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631 /* Implemented by aarch64_crypto_sha512hqv2di. */
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632 VAR1 (TERNOPU, crypto_sha512hq, 0, v2di)
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633 /* Implemented by aarch64_sha512h2qv2di. */
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634 VAR1 (TERNOPU, crypto_sha512h2q, 0, v2di)
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|
635 /* Implemented by aarch64_crypto_sha512su0qv2di. */
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636 VAR1 (BINOPU, crypto_sha512su0q, 0, v2di)
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|
637 /* Implemented by aarch64_crypto_sha512su1qv2di. */
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638 VAR1 (TERNOPU, crypto_sha512su1q, 0, v2di)
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639 /* Implemented by eor3q<mode>4. */
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640 BUILTIN_VQ_I (TERNOPU, eor3q, 4)
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641 BUILTIN_VQ_I (TERNOP, eor3q, 4)
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642 /* Implemented by aarch64_rax1qv2di. */
|
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643 VAR1 (BINOPU, rax1q, 0, v2di)
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644 /* Implemented by aarch64_xarqv2di. */
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645 VAR1 (TERNOPUI, xarq, 0, v2di)
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646 /* Implemented by bcaxq<mode>4. */
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647 BUILTIN_VQ_I (TERNOPU, bcaxq, 4)
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648 BUILTIN_VQ_I (TERNOP, bcaxq, 4)
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649
|
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|
650 /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */
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651 VAR1 (TERNOP, fmlal_low, 0, v2sf)
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652 VAR1 (TERNOP, fmlsl_low, 0, v2sf)
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653 VAR1 (TERNOP, fmlalq_low, 0, v4sf)
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654 VAR1 (TERNOP, fmlslq_low, 0, v4sf)
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655 /* Implemented by aarch64_fml<f16mac1>l<f16quad>_high<mode>. */
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656 VAR1 (TERNOP, fmlal_high, 0, v2sf)
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657 VAR1 (TERNOP, fmlsl_high, 0, v2sf)
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658 VAR1 (TERNOP, fmlalq_high, 0, v4sf)
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659 VAR1 (TERNOP, fmlslq_high, 0, v4sf)
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660 /* Implemented by aarch64_fml<f16mac1>l_lane_lowv2sf. */
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661 VAR1 (QUADOP_LANE, fmlal_lane_low, 0, v2sf)
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662 VAR1 (QUADOP_LANE, fmlsl_lane_low, 0, v2sf)
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663 /* Implemented by aarch64_fml<f16mac1>l_laneq_lowv2sf. */
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|
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664 VAR1 (QUADOP_LANE, fmlal_laneq_low, 0, v2sf)
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|
665 VAR1 (QUADOP_LANE, fmlsl_laneq_low, 0, v2sf)
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666 /* Implemented by aarch64_fml<f16mac1>lq_lane_lowv4sf. */
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|
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667 VAR1 (QUADOP_LANE, fmlalq_lane_low, 0, v4sf)
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668 VAR1 (QUADOP_LANE, fmlslq_lane_low, 0, v4sf)
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|
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669 /* Implemented by aarch64_fml<f16mac1>lq_laneq_lowv4sf. */
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|
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670 VAR1 (QUADOP_LANE, fmlalq_laneq_low, 0, v4sf)
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|
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671 VAR1 (QUADOP_LANE, fmlslq_laneq_low, 0, v4sf)
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|
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672 /* Implemented by aarch64_fml<f16mac1>l_lane_highv2sf. */
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673 VAR1 (QUADOP_LANE, fmlal_lane_high, 0, v2sf)
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674 VAR1 (QUADOP_LANE, fmlsl_lane_high, 0, v2sf)
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|
675 /* Implemented by aarch64_fml<f16mac1>l_laneq_highv2sf. */
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676 VAR1 (QUADOP_LANE, fmlal_laneq_high, 0, v2sf)
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|
|
677 VAR1 (QUADOP_LANE, fmlsl_laneq_high, 0, v2sf)
|
|
|
678 /* Implemented by aarch64_fml<f16mac1>lq_lane_highv4sf. */
|
|
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679 VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, v4sf)
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|
|
680 VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, v4sf)
|
|
|
681 /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */
|
|
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682 VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, v4sf)
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|
|
683 VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, v4sf)
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|
145
|
684
|
|
|
685 /* Implemented by aarch64_<frintnzs_op><mode>. */
|
|
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686 BUILTIN_VSFDF (UNOP, frint32z, 0)
|
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|
687 BUILTIN_VSFDF (UNOP, frint32x, 0)
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688 BUILTIN_VSFDF (UNOP, frint64z, 0)
|
|
|
689 BUILTIN_VSFDF (UNOP, frint64x, 0)
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|
|
690
|
|
|
691 /* Implemented by aarch64_bfdot{_lane}{q}<mode>. */
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|
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692 VAR2 (TERNOP, bfdot, 0, v2sf, v4sf)
|
|
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693 VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, v2sf, v4sf)
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|
|
694 VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, v2sf, v4sf)
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695
|
|
|
696 /* Implemented by aarch64_bfmmlaqv4sf */
|
|
|
697 VAR1 (TERNOP, bfmmlaq, 0, v4sf)
|
|
|
698
|
|
|
699 /* Implemented by aarch64_bfmlal<bt>{_lane{q}}v4sf */
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700 VAR1 (TERNOP, bfmlalb, 0, v4sf)
|
|
|
701 VAR1 (TERNOP, bfmlalt, 0, v4sf)
|
|
|
702 VAR1 (QUADOP_LANE, bfmlalb_lane, 0, v4sf)
|
|
|
703 VAR1 (QUADOP_LANE, bfmlalt_lane, 0, v4sf)
|
|
|
704 VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, v4sf)
|
|
|
705 VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, v4sf)
|
|
|
706
|
|
|
707 /* Implemented by aarch64_simd_<sur>mmlav16qi. */
|
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|
708 VAR1 (TERNOP, simd_smmla, 0, v16qi)
|
|
|
709 VAR1 (TERNOPU, simd_ummla, 0, v16qi)
|
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|
710 VAR1 (TERNOP_SSUS, simd_usmmla, 0, v16qi)
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