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comparison gcc/config/aarch64/saphira.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
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131:84e7813d76e9 145:1830386684a0
1 ;; Saphira pipeline description
2 ;; Copyright (C) 2017-2020 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
10 ;;
11 ;; GCC is distributed in the hope that it will be useful, but
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 ;; General Public License for more details.
15 ;;
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 (define_automaton "saphira")
21
22 ;; Complex int instructions (e.g. multiply and divide) execute in the X
23 ;; pipeline. Simple int instructions execute in the X, Y, Z and B pipelines.
24
25 (define_cpu_unit "saphira_x" "saphira")
26 (define_cpu_unit "saphira_y" "saphira")
27
28 ;; Branches execute in the Z or B pipeline or in one of the int pipelines depending
29 ;; on how complex it is. Simple int insns (like movz) can also execute here.
30
31 (define_cpu_unit "saphira_z" "saphira")
32 (define_cpu_unit "saphira_b" "saphira")
33
34 ;; Vector and FP insns execute in the VX and VY pipelines.
35
36 (define_automaton "saphira_vfp")
37
38 (define_cpu_unit "saphira_vx" "saphira_vfp")
39 (define_cpu_unit "saphira_vy" "saphira_vfp")
40
41 ;; Loads execute in the LD pipeline.
42 ;; Stores execute in the ST pipeline, for address, data, and
43 ;; vector data.
44
45 (define_automaton "saphira_mem")
46
47 (define_cpu_unit "saphira_ld" "saphira_mem")
48 (define_cpu_unit "saphira_st" "saphira_mem")
49
50 ;; The GTOV and VTOG pipelines are for general to vector reg moves, and vice
51 ;; versa.
52
53 (define_cpu_unit "saphira_gtov" "saphira")
54 (define_cpu_unit "saphira_vtog" "saphira")
55
56 ;; Common reservation combinations.
57
58 (define_reservation "saphira_vxvy" "saphira_vx|saphira_vy")
59 (define_reservation "saphira_zb" "saphira_z|saphira_b")
60 (define_reservation "saphira_xyzb" "saphira_x|saphira_y|saphira_z|saphira_b")
61
62 ;; SIMD Floating-Point Instructions
63
64 (define_insn_reservation "saphira_afp_1_vxvy" 1
65 (and (eq_attr "tune" "saphira")
66 (eq_attr "type" "neon_fp_neg_s,neon_fp_neg_d,neon_fp_abs_s,neon_fp_abs_d,neon_fp_neg_s_q,neon_fp_neg_d_q,neon_fp_abs_s_q,neon_fp_abs_d_q"))
67 "saphira_vxvy")
68
69 (define_insn_reservation "saphira_afp_2_vxvy" 2
70 (and (eq_attr "tune" "saphira")
71 (eq_attr "type" "neon_fp_minmax_s,neon_fp_minmax_d,neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d,neon_fp_compare_s,neon_fp_compare_d,neon_fp_round_s,neon_fp_round_d,neon_fp_minmax_s_q,neon_fp_minmax_d_q,neon_fp_compare_s_q,neon_fp_compare_d_q,neon_fp_round_s_q,neon_fp_round_d_q"))
72 "saphira_vxvy")
73
74 (define_insn_reservation "saphira_afp_3_vxvy" 3
75 (and (eq_attr "tune" "saphira")
76 (eq_attr "type" "neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q,neon_fp_abd_s,neon_fp_abd_d,neon_fp_addsub_s,neon_fp_addsub_d,neon_fp_reduc_add_s,neon_fp_reduc_add_d,neon_fp_abd_s_q,neon_fp_abd_d_q,neon_fp_addsub_s_q,neon_fp_addsub_d_q,neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q"))
77 "saphira_vxvy")
78
79 (define_insn_reservation "saphira_afp_4_vxvy" 4
80 (and (eq_attr "tune" "saphira")
81 (eq_attr "type" "neon_fp_to_int_s,neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d,neon_fp_cvt_widen_h,neon_fp_cvt_widen_s,neon_fp_to_int_s_q,neon_fp_to_int_d_q,neon_int_to_fp_s_q,neon_int_to_fp_d_q"))
82 "saphira_vxvy")
83
84 (define_insn_reservation "saphira_afp_5_vxvy_mul" 5
85 (and (eq_attr "tune" "saphira")
86 (eq_attr "type" "neon_fp_mul_s,neon_fp_mul_s_scalar,neon_fp_mul_s_q,neon_fp_mul_s_scalar_q"))
87 "saphira_vxvy")
88
89 (define_insn_reservation "saphira_afp_5_vxvy_mla" 5
90 (and (eq_attr "tune" "saphira")
91 (eq_attr "type" "neon_fp_mla_s,neon_fp_mla_s_scalar,neon_fp_mla_s_q,neon_fp_mla_s_scalar_q"))
92 "saphira_vxvy")
93
94 (define_insn_reservation "saphira_afp_6_vxvy_mul" 6
95 (and (eq_attr "tune" "saphira")
96 (eq_attr "type" "neon_fp_mul_d,neon_fp_mul_d_q,neon_fp_mul_d_scalar_q"))
97 "saphira_vxvy")
98
99 (define_insn_reservation "saphira_afp_6_vxvy_mla" 6
100 (and (eq_attr "tune" "saphira")
101 (eq_attr "type" "neon_fp_mla_d,neon_fp_mla_d_q,neon_fp_mla_d_scalar_q"))
102 "saphira_vxvy")
103
104 (define_insn_reservation "saphira_afp_4_vxvy_vxvy_vxvy" 4
105 (and (eq_attr "tune" "saphira")
106 (eq_attr "type" "neon_fp_cvt_narrow_s_q,neon_fp_cvt_narrow_d_q"))
107 "saphira_vxvy+saphira_vxvy,saphira_vxvy")
108
109 (define_insn_reservation "saphira_afp_6_vx_vy" 6
110 (and (eq_attr "tune" "saphira")
111 (eq_attr "type" "neon_fp_div_s"))
112 "saphira_vx+saphira_vy")
113
114 (define_insn_reservation "saphira_afp_11_vx_vy" 11
115 (and (eq_attr "tune" "saphira")
116 (eq_attr "type" "neon_fp_div_d"))
117 "saphira_vx+saphira_vy")
118
119 (define_insn_reservation "saphira_afp_6_vx_vy_vx_vy" 6
120 (and (eq_attr "tune" "saphira")
121 (eq_attr "type" "neon_fp_div_s_q"))
122 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
123
124 (define_insn_reservation "saphira_afp_11_vx_vy_vx_vy" 11
125 (and (eq_attr "tune" "saphira")
126 (eq_attr "type" "neon_fp_div_d_q"))
127 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
128
129 (define_insn_reservation "saphira_afp_12_vx_vy" 12
130 (and (eq_attr "tune" "saphira")
131 (eq_attr "type" "neon_fp_sqrt_s"))
132 "saphira_vx+saphira_vy")
133
134 (define_insn_reservation "saphira_afp_22_vx_vy" 22
135 (and (eq_attr "tune" "saphira")
136 (eq_attr "type" "neon_fp_sqrt_d"))
137 "saphira_vx+saphira_vy")
138
139 (define_insn_reservation "saphira_afp_12_vx_vy_vx_vy" 12
140 (and (eq_attr "tune" "saphira")
141 (eq_attr "type" "neon_fp_sqrt_s_q"))
142 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
143
144 (define_insn_reservation "saphira_afp_22_vx_vy_vx_vy" 22
145 (and (eq_attr "tune" "saphira")
146 (eq_attr "type" "neon_fp_sqrt_d_q"))
147 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
148
149 ;; SIMD Integer Instructions
150
151 (define_insn_reservation "saphira_ai_1_vxvy" 1
152 (and (eq_attr "tune" "saphira")
153 (eq_attr "type" "neon_add,neon_reduc_add,neon_logic,neon_neg,neon_sub,neon_add_q,neon_reduc_add_q,neon_logic_q,neon_neg_q,neon_sub_q"))
154 "saphira_vxvy")
155
156 (define_insn_reservation "saphira_ai_2_vxvy" 2
157 (and (eq_attr "tune" "saphira")
158 (eq_attr "type" "neon_add_long,neon_sub_long,neon_add_halve,neon_sub_halve,neon_shift_imm,neon_shift_reg,neon_minmax,neon_abs,neon_compare,neon_compare_zero,neon_tst,neon_shift_imm_long,neon_reduc_add_long,neon_add_halve_q,neon_sub_halve_q,neon_shift_imm_q,neon_shift_reg_q,neon_minmax_q,neon_abs_q,neon_compare_q,neon_compare_zero_q,neon_tst_q"))
159 "saphira_vxvy")
160
161 (define_insn_reservation "saphira_ai_3_vxvy" 3
162 (and (eq_attr "tune" "saphira")
163 (eq_attr "type" "neon_shift_acc,neon_reduc_add_acc,neon_abd,neon_qadd,neon_qsub,neon_qabs,neon_qneg,neon_sat_shift_imm,neon_sat_shift_imm_narrow_q,neon_sat_shift_reg,neon_shift_acc_q,neon_reduc_add_acc_q,neon_abd_q,neon_abd_long,neon_qadd_q,neon_qsub_q,neon_qabs_q,neon_qneg_q,neon_sat_shift_imm_q,neon_sat_shift_reg_q,neon_add_halve_narrow_q,neon_sub_halve_narrow_q"))
164 "saphira_vxvy")
165
166 (define_insn_reservation "saphira_ai_4_vxvy" 4
167 (and (eq_attr "tune" "saphira")
168 (eq_attr "type" "neon_reduc_minmax,neon_reduc_minmax_q,neon_arith_acc,neon_arith_acc_q"))
169 "saphira_vxvy")
170
171 (define_insn_reservation "saphira_ai_4_vxvy_mul" 4
172 (and (eq_attr "tune" "saphira")
173 (eq_attr "type" "neon_mul_b,neon_mul_h,neon_mul_s,neon_mul_h_scalar,neon_mul_s_scalar,neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s,neon_sat_mul_h_scalar,neon_sat_mul_s_scalar,neon_mul_b_q,neon_mul_h_q,neon_mul_s_q,neon_mul_h_scalar_q,neon_mul_s_scalar_q,neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,neon_mul_d_long,neon_mul_h_scalar_long,neon_mul_s_scalar_long,neon_sat_mul_b_long,neon_sat_mul_h_long,neon_sat_mul_s_long,neon_sat_mul_h_scalar_q,neon_sat_mul_s_scalar_q,neon_sat_mul_h_scalar_long,neon_sat_mul_s_scalar_long"))
174 "saphira_vxvy")
175
176 (define_insn_reservation "saphira_ai_4_vxvy_mla" 4
177 (and (eq_attr "tune" "saphira")
178 (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,neon_mla_s_scalar,neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,neon_mla_h_scalar_q,neon_mla_s_scalar_q,neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,neon_mla_h_scalar_long,neon_mla_s_scalar_long,neon_sat_mla_b_long,neon_sat_mla_h_long,neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,neon_sat_mla_s_scalar_long"))
179 "saphira_vxvy")
180
181 (define_insn_reservation "saphira_2_ai_vxvy_vxvy" 2
182 (and (eq_attr "tune" "saphira")
183 (eq_attr "type" "neon_add_widen,neon_sub_widen"))
184 "(saphira_vxvy),(saphira_vxvy)")
185
186 ;; SIMD Load Instructions
187
188 (define_insn_reservation "saphira_ald_4_ld" 4
189 (and (eq_attr "tune" "saphira")
190 (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,neon_load1_all_lanes,neon_load2_one_lane"))
191 "saphira_ld")
192
193 (define_insn_reservation "saphira_ald_4_ld_none" 4
194 (and (eq_attr "tune" "saphira")
195 (eq_attr "type" "neon_load1_2reg,neon_load2_2reg,neon_load2_all_lanes"))
196 "saphira_ld")
197
198 (define_insn_reservation "saphira_ald_4_ld_ld" 4
199 (and (eq_attr "tune" "saphira")
200 (eq_attr "type" "neon_load1_2reg_q,neon_load2_2reg_q,neon_load2_all_lanes_q,neon_load3_one_lane,neon_load4_one_lane,neon_ldp,neon_ldp_q"))
201 "saphira_ld,saphira_ld")
202
203 (define_insn_reservation "saphira_ald_4_ld_ld_none" 4
204 (and (eq_attr "tune" "saphira")
205 (eq_attr "type" "neon_load1_3reg,neon_load3_3reg,neon_load3_all_lanes"))
206 "saphira_ld,saphira_ld")
207
208 (define_insn_reservation "saphira_ald_4_ld_ld_ld" 4
209 (and (eq_attr "tune" "saphira")
210 (eq_attr "type" "neon_load1_3reg_q,neon_load3_3reg_q,neon_load3_all_lanes_q"))
211 "saphira_ld,saphira_ld,saphira_ld")
212
213 (define_insn_reservation "saphira_ald_4_ld_ld_none_none" 4
214 (and (eq_attr "tune" "saphira")
215 (eq_attr "type" "neon_load1_4reg,neon_load4_4reg"))
216 "saphira_ld,saphira_ld")
217
218 (define_insn_reservation "saphira_ald_4_ld_ld_ld_ld" 4
219 (and (eq_attr "tune" "saphira")
220 (eq_attr "type" "neon_load1_4reg_q,neon_load4_4reg_q,neon_load4_all_lanes,neon_load4_all_lanes_q"))
221 "saphira_ld,saphira_ld,saphira_ld,saphira_ld")
222
223 ;; Arithmetic and Logical Instructions
224
225 (define_insn_reservation "saphira_alu_1_xyz" 1
226 (and (eq_attr "tune" "saphira")
227 (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
228 "saphira_xyzb")
229
230 ;; SIMD Miscellaneous Instructions
231
232 ;; No separate type for ins and dup. But this is correct for both.
233
234 (define_insn_reservation "saphira_am_3_gtov" 3
235 (and (eq_attr "tune" "saphira")
236 (eq_attr "type" "neon_from_gp"))
237 "saphira_gtov")
238
239 ;; No separate type for ins and dup. Assuming dup is more common. Ins is
240 ;; gtov+vxvy and latency of 4.
241
242 (define_insn_reservation "saphira_am_3_gtov_gtov" 3
243 (and (eq_attr "tune" "saphira")
244 (eq_attr "type" "neon_from_gp_q"))
245 "saphira_gtov,saphira_gtov")
246
247 ;; DUP does not use vector pipes in Q mode, only gtov+gtov.
248 (define_insn_reservation "saphira_am_1_gtov_gtov" 1
249 (and (eq_attr "tune" "saphira")
250 (eq_attr "type" "neon_dup_q"))
251 "saphira_gtov,saphira_gtov")
252
253 ;; neon_to_gp_q is used for 32-bit ARM instructions that move 64-bits of data
254 ;; so no use needed here.
255
256 (define_insn_reservation "saphira_am_3_vtog" 3
257 (and (eq_attr "tune" "saphira")
258 (eq_attr "type" "neon_to_gp"))
259 "saphira_vtog")
260
261 (define_insn_reservation "saphira_am_1_vxvy" 1
262 (and (eq_attr "tune" "saphira")
263 (eq_attr "type" "neon_bsl,neon_dup,neon_ext,neon_ins,neon_ins_q,neon_move,neon_rev,neon_tbl1,neon_permute,neon_shift_imm_narrow_q,neon_bsl_q,neon_ext_q,neon_move_q,neon_rev_q,neon_tbl1_q,neon_permute_q,neon_tbl1,neon_tbl1_q,neon_tbl2_q,neon_tbl2"))
264 "saphira_vxvy")
265
266 (define_insn_reservation "saphira_am_2_vxvy" 2
267 (and (eq_attr "tune" "saphira")
268 (eq_attr "type" "neon_cls,neon_cnt,neon_rbit,neon_cls_q,neon_cnt_q,neon_rbit_q,neon_tbl2,neon_tbl3_q,neon_tbl3"))
269 "saphira_vxvy")
270
271 (define_insn_reservation "saphira_am_3_vxvy" 3
272 (and (eq_attr "tune" "saphira")
273 (eq_attr "type" "neon_fp_recpe_s,neon_fp_recpe_d,neon_fp_rsqrte_s,neon_fp_rsqrte_d,neon_fp_recpx_s,neon_fp_recpx_d,neon_fp_recpe_s_q,neon_fp_recpe_d_q,neon_fp_rsqrte_s_q,neon_fp_rsqrte_d_q,neon_tbl4_q,neon_tbl4"))
274 "saphira_vxvy")
275
276 (define_insn_reservation "saphira_am_5_vxvy" 5
277 (and (eq_attr "tune" "saphira")
278 (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q"))
279 "saphira_vxvy")
280
281 (define_insn_reservation "saphira_am_6_vxvy" 6
282 (and (eq_attr "tune" "saphira")
283 (eq_attr "type" "neon_fp_recps_d,neon_fp_rsqrts_d,neon_fp_recps_d_q,neon_fp_rsqrts_d_q"))
284 "saphira_vxvy")
285
286 ;; SIMD Store Instructions
287
288 ;; ??? stp is neon_store1_2reg in aarch64.md, but neon_stp in aarch64-simd.md.
289 ;; Similarly with ldp.
290
291 (define_insn_reservation "saphira_ast_st_vsd" 0
292 (and (eq_attr "tune" "saphira")
293 (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,neon_store1_one_lane,neon_store1_one_lane_q,neon_store1_2reg,neon_store2_2reg,neon_store2_one_lane,neon_store2_one_lane_q,neon_stp"))
294 "saphira_st")
295
296 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd" 0
297 (and (eq_attr "tune" "saphira")
298 (eq_attr "type" "neon_store1_2reg_q,neon_store1_3reg,neon_store1_4reg,neon_store2_2reg_q,neon_store3_3reg,neon_store4_4reg,neon_store3_one_lane,neon_store3_one_lane_q,neon_store4_one_lane,neon_store4_one_lane_q,neon_stp_q"))
299 "(saphira_st),(saphira_st)")
300
301 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd_st_vsd" 0
302 (and (eq_attr "tune" "saphira")
303 (eq_attr "type" "neon_store1_3reg_q,neon_store3_3reg_q"))
304 "(saphira_st),(saphira_st),(saphira_st)")
305
306 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd_st_vsd_st_vsd" 0
307 (and (eq_attr "tune" "saphira")
308 (eq_attr "type" "neon_store1_4reg_q,neon_store4_4reg_q"))
309 "(saphira_st),(saphira_st),(saphira_st),(saphira_st)")
310
311 ;; Branch Instructions
312
313 (define_insn_reservation "saphira_branch_0_zb" 0
314 (and (eq_attr "tune" "saphira")
315 (eq_attr "type" "branch"))
316 "saphira_zb")
317
318 (define_insn_reservation "saphira_call_0_xyzb" 0
319 (and (eq_attr "tune" "saphira")
320 (eq_attr "type" "call"))
321 "saphira_xyzb")
322
323 ;; Cryptography Extensions
324
325 (define_insn_reservation "saphira_cry_1_vxvy" 1
326 (and (eq_attr "tune" "saphira")
327 (eq_attr "type" "crypto_sha1_fast"))
328 "saphira_vxvy")
329
330 (define_insn_reservation "saphira_cry_2_vxvy" 2
331 (and (eq_attr "tune" "saphira")
332 (eq_attr "type" "crypto_aesmc"))
333 "saphira_vxvy")
334
335 (define_insn_reservation "saphira_cry_2_vxvy_vxvy" 2
336 (and (eq_attr "tune" "saphira")
337 (eq_attr "type" "crypto_sha1_xor,crypto_sha256_fast,crypto_pmull,crypto_aese"))
338 "saphira_vxvy")
339
340 (define_insn_reservation "saphira_cry_4_vy_vx" 4
341 (and (eq_attr "tune" "saphira")
342 (eq_attr "type" "crypto_sha1_slow"))
343 "saphira_vxvy")
344
345 (define_insn_reservation "saphira_cry_5_vy_vx" 5
346 (and (eq_attr "tune" "saphira")
347 (eq_attr "type" "crypto_sha256_slow"))
348 "saphira_vxvy")
349
350 ;; FP Load Instructions
351
352 (define_insn_reservation "saphira_fld_4_ld" 4
353 (and (eq_attr "tune" "saphira")
354 (eq_attr "type" "f_loads,f_loadd"))
355 "saphira_ld")
356
357 ;; No separate FP store section, these are found in the SIMD store section.
358
359 (define_insn_reservation "saphira_fld_0_st_vsd" 0
360 (and (eq_attr "tune" "saphira")
361 (eq_attr "type" "f_stores,f_stored"))
362 "saphira_st")
363
364 ;; FP Data Processing Instructions
365
366 (define_insn_reservation "saphira_fpdt_0_vxvy" 0
367 (and (eq_attr "tune" "saphira")
368 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
369 "saphira_vxvy")
370
371 (define_insn_reservation "saphira_fpdt_5_vtog" 5
372 (and (eq_attr "tune" "saphira")
373 (eq_attr "type" "f_cvtf2i"))
374 "saphira_vtog")
375
376 (define_insn_reservation "saphira_fpdt_1_vxvy" 1
377 (and (eq_attr "tune" "saphira")
378 (eq_attr "type" "ffariths,ffarithd,fcsel"))
379 "saphira_vxvy")
380
381 (define_insn_reservation "saphira_fpdt_2_vxvy" 2
382 (and (eq_attr "tune" "saphira")
383 (eq_attr "type" "f_minmaxd,f_minmaxs,f_rintd,f_rints"))
384 "saphira_vxvy")
385
386 ;; Scalar FP ABD is handled same as vector FP ABD.
387
388 (define_insn_reservation "saphira_fpdt_3_vxvy" 3
389 (and (eq_attr "tune" "saphira")
390 (eq_attr "type" "faddd,fadds"))
391 "saphira_vxvy")
392
393 (define_insn_reservation "saphira_fpdt_4_vxvy" 4
394 (and (eq_attr "tune" "saphira")
395 (eq_attr "type" "f_cvt"))
396 "saphira_vxvy")
397
398 (define_insn_reservation "saphira_fpdt_5_vxvy_mul" 5
399 (and (eq_attr "tune" "saphira")
400 (eq_attr "type" "fmuls"))
401 "saphira_vxvy")
402
403 (define_insn_reservation "saphira_fpdt_5_vxvy_mla" 5
404 (and (eq_attr "tune" "saphira")
405 (eq_attr "type" "fmacs,ffmas"))
406 "saphira_vxvy")
407
408 (define_insn_reservation "saphira_fpdt_6_vxvy_mul" 6
409 (and (eq_attr "tune" "saphira")
410 (eq_attr "type" "fmuld"))
411 "saphira_vxvy")
412
413 (define_insn_reservation "saphira_fpdt_6_vxvy_mla" 6
414 (and (eq_attr "tune" "saphira")
415 (eq_attr "type" "fmacd,ffmad"))
416 "saphira_vxvy")
417
418 (define_insn_reservation "saphira_fpdt_6_vx_vy" 6
419 (and (eq_attr "tune" "saphira")
420 (eq_attr "type" "fdivs"))
421 "saphira_vx+saphira_vy")
422
423 (define_insn_reservation "saphira_fpdt_11_vx_vy" 11
424 (and (eq_attr "tune" "saphira")
425 (eq_attr "type" "fdivd"))
426 "saphira_vx+saphira_vy")
427
428 (define_insn_reservation "saphira_fpdt_12_vx_vy" 12
429 (and (eq_attr "tune" "saphira")
430 (eq_attr "type" "fsqrts"))
431 "saphira_vxvy")
432
433 (define_insn_reservation "saphira_fpdt_22_vx_vy" 22
434 (and (eq_attr "tune" "saphira")
435 (eq_attr "type" "fsqrtd"))
436 "saphira_vxvy")
437
438 ;; FP Miscellaneous Instructions
439
440 (define_insn_reservation "saphira_fpmsc_3_vtog" 3
441 (and (eq_attr "tune" "saphira")
442 (eq_attr "type" "f_mrc"))
443 "saphira_vtog")
444
445 (define_insn_reservation "saphira_fpmsc_3_gtov" 3
446 (and (eq_attr "tune" "saphira")
447 (eq_attr "type" "f_mcr"))
448 "saphira_gtov")
449
450 (define_insn_reservation "saphira_fpmsc_1_vxvy" 1
451 (and (eq_attr "tune" "saphira")
452 (eq_attr "type" "fmov,fconsts,fconstd"))
453 "saphira_vxvy")
454
455 ;; No separate type for float-to-fixed conversions. Same type as
456 ;; float-to-int conversions. They schedule the same though, so no problem.
457
458 (define_insn_reservation "saphira_fpmsc_6_gtov" 6
459 (and (eq_attr "tune" "saphira")
460 (eq_attr "type" "f_cvti2f"))
461 "saphira_gtov")
462
463 ;; Load Instructions
464
465 (define_insn_reservation "saphira_ld_3_ld" 3
466 (and (eq_attr "tune" "saphira")
467 (eq_attr "type" "load_4,load_8,load_16"))
468 "saphira_ld")
469
470 ;; Miscellaneous Data-Processing Instructions
471
472 (define_insn_reservation "saphira_misc_1_xyzb" 1
473 (and (eq_attr "tune" "saphira")
474 (eq_attr "type" "bfx,bfm,extend,rotate_imm,shift_imm"))
475 "saphira_xyzb")
476
477 (define_insn_reservation "saphira_misc_2_x" 2
478 (and (eq_attr "tune" "saphira")
479 (eq_attr "type" "crc"))
480 "saphira_x")
481
482 (define_insn_reservation "saphira_misc_2_xyzb" 2
483 (and (eq_attr "tune" "saphira")
484 (eq_attr "type" "clz,rbit,rev"))
485 "saphira_xyzb")
486
487 ;; Divide and Multiply Instructions
488
489 (define_insn_reservation "saphira_muldiv_4_x_mul" 4
490 (and (eq_attr "tune" "saphira")
491 (eq_attr "type" "mul"))
492 "saphira_x")
493
494 (define_insn_reservation "saphira_muldiv_4_x_mla" 4
495 (and (eq_attr "tune" "saphira")
496 (eq_attr "type" "mla,smlal,umlal"))
497 "saphira_x")
498
499 (define_insn_reservation "saphira_muldiv_5_x_mul" 5
500 (and (eq_attr "tune" "saphira")
501 (eq_attr "type" "smull,umull"))
502 "saphira_x")
503
504 (define_insn_reservation "saphira_md_11_x_zb" 11
505 (and (eq_attr "tune" "saphira")
506 (eq_attr "type" "sdiv,udiv"))
507 "saphira_x+saphira_zb")
508
509 ;; Move and Shift Instructions
510
511 (define_insn_reservation "saphira_mvs_1_xyzb" 1
512 (and (eq_attr "tune" "saphira")
513 (eq_attr "type" "mov_imm,shift_reg,adr"))
514 "saphira_xyzb")
515
516 ;; Other Instructions
517
518 ;; Block is for instruction scheduling blockage insns in RTL. There are no
519 ;; hardware instructions emitted for them, so don't use any resources.
520
521 (define_insn_reservation "saphira_other_0_nothing" 0
522 (and (eq_attr "tune" "saphira")
523 (eq_attr "type" "trap,block"))
524 "nothing")
525
526 (define_insn_reservation "saphira_other_2_ld" 2
527 (and (eq_attr "tune" "saphira")
528 (eq_attr "type" "mrs"))
529 "saphira_ld")
530
531 ;; Assume multiple instructions use all pipes.
532
533 (define_insn_reservation "saphira_extra" 1
534 (and (eq_attr "tune" "saphira")
535 (eq_attr "type" "multiple"))
536 "saphira_x+saphira_y+saphira_z+saphira_b+saphira_vx+saphira_vy+saphira_ld+saphira_st+saphira_gtov+saphira_vtog")
537
538 ;; Store Instructions
539
540 ;; No use of store_rel, store3, or store4 in aarch64.
541
542 (define_insn_reservation "saphira_st_0_st_sd" 0
543 (and (eq_attr "tune" "saphira")
544 (eq_attr "type" "store_4,store_8,store_16"))
545 "saphira_st")
546
547 ;; Muliply bypasses.
548
549 ;; 1 cycle latency (0 bubble) for an integer mul or mac feeding into a mac.
550
551 (define_bypass 1
552 "saphira_ai_4_vxvy_mul,saphira_ai_4_vxvy_mla,saphira_muldiv_4_x_mul,saphira_muldiv_4_x_mla,saphira_muldiv_5_x_mul"
553 "saphira_ai_4_vxvy_mla,saphira_muldiv_4_x_mla")
554
555 ;; 3 cycle latency (2 bubbles) for an FP mul or mac feeding into a mac.
556
557 (define_bypass 3
558 "saphira_afp_5_vxvy_mul,saphira_afp_5_vxvy_mla,saphira_afp_6_vxvy_mul,saphira_afp_6_vxvy_mla,saphira_fpdt_5_vxvy_mul,saphira_fpdt_5_vxvy_mla,saphira_fpdt_6_vxvy_mul,saphira_fpdt_6_vxvy_mla"
559 "saphira_afp_5_vxvy_mla,saphira_afp_6_vxvy_mla,saphira_fpdt_5_vxvy_mla,saphira_fpdt_6_vxvy_mla")
560