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1 ;; Saphira pipeline description
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2 ;; Copyright (C) 2017-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but
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12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 ;; General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "saphira")
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21
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22 ;; Complex int instructions (e.g. multiply and divide) execute in the X
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23 ;; pipeline. Simple int instructions execute in the X, Y, Z and B pipelines.
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24
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25 (define_cpu_unit "saphira_x" "saphira")
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26 (define_cpu_unit "saphira_y" "saphira")
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27
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28 ;; Branches execute in the Z or B pipeline or in one of the int pipelines depending
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29 ;; on how complex it is. Simple int insns (like movz) can also execute here.
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30
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31 (define_cpu_unit "saphira_z" "saphira")
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32 (define_cpu_unit "saphira_b" "saphira")
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33
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34 ;; Vector and FP insns execute in the VX and VY pipelines.
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35
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36 (define_automaton "saphira_vfp")
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37
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38 (define_cpu_unit "saphira_vx" "saphira_vfp")
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39 (define_cpu_unit "saphira_vy" "saphira_vfp")
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40
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41 ;; Loads execute in the LD pipeline.
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42 ;; Stores execute in the ST pipeline, for address, data, and
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43 ;; vector data.
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44
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45 (define_automaton "saphira_mem")
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46
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47 (define_cpu_unit "saphira_ld" "saphira_mem")
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48 (define_cpu_unit "saphira_st" "saphira_mem")
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49
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50 ;; The GTOV and VTOG pipelines are for general to vector reg moves, and vice
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51 ;; versa.
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52
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53 (define_cpu_unit "saphira_gtov" "saphira")
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54 (define_cpu_unit "saphira_vtog" "saphira")
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55
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56 ;; Common reservation combinations.
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57
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58 (define_reservation "saphira_vxvy" "saphira_vx|saphira_vy")
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59 (define_reservation "saphira_zb" "saphira_z|saphira_b")
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60 (define_reservation "saphira_xyzb" "saphira_x|saphira_y|saphira_z|saphira_b")
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61
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62 ;; SIMD Floating-Point Instructions
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63
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64 (define_insn_reservation "saphira_afp_1_vxvy" 1
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65 (and (eq_attr "tune" "saphira")
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66 (eq_attr "type" "neon_fp_neg_s,neon_fp_neg_d,neon_fp_abs_s,neon_fp_abs_d,neon_fp_neg_s_q,neon_fp_neg_d_q,neon_fp_abs_s_q,neon_fp_abs_d_q"))
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67 "saphira_vxvy")
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68
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69 (define_insn_reservation "saphira_afp_2_vxvy" 2
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70 (and (eq_attr "tune" "saphira")
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71 (eq_attr "type" "neon_fp_minmax_s,neon_fp_minmax_d,neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d,neon_fp_compare_s,neon_fp_compare_d,neon_fp_round_s,neon_fp_round_d,neon_fp_minmax_s_q,neon_fp_minmax_d_q,neon_fp_compare_s_q,neon_fp_compare_d_q,neon_fp_round_s_q,neon_fp_round_d_q"))
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72 "saphira_vxvy")
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73
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74 (define_insn_reservation "saphira_afp_3_vxvy" 3
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75 (and (eq_attr "tune" "saphira")
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76 (eq_attr "type" "neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q,neon_fp_abd_s,neon_fp_abd_d,neon_fp_addsub_s,neon_fp_addsub_d,neon_fp_reduc_add_s,neon_fp_reduc_add_d,neon_fp_abd_s_q,neon_fp_abd_d_q,neon_fp_addsub_s_q,neon_fp_addsub_d_q,neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q"))
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77 "saphira_vxvy")
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78
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79 (define_insn_reservation "saphira_afp_4_vxvy" 4
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80 (and (eq_attr "tune" "saphira")
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81 (eq_attr "type" "neon_fp_to_int_s,neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d,neon_fp_cvt_widen_h,neon_fp_cvt_widen_s,neon_fp_to_int_s_q,neon_fp_to_int_d_q,neon_int_to_fp_s_q,neon_int_to_fp_d_q"))
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82 "saphira_vxvy")
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83
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84 (define_insn_reservation "saphira_afp_5_vxvy_mul" 5
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85 (and (eq_attr "tune" "saphira")
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86 (eq_attr "type" "neon_fp_mul_s,neon_fp_mul_s_scalar,neon_fp_mul_s_q,neon_fp_mul_s_scalar_q"))
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87 "saphira_vxvy")
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88
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89 (define_insn_reservation "saphira_afp_5_vxvy_mla" 5
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90 (and (eq_attr "tune" "saphira")
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91 (eq_attr "type" "neon_fp_mla_s,neon_fp_mla_s_scalar,neon_fp_mla_s_q,neon_fp_mla_s_scalar_q"))
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92 "saphira_vxvy")
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93
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94 (define_insn_reservation "saphira_afp_6_vxvy_mul" 6
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95 (and (eq_attr "tune" "saphira")
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96 (eq_attr "type" "neon_fp_mul_d,neon_fp_mul_d_q,neon_fp_mul_d_scalar_q"))
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97 "saphira_vxvy")
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98
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99 (define_insn_reservation "saphira_afp_6_vxvy_mla" 6
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100 (and (eq_attr "tune" "saphira")
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101 (eq_attr "type" "neon_fp_mla_d,neon_fp_mla_d_q,neon_fp_mla_d_scalar_q"))
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102 "saphira_vxvy")
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103
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104 (define_insn_reservation "saphira_afp_4_vxvy_vxvy_vxvy" 4
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105 (and (eq_attr "tune" "saphira")
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106 (eq_attr "type" "neon_fp_cvt_narrow_s_q,neon_fp_cvt_narrow_d_q"))
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107 "saphira_vxvy+saphira_vxvy,saphira_vxvy")
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108
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109 (define_insn_reservation "saphira_afp_6_vx_vy" 6
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110 (and (eq_attr "tune" "saphira")
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111 (eq_attr "type" "neon_fp_div_s"))
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112 "saphira_vx+saphira_vy")
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113
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114 (define_insn_reservation "saphira_afp_11_vx_vy" 11
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115 (and (eq_attr "tune" "saphira")
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116 (eq_attr "type" "neon_fp_div_d"))
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117 "saphira_vx+saphira_vy")
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118
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119 (define_insn_reservation "saphira_afp_6_vx_vy_vx_vy" 6
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120 (and (eq_attr "tune" "saphira")
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121 (eq_attr "type" "neon_fp_div_s_q"))
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122 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
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123
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124 (define_insn_reservation "saphira_afp_11_vx_vy_vx_vy" 11
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125 (and (eq_attr "tune" "saphira")
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126 (eq_attr "type" "neon_fp_div_d_q"))
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127 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
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128
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129 (define_insn_reservation "saphira_afp_12_vx_vy" 12
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130 (and (eq_attr "tune" "saphira")
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131 (eq_attr "type" "neon_fp_sqrt_s"))
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132 "saphira_vx+saphira_vy")
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133
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134 (define_insn_reservation "saphira_afp_22_vx_vy" 22
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135 (and (eq_attr "tune" "saphira")
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136 (eq_attr "type" "neon_fp_sqrt_d"))
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137 "saphira_vx+saphira_vy")
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138
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139 (define_insn_reservation "saphira_afp_12_vx_vy_vx_vy" 12
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140 (and (eq_attr "tune" "saphira")
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141 (eq_attr "type" "neon_fp_sqrt_s_q"))
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142 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
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143
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144 (define_insn_reservation "saphira_afp_22_vx_vy_vx_vy" 22
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145 (and (eq_attr "tune" "saphira")
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146 (eq_attr "type" "neon_fp_sqrt_d_q"))
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147 "(saphira_vx+saphira_vy),(saphira_vx+saphira_vy)")
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148
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149 ;; SIMD Integer Instructions
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150
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151 (define_insn_reservation "saphira_ai_1_vxvy" 1
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152 (and (eq_attr "tune" "saphira")
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153 (eq_attr "type" "neon_add,neon_reduc_add,neon_logic,neon_neg,neon_sub,neon_add_q,neon_reduc_add_q,neon_logic_q,neon_neg_q,neon_sub_q"))
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154 "saphira_vxvy")
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155
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156 (define_insn_reservation "saphira_ai_2_vxvy" 2
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157 (and (eq_attr "tune" "saphira")
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158 (eq_attr "type" "neon_add_long,neon_sub_long,neon_add_halve,neon_sub_halve,neon_shift_imm,neon_shift_reg,neon_minmax,neon_abs,neon_compare,neon_compare_zero,neon_tst,neon_shift_imm_long,neon_reduc_add_long,neon_add_halve_q,neon_sub_halve_q,neon_shift_imm_q,neon_shift_reg_q,neon_minmax_q,neon_abs_q,neon_compare_q,neon_compare_zero_q,neon_tst_q"))
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159 "saphira_vxvy")
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160
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161 (define_insn_reservation "saphira_ai_3_vxvy" 3
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162 (and (eq_attr "tune" "saphira")
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163 (eq_attr "type" "neon_shift_acc,neon_reduc_add_acc,neon_abd,neon_qadd,neon_qsub,neon_qabs,neon_qneg,neon_sat_shift_imm,neon_sat_shift_imm_narrow_q,neon_sat_shift_reg,neon_shift_acc_q,neon_reduc_add_acc_q,neon_abd_q,neon_abd_long,neon_qadd_q,neon_qsub_q,neon_qabs_q,neon_qneg_q,neon_sat_shift_imm_q,neon_sat_shift_reg_q,neon_add_halve_narrow_q,neon_sub_halve_narrow_q"))
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164 "saphira_vxvy")
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165
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166 (define_insn_reservation "saphira_ai_4_vxvy" 4
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167 (and (eq_attr "tune" "saphira")
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168 (eq_attr "type" "neon_reduc_minmax,neon_reduc_minmax_q,neon_arith_acc,neon_arith_acc_q"))
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169 "saphira_vxvy")
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170
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171 (define_insn_reservation "saphira_ai_4_vxvy_mul" 4
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172 (and (eq_attr "tune" "saphira")
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173 (eq_attr "type" "neon_mul_b,neon_mul_h,neon_mul_s,neon_mul_h_scalar,neon_mul_s_scalar,neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s,neon_sat_mul_h_scalar,neon_sat_mul_s_scalar,neon_mul_b_q,neon_mul_h_q,neon_mul_s_q,neon_mul_h_scalar_q,neon_mul_s_scalar_q,neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,neon_mul_d_long,neon_mul_h_scalar_long,neon_mul_s_scalar_long,neon_sat_mul_b_long,neon_sat_mul_h_long,neon_sat_mul_s_long,neon_sat_mul_h_scalar_q,neon_sat_mul_s_scalar_q,neon_sat_mul_h_scalar_long,neon_sat_mul_s_scalar_long"))
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174 "saphira_vxvy")
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175
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176 (define_insn_reservation "saphira_ai_4_vxvy_mla" 4
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177 (and (eq_attr "tune" "saphira")
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178 (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,neon_mla_s_scalar,neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,neon_mla_h_scalar_q,neon_mla_s_scalar_q,neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,neon_mla_h_scalar_long,neon_mla_s_scalar_long,neon_sat_mla_b_long,neon_sat_mla_h_long,neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,neon_sat_mla_s_scalar_long"))
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179 "saphira_vxvy")
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180
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181 (define_insn_reservation "saphira_2_ai_vxvy_vxvy" 2
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182 (and (eq_attr "tune" "saphira")
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183 (eq_attr "type" "neon_add_widen,neon_sub_widen"))
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184 "(saphira_vxvy),(saphira_vxvy)")
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185
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186 ;; SIMD Load Instructions
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187
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188 (define_insn_reservation "saphira_ald_4_ld" 4
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189 (and (eq_attr "tune" "saphira")
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190 (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,neon_load1_all_lanes,neon_load2_one_lane"))
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191 "saphira_ld")
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192
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193 (define_insn_reservation "saphira_ald_4_ld_none" 4
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194 (and (eq_attr "tune" "saphira")
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195 (eq_attr "type" "neon_load1_2reg,neon_load2_2reg,neon_load2_all_lanes"))
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196 "saphira_ld")
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197
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198 (define_insn_reservation "saphira_ald_4_ld_ld" 4
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199 (and (eq_attr "tune" "saphira")
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200 (eq_attr "type" "neon_load1_2reg_q,neon_load2_2reg_q,neon_load2_all_lanes_q,neon_load3_one_lane,neon_load4_one_lane,neon_ldp,neon_ldp_q"))
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201 "saphira_ld,saphira_ld")
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202
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203 (define_insn_reservation "saphira_ald_4_ld_ld_none" 4
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204 (and (eq_attr "tune" "saphira")
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205 (eq_attr "type" "neon_load1_3reg,neon_load3_3reg,neon_load3_all_lanes"))
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206 "saphira_ld,saphira_ld")
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207
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208 (define_insn_reservation "saphira_ald_4_ld_ld_ld" 4
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209 (and (eq_attr "tune" "saphira")
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210 (eq_attr "type" "neon_load1_3reg_q,neon_load3_3reg_q,neon_load3_all_lanes_q"))
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211 "saphira_ld,saphira_ld,saphira_ld")
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212
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213 (define_insn_reservation "saphira_ald_4_ld_ld_none_none" 4
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214 (and (eq_attr "tune" "saphira")
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215 (eq_attr "type" "neon_load1_4reg,neon_load4_4reg"))
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216 "saphira_ld,saphira_ld")
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217
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218 (define_insn_reservation "saphira_ald_4_ld_ld_ld_ld" 4
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219 (and (eq_attr "tune" "saphira")
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220 (eq_attr "type" "neon_load1_4reg_q,neon_load4_4reg_q,neon_load4_all_lanes,neon_load4_all_lanes_q"))
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221 "saphira_ld,saphira_ld,saphira_ld,saphira_ld")
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222
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223 ;; Arithmetic and Logical Instructions
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224
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225 (define_insn_reservation "saphira_alu_1_xyz" 1
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226 (and (eq_attr "tune" "saphira")
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227 (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
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228 "saphira_xyzb")
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229
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230 ;; SIMD Miscellaneous Instructions
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231
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232 ;; No separate type for ins and dup. But this is correct for both.
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233
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234 (define_insn_reservation "saphira_am_3_gtov" 3
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235 (and (eq_attr "tune" "saphira")
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236 (eq_attr "type" "neon_from_gp"))
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237 "saphira_gtov")
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238
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239 ;; No separate type for ins and dup. Assuming dup is more common. Ins is
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240 ;; gtov+vxvy and latency of 4.
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241
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242 (define_insn_reservation "saphira_am_3_gtov_gtov" 3
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243 (and (eq_attr "tune" "saphira")
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244 (eq_attr "type" "neon_from_gp_q"))
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245 "saphira_gtov,saphira_gtov")
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246
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247 ;; DUP does not use vector pipes in Q mode, only gtov+gtov.
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248 (define_insn_reservation "saphira_am_1_gtov_gtov" 1
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249 (and (eq_attr "tune" "saphira")
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250 (eq_attr "type" "neon_dup_q"))
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251 "saphira_gtov,saphira_gtov")
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252
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253 ;; neon_to_gp_q is used for 32-bit ARM instructions that move 64-bits of data
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254 ;; so no use needed here.
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255
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256 (define_insn_reservation "saphira_am_3_vtog" 3
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257 (and (eq_attr "tune" "saphira")
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258 (eq_attr "type" "neon_to_gp"))
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259 "saphira_vtog")
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260
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261 (define_insn_reservation "saphira_am_1_vxvy" 1
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262 (and (eq_attr "tune" "saphira")
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263 (eq_attr "type" "neon_bsl,neon_dup,neon_ext,neon_ins,neon_ins_q,neon_move,neon_rev,neon_tbl1,neon_permute,neon_shift_imm_narrow_q,neon_bsl_q,neon_ext_q,neon_move_q,neon_rev_q,neon_tbl1_q,neon_permute_q,neon_tbl1,neon_tbl1_q,neon_tbl2_q,neon_tbl2"))
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264 "saphira_vxvy")
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265
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266 (define_insn_reservation "saphira_am_2_vxvy" 2
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267 (and (eq_attr "tune" "saphira")
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268 (eq_attr "type" "neon_cls,neon_cnt,neon_rbit,neon_cls_q,neon_cnt_q,neon_rbit_q,neon_tbl2,neon_tbl3_q,neon_tbl3"))
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269 "saphira_vxvy")
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270
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271 (define_insn_reservation "saphira_am_3_vxvy" 3
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272 (and (eq_attr "tune" "saphira")
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273 (eq_attr "type" "neon_fp_recpe_s,neon_fp_recpe_d,neon_fp_rsqrte_s,neon_fp_rsqrte_d,neon_fp_recpx_s,neon_fp_recpx_d,neon_fp_recpe_s_q,neon_fp_recpe_d_q,neon_fp_rsqrte_s_q,neon_fp_rsqrte_d_q,neon_tbl4_q,neon_tbl4"))
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274 "saphira_vxvy")
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275
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276 (define_insn_reservation "saphira_am_5_vxvy" 5
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277 (and (eq_attr "tune" "saphira")
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278 (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q"))
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279 "saphira_vxvy")
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280
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281 (define_insn_reservation "saphira_am_6_vxvy" 6
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282 (and (eq_attr "tune" "saphira")
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283 (eq_attr "type" "neon_fp_recps_d,neon_fp_rsqrts_d,neon_fp_recps_d_q,neon_fp_rsqrts_d_q"))
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284 "saphira_vxvy")
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285
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286 ;; SIMD Store Instructions
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287
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288 ;; ??? stp is neon_store1_2reg in aarch64.md, but neon_stp in aarch64-simd.md.
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289 ;; Similarly with ldp.
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290
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291 (define_insn_reservation "saphira_ast_st_vsd" 0
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292 (and (eq_attr "tune" "saphira")
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293 (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,neon_store1_one_lane,neon_store1_one_lane_q,neon_store1_2reg,neon_store2_2reg,neon_store2_one_lane,neon_store2_one_lane_q,neon_stp"))
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294 "saphira_st")
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295
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296 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd" 0
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297 (and (eq_attr "tune" "saphira")
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298 (eq_attr "type" "neon_store1_2reg_q,neon_store1_3reg,neon_store1_4reg,neon_store2_2reg_q,neon_store3_3reg,neon_store4_4reg,neon_store3_one_lane,neon_store3_one_lane_q,neon_store4_one_lane,neon_store4_one_lane_q,neon_stp_q"))
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299 "(saphira_st),(saphira_st)")
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300
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301 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd_st_vsd" 0
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302 (and (eq_attr "tune" "saphira")
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303 (eq_attr "type" "neon_store1_3reg_q,neon_store3_3reg_q"))
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304 "(saphira_st),(saphira_st),(saphira_st)")
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305
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306 (define_insn_reservation "saphira_as_0_st_vsd_st_vsd_st_vsd_st_vsd" 0
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307 (and (eq_attr "tune" "saphira")
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308 (eq_attr "type" "neon_store1_4reg_q,neon_store4_4reg_q"))
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309 "(saphira_st),(saphira_st),(saphira_st),(saphira_st)")
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310
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311 ;; Branch Instructions
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312
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313 (define_insn_reservation "saphira_branch_0_zb" 0
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314 (and (eq_attr "tune" "saphira")
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315 (eq_attr "type" "branch"))
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316 "saphira_zb")
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317
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318 (define_insn_reservation "saphira_call_0_xyzb" 0
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319 (and (eq_attr "tune" "saphira")
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320 (eq_attr "type" "call"))
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321 "saphira_xyzb")
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322
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323 ;; Cryptography Extensions
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324
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325 (define_insn_reservation "saphira_cry_1_vxvy" 1
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326 (and (eq_attr "tune" "saphira")
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327 (eq_attr "type" "crypto_sha1_fast"))
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328 "saphira_vxvy")
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329
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330 (define_insn_reservation "saphira_cry_2_vxvy" 2
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331 (and (eq_attr "tune" "saphira")
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332 (eq_attr "type" "crypto_aesmc"))
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333 "saphira_vxvy")
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334
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335 (define_insn_reservation "saphira_cry_2_vxvy_vxvy" 2
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336 (and (eq_attr "tune" "saphira")
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337 (eq_attr "type" "crypto_sha1_xor,crypto_sha256_fast,crypto_pmull,crypto_aese"))
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338 "saphira_vxvy")
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339
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340 (define_insn_reservation "saphira_cry_4_vy_vx" 4
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341 (and (eq_attr "tune" "saphira")
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342 (eq_attr "type" "crypto_sha1_slow"))
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343 "saphira_vxvy")
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344
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345 (define_insn_reservation "saphira_cry_5_vy_vx" 5
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346 (and (eq_attr "tune" "saphira")
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347 (eq_attr "type" "crypto_sha256_slow"))
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348 "saphira_vxvy")
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349
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350 ;; FP Load Instructions
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351
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352 (define_insn_reservation "saphira_fld_4_ld" 4
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353 (and (eq_attr "tune" "saphira")
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354 (eq_attr "type" "f_loads,f_loadd"))
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355 "saphira_ld")
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356
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357 ;; No separate FP store section, these are found in the SIMD store section.
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358
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359 (define_insn_reservation "saphira_fld_0_st_vsd" 0
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360 (and (eq_attr "tune" "saphira")
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361 (eq_attr "type" "f_stores,f_stored"))
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362 "saphira_st")
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363
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364 ;; FP Data Processing Instructions
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365
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366 (define_insn_reservation "saphira_fpdt_0_vxvy" 0
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367 (and (eq_attr "tune" "saphira")
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368 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
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369 "saphira_vxvy")
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370
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371 (define_insn_reservation "saphira_fpdt_5_vtog" 5
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372 (and (eq_attr "tune" "saphira")
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373 (eq_attr "type" "f_cvtf2i"))
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374 "saphira_vtog")
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375
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376 (define_insn_reservation "saphira_fpdt_1_vxvy" 1
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377 (and (eq_attr "tune" "saphira")
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378 (eq_attr "type" "ffariths,ffarithd,fcsel"))
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379 "saphira_vxvy")
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380
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381 (define_insn_reservation "saphira_fpdt_2_vxvy" 2
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382 (and (eq_attr "tune" "saphira")
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383 (eq_attr "type" "f_minmaxd,f_minmaxs,f_rintd,f_rints"))
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384 "saphira_vxvy")
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385
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386 ;; Scalar FP ABD is handled same as vector FP ABD.
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387
|
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388 (define_insn_reservation "saphira_fpdt_3_vxvy" 3
|
|
389 (and (eq_attr "tune" "saphira")
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390 (eq_attr "type" "faddd,fadds"))
|
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391 "saphira_vxvy")
|
|
392
|
|
393 (define_insn_reservation "saphira_fpdt_4_vxvy" 4
|
|
394 (and (eq_attr "tune" "saphira")
|
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395 (eq_attr "type" "f_cvt"))
|
|
396 "saphira_vxvy")
|
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397
|
|
398 (define_insn_reservation "saphira_fpdt_5_vxvy_mul" 5
|
|
399 (and (eq_attr "tune" "saphira")
|
|
400 (eq_attr "type" "fmuls"))
|
|
401 "saphira_vxvy")
|
|
402
|
|
403 (define_insn_reservation "saphira_fpdt_5_vxvy_mla" 5
|
|
404 (and (eq_attr "tune" "saphira")
|
|
405 (eq_attr "type" "fmacs,ffmas"))
|
|
406 "saphira_vxvy")
|
|
407
|
|
408 (define_insn_reservation "saphira_fpdt_6_vxvy_mul" 6
|
|
409 (and (eq_attr "tune" "saphira")
|
|
410 (eq_attr "type" "fmuld"))
|
|
411 "saphira_vxvy")
|
|
412
|
|
413 (define_insn_reservation "saphira_fpdt_6_vxvy_mla" 6
|
|
414 (and (eq_attr "tune" "saphira")
|
|
415 (eq_attr "type" "fmacd,ffmad"))
|
|
416 "saphira_vxvy")
|
|
417
|
|
418 (define_insn_reservation "saphira_fpdt_6_vx_vy" 6
|
|
419 (and (eq_attr "tune" "saphira")
|
|
420 (eq_attr "type" "fdivs"))
|
|
421 "saphira_vx+saphira_vy")
|
|
422
|
|
423 (define_insn_reservation "saphira_fpdt_11_vx_vy" 11
|
|
424 (and (eq_attr "tune" "saphira")
|
|
425 (eq_attr "type" "fdivd"))
|
|
426 "saphira_vx+saphira_vy")
|
|
427
|
|
428 (define_insn_reservation "saphira_fpdt_12_vx_vy" 12
|
|
429 (and (eq_attr "tune" "saphira")
|
|
430 (eq_attr "type" "fsqrts"))
|
|
431 "saphira_vxvy")
|
|
432
|
|
433 (define_insn_reservation "saphira_fpdt_22_vx_vy" 22
|
|
434 (and (eq_attr "tune" "saphira")
|
|
435 (eq_attr "type" "fsqrtd"))
|
|
436 "saphira_vxvy")
|
|
437
|
|
438 ;; FP Miscellaneous Instructions
|
|
439
|
|
440 (define_insn_reservation "saphira_fpmsc_3_vtog" 3
|
|
441 (and (eq_attr "tune" "saphira")
|
|
442 (eq_attr "type" "f_mrc"))
|
|
443 "saphira_vtog")
|
|
444
|
|
445 (define_insn_reservation "saphira_fpmsc_3_gtov" 3
|
|
446 (and (eq_attr "tune" "saphira")
|
|
447 (eq_attr "type" "f_mcr"))
|
|
448 "saphira_gtov")
|
|
449
|
|
450 (define_insn_reservation "saphira_fpmsc_1_vxvy" 1
|
|
451 (and (eq_attr "tune" "saphira")
|
|
452 (eq_attr "type" "fmov,fconsts,fconstd"))
|
|
453 "saphira_vxvy")
|
|
454
|
|
455 ;; No separate type for float-to-fixed conversions. Same type as
|
|
456 ;; float-to-int conversions. They schedule the same though, so no problem.
|
|
457
|
|
458 (define_insn_reservation "saphira_fpmsc_6_gtov" 6
|
|
459 (and (eq_attr "tune" "saphira")
|
|
460 (eq_attr "type" "f_cvti2f"))
|
|
461 "saphira_gtov")
|
|
462
|
|
463 ;; Load Instructions
|
|
464
|
|
465 (define_insn_reservation "saphira_ld_3_ld" 3
|
|
466 (and (eq_attr "tune" "saphira")
|
|
467 (eq_attr "type" "load_4,load_8,load_16"))
|
|
468 "saphira_ld")
|
|
469
|
|
470 ;; Miscellaneous Data-Processing Instructions
|
|
471
|
|
472 (define_insn_reservation "saphira_misc_1_xyzb" 1
|
|
473 (and (eq_attr "tune" "saphira")
|
|
474 (eq_attr "type" "bfx,bfm,extend,rotate_imm,shift_imm"))
|
|
475 "saphira_xyzb")
|
|
476
|
|
477 (define_insn_reservation "saphira_misc_2_x" 2
|
|
478 (and (eq_attr "tune" "saphira")
|
|
479 (eq_attr "type" "crc"))
|
|
480 "saphira_x")
|
|
481
|
|
482 (define_insn_reservation "saphira_misc_2_xyzb" 2
|
|
483 (and (eq_attr "tune" "saphira")
|
|
484 (eq_attr "type" "clz,rbit,rev"))
|
|
485 "saphira_xyzb")
|
|
486
|
|
487 ;; Divide and Multiply Instructions
|
|
488
|
|
489 (define_insn_reservation "saphira_muldiv_4_x_mul" 4
|
|
490 (and (eq_attr "tune" "saphira")
|
|
491 (eq_attr "type" "mul"))
|
|
492 "saphira_x")
|
|
493
|
|
494 (define_insn_reservation "saphira_muldiv_4_x_mla" 4
|
|
495 (and (eq_attr "tune" "saphira")
|
|
496 (eq_attr "type" "mla,smlal,umlal"))
|
|
497 "saphira_x")
|
|
498
|
|
499 (define_insn_reservation "saphira_muldiv_5_x_mul" 5
|
|
500 (and (eq_attr "tune" "saphira")
|
|
501 (eq_attr "type" "smull,umull"))
|
|
502 "saphira_x")
|
|
503
|
|
504 (define_insn_reservation "saphira_md_11_x_zb" 11
|
|
505 (and (eq_attr "tune" "saphira")
|
|
506 (eq_attr "type" "sdiv,udiv"))
|
|
507 "saphira_x+saphira_zb")
|
|
508
|
|
509 ;; Move and Shift Instructions
|
|
510
|
|
511 (define_insn_reservation "saphira_mvs_1_xyzb" 1
|
|
512 (and (eq_attr "tune" "saphira")
|
|
513 (eq_attr "type" "mov_imm,shift_reg,adr"))
|
|
514 "saphira_xyzb")
|
|
515
|
|
516 ;; Other Instructions
|
|
517
|
|
518 ;; Block is for instruction scheduling blockage insns in RTL. There are no
|
|
519 ;; hardware instructions emitted for them, so don't use any resources.
|
|
520
|
|
521 (define_insn_reservation "saphira_other_0_nothing" 0
|
|
522 (and (eq_attr "tune" "saphira")
|
|
523 (eq_attr "type" "trap,block"))
|
|
524 "nothing")
|
|
525
|
|
526 (define_insn_reservation "saphira_other_2_ld" 2
|
|
527 (and (eq_attr "tune" "saphira")
|
|
528 (eq_attr "type" "mrs"))
|
|
529 "saphira_ld")
|
|
530
|
|
531 ;; Assume multiple instructions use all pipes.
|
|
532
|
|
533 (define_insn_reservation "saphira_extra" 1
|
|
534 (and (eq_attr "tune" "saphira")
|
|
535 (eq_attr "type" "multiple"))
|
|
536 "saphira_x+saphira_y+saphira_z+saphira_b+saphira_vx+saphira_vy+saphira_ld+saphira_st+saphira_gtov+saphira_vtog")
|
|
537
|
|
538 ;; Store Instructions
|
|
539
|
|
540 ;; No use of store_rel, store3, or store4 in aarch64.
|
|
541
|
|
542 (define_insn_reservation "saphira_st_0_st_sd" 0
|
|
543 (and (eq_attr "tune" "saphira")
|
|
544 (eq_attr "type" "store_4,store_8,store_16"))
|
|
545 "saphira_st")
|
|
546
|
|
547 ;; Muliply bypasses.
|
|
548
|
|
549 ;; 1 cycle latency (0 bubble) for an integer mul or mac feeding into a mac.
|
|
550
|
|
551 (define_bypass 1
|
|
552 "saphira_ai_4_vxvy_mul,saphira_ai_4_vxvy_mla,saphira_muldiv_4_x_mul,saphira_muldiv_4_x_mla,saphira_muldiv_5_x_mul"
|
|
553 "saphira_ai_4_vxvy_mla,saphira_muldiv_4_x_mla")
|
|
554
|
|
555 ;; 3 cycle latency (2 bubbles) for an FP mul or mac feeding into a mac.
|
|
556
|
|
557 (define_bypass 3
|
|
558 "saphira_afp_5_vxvy_mul,saphira_afp_5_vxvy_mla,saphira_afp_6_vxvy_mul,saphira_afp_6_vxvy_mla,saphira_fpdt_5_vxvy_mul,saphira_fpdt_5_vxvy_mla,saphira_fpdt_6_vxvy_mul,saphira_fpdt_6_vxvy_mla"
|
|
559 "saphira_afp_5_vxvy_mla,saphira_afp_6_vxvy_mla,saphira_fpdt_5_vxvy_mla,saphira_fpdt_6_vxvy_mla")
|
|
560
|