Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/arm/arm-fixed.md @ 145:1830386684a0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
equal deleted inserted replaced
131:84e7813d76e9 145:1830386684a0
1 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc. 1 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify it 5 ;; GCC is free software; you can redistribute it and/or modify it
6 ;; under the terms of the GNU General Public License as published 6 ;; under the terms of the GNU General Public License as published
26 "add%?\\t%0, %1, %2" 26 "add%?\\t%0, %1, %2"
27 [(set_attr "predicable" "yes") 27 [(set_attr "predicable" "yes")
28 (set_attr "predicable_short_it" "yes,no") 28 (set_attr "predicable_short_it" "yes,no")
29 (set_attr "type" "alu_sreg")]) 29 (set_attr "type" "alu_sreg")])
30 30
31 (define_insn "add<mode>3" 31 (define_expand "add<mode>3"
32 [(set (match_operand:ADDSUB 0 "s_register_operand")
33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand")
34 (match_operand:ADDSUB 2 "s_register_operand")))]
35 "TARGET_INT_SIMD"
36 {
37 if (ARM_GE_BITS_READ)
38 FAIL;
39 }
40 )
41
42 (define_insn "*arm_add<mode>3"
32 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") 43 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 44 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
34 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 45 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
35 "TARGET_INT_SIMD" 46 "TARGET_INT_SIMD && !ARM_GE_BITS_READ"
36 "sadd<qaddsub_suf>%?\\t%0, %1, %2" 47 "sadd<qaddsub_suf>%?\\t%0, %1, %2"
37 [(set_attr "predicable" "yes") 48 [(set_attr "predicable" "yes")
38 (set_attr "type" "alu_dsp_reg")]) 49 (set_attr "type" "alu_dsp_reg")])
39 50
40 (define_insn "usadd<mode>3" 51 (define_insn "usadd<mode>3"
44 "TARGET_INT_SIMD" 55 "TARGET_INT_SIMD"
45 "uqadd<qaddsub_suf>%?\\t%0, %1, %2" 56 "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
46 [(set_attr "predicable" "yes") 57 [(set_attr "predicable" "yes")
47 (set_attr "type" "alu_dsp_reg")]) 58 (set_attr "type" "alu_dsp_reg")])
48 59
49 (define_insn "ssadd<mode>3" 60 (define_expand "ssadd<mode>3"
61 [(set (match_operand:QADDSUB 0 "s_register_operand")
62 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand")
63 (match_operand:QADDSUB 2 "s_register_operand")))]
64 "TARGET_INT_SIMD"
65 {
66 if (<qaddsub_clob_q>)
67 FAIL;
68 }
69 )
70
71 (define_insn "*arm_ssadd<mode>3"
50 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 72 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
51 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 73 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
52 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 74 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
53 "TARGET_INT_SIMD" 75 "TARGET_INT_SIMD && !<qaddsub_clob_q>"
54 "qadd<qaddsub_suf>%?\\t%0, %1, %2" 76 "qadd<qaddsub_suf>%?\\t%0, %1, %2"
55 [(set_attr "predicable" "yes") 77 [(set_attr "predicable" "yes")
56 (set_attr "type" "alu_dsp_reg")]) 78 (set_attr "type" "alu_dsp_reg")])
57 79
58 (define_insn "sub<mode>3" 80 (define_insn "sub<mode>3"
63 "sub%?\\t%0, %1, %2" 85 "sub%?\\t%0, %1, %2"
64 [(set_attr "predicable" "yes") 86 [(set_attr "predicable" "yes")
65 (set_attr "predicable_short_it" "yes,no") 87 (set_attr "predicable_short_it" "yes,no")
66 (set_attr "type" "alu_sreg")]) 88 (set_attr "type" "alu_sreg")])
67 89
68 (define_insn "sub<mode>3" 90 (define_expand "sub<mode>3"
91 [(set (match_operand:ADDSUB 0 "s_register_operand")
92 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand")
93 (match_operand:ADDSUB 2 "s_register_operand")))]
94 "TARGET_INT_SIMD"
95 {
96 if (ARM_GE_BITS_READ)
97 FAIL;
98 }
99 )
100
101 (define_insn "*arm_sub<mode>3"
69 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") 102 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
70 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 103 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
71 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 104 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
72 "TARGET_INT_SIMD" 105 "TARGET_INT_SIMD && !ARM_GE_BITS_READ"
73 "ssub<qaddsub_suf>%?\\t%0, %1, %2" 106 "ssub<qaddsub_suf>%?\\t%0, %1, %2"
74 [(set_attr "predicable" "yes") 107 [(set_attr "predicable" "yes")
75 (set_attr "type" "alu_dsp_reg")]) 108 (set_attr "type" "alu_dsp_reg")])
76 109
77 (define_insn "ussub<mode>3" 110 (define_insn "ussub<mode>3"
82 "TARGET_INT_SIMD" 115 "TARGET_INT_SIMD"
83 "uqsub<qaddsub_suf>%?\\t%0, %1, %2" 116 "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
84 [(set_attr "predicable" "yes") 117 [(set_attr "predicable" "yes")
85 (set_attr "type" "alu_dsp_reg")]) 118 (set_attr "type" "alu_dsp_reg")])
86 119
87 (define_insn "sssub<mode>3" 120 (define_expand "sssub<mode>3"
121 [(set (match_operand:QADDSUB 0 "s_register_operand")
122 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand")
123 (match_operand:QADDSUB 2 "s_register_operand")))]
124 "TARGET_INT_SIMD"
125 {
126 if (<qaddsub_clob_q>)
127 FAIL;
128 }
129 )
130
131 (define_insn "*arm_sssub<mode>3"
88 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 132 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
89 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 133 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
90 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 134 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
91 "TARGET_INT_SIMD" 135 "TARGET_INT_SIMD && !<qaddsub_clob_q>"
92 "qsub<qaddsub_suf>%?\\t%0, %1, %2" 136 "qsub<qaddsub_suf>%?\\t%0, %1, %2"
93 [(set_attr "predicable" "yes") 137 [(set_attr "predicable" "yes")
94 (set_attr "type" "alu_dsp_reg")]) 138 (set_attr "type" "alu_dsp_reg")])
95 139
96 ;; Fractional multiplies. 140 ;; Fractional multiplies.
97 141
98 ; Note: none of these do any rounding. 142 ; Note: none of these do any rounding.
99 143
100 (define_expand "mulqq3" 144 (define_expand "mulqq3"
101 [(set (match_operand:QQ 0 "s_register_operand" "") 145 [(set (match_operand:QQ 0 "s_register_operand")
102 (mult:QQ (match_operand:QQ 1 "s_register_operand" "") 146 (mult:QQ (match_operand:QQ 1 "s_register_operand")
103 (match_operand:QQ 2 "s_register_operand" "")))] 147 (match_operand:QQ 2 "s_register_operand")))]
104 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 148 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
105 { 149 {
106 rtx tmp1 = gen_reg_rtx (HImode); 150 rtx tmp1 = gen_reg_rtx (HImode);
107 rtx tmp2 = gen_reg_rtx (HImode); 151 rtx tmp2 = gen_reg_rtx (HImode);
108 rtx tmp3 = gen_reg_rtx (SImode); 152 rtx tmp3 = gen_reg_rtx (SImode);
114 GEN_INT (7))); 158 GEN_INT (7)));
115 DONE; 159 DONE;
116 }) 160 })
117 161
118 (define_expand "mulhq3" 162 (define_expand "mulhq3"
119 [(set (match_operand:HQ 0 "s_register_operand" "") 163 [(set (match_operand:HQ 0 "s_register_operand")
120 (mult:HQ (match_operand:HQ 1 "s_register_operand" "") 164 (mult:HQ (match_operand:HQ 1 "s_register_operand")
121 (match_operand:HQ 2 "s_register_operand" "")))] 165 (match_operand:HQ 2 "s_register_operand")))]
122 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 166 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
123 { 167 {
124 rtx tmp = gen_reg_rtx (SImode); 168 rtx tmp = gen_reg_rtx (SImode);
125 169
126 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 170 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
132 GEN_INT (16), GEN_INT (15))); 176 GEN_INT (16), GEN_INT (15)));
133 DONE; 177 DONE;
134 }) 178 })
135 179
136 (define_expand "mulsq3" 180 (define_expand "mulsq3"
137 [(set (match_operand:SQ 0 "s_register_operand" "") 181 [(set (match_operand:SQ 0 "s_register_operand")
138 (mult:SQ (match_operand:SQ 1 "s_register_operand" "") 182 (mult:SQ (match_operand:SQ 1 "s_register_operand")
139 (match_operand:SQ 2 "s_register_operand" "")))] 183 (match_operand:SQ 2 "s_register_operand")))]
140 "TARGET_32BIT" 184 "TARGET_32BIT"
141 { 185 {
142 rtx tmp1 = gen_reg_rtx (DImode); 186 rtx tmp1 = gen_reg_rtx (DImode);
143 rtx tmp2 = gen_reg_rtx (SImode); 187 rtx tmp2 = gen_reg_rtx (SImode);
144 rtx tmp3 = gen_reg_rtx (SImode); 188 rtx tmp3 = gen_reg_rtx (SImode);
154 }) 198 })
155 199
156 ;; Accumulator multiplies. 200 ;; Accumulator multiplies.
157 201
158 (define_expand "mulsa3" 202 (define_expand "mulsa3"
159 [(set (match_operand:SA 0 "s_register_operand" "") 203 [(set (match_operand:SA 0 "s_register_operand")
160 (mult:SA (match_operand:SA 1 "s_register_operand" "") 204 (mult:SA (match_operand:SA 1 "s_register_operand")
161 (match_operand:SA 2 "s_register_operand" "")))] 205 (match_operand:SA 2 "s_register_operand")))]
162 "TARGET_32BIT" 206 "TARGET_32BIT"
163 { 207 {
164 rtx tmp1 = gen_reg_rtx (DImode); 208 rtx tmp1 = gen_reg_rtx (DImode);
165 rtx tmp2 = gen_reg_rtx (SImode); 209 rtx tmp2 = gen_reg_rtx (SImode);
166 rtx tmp3 = gen_reg_rtx (SImode); 210 rtx tmp3 = gen_reg_rtx (SImode);
173 217
174 DONE; 218 DONE;
175 }) 219 })
176 220
177 (define_expand "mulusa3" 221 (define_expand "mulusa3"
178 [(set (match_operand:USA 0 "s_register_operand" "") 222 [(set (match_operand:USA 0 "s_register_operand")
179 (mult:USA (match_operand:USA 1 "s_register_operand" "") 223 (mult:USA (match_operand:USA 1 "s_register_operand")
180 (match_operand:USA 2 "s_register_operand" "")))] 224 (match_operand:USA 2 "s_register_operand")))]
181 "TARGET_32BIT" 225 "TARGET_32BIT"
182 { 226 {
183 rtx tmp1 = gen_reg_rtx (DImode); 227 rtx tmp1 = gen_reg_rtx (DImode);
184 rtx tmp2 = gen_reg_rtx (SImode); 228 rtx tmp2 = gen_reg_rtx (SImode);
185 rtx tmp3 = gen_reg_rtx (SImode); 229 rtx tmp3 = gen_reg_rtx (SImode);
191 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); 235 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
192 236
193 DONE; 237 DONE;
194 }) 238 })
195 239
196 ;; The code sequence emitted by this insn pattern uses the Q flag, which GCC 240 ;; The code sequence emitted by this insn pattern uses the Q flag, so we need
197 ;; doesn't generally know about, so we don't bother expanding to individual 241 ;; to bail out when ARM_Q_BIT_READ and resort to a library sequence instead.
198 ;; instructions. It may be better to just use an out-of-line asm libcall for 242
199 ;; this. 243 (define_expand "ssmulsa3"
200 244 [(parallel [(set (match_operand:SA 0 "s_register_operand")
201 (define_insn "ssmulsa3" 245 (ss_mult:SA (match_operand:SA 1 "s_register_operand")
246 (match_operand:SA 2 "s_register_operand")))
247 (clobber (match_scratch:DI 3))
248 (clobber (match_scratch:SI 4))
249 (clobber (reg:CC CC_REGNUM))])]
250 "TARGET_32BIT && arm_arch6"
251 {
252 if (ARM_Q_BIT_READ)
253 FAIL;
254 }
255 )
256
257 (define_insn "*arm_ssmulsa3"
202 [(set (match_operand:SA 0 "s_register_operand" "=r") 258 [(set (match_operand:SA 0 "s_register_operand" "=r")
203 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r") 259 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r")
204 (match_operand:SA 2 "s_register_operand" "r"))) 260 (match_operand:SA 2 "s_register_operand" "r")))
205 (clobber (match_scratch:DI 3 "=r")) 261 (clobber (match_scratch:DI 3 "=r"))
206 (clobber (match_scratch:SI 4 "=r")) 262 (clobber (match_scratch:SI 4 "=r"))
207 (clobber (reg:CC CC_REGNUM))] 263 (clobber (reg:CC CC_REGNUM))]
208 "TARGET_32BIT && arm_arch6" 264 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
209 { 265 {
210 /* s16.15 * s16.15 -> s32.30. */ 266 /* s16.15 * s16.15 -> s32.30. */
211 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands); 267 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands);
212 268
213 if (TARGET_ARM) 269 if (TARGET_ARM)
254 (if_then_else (match_test "arm_restrict_it") 310 (if_then_else (match_test "arm_restrict_it")
255 (const_int 40) 311 (const_int 40)
256 (const_int 38)) 312 (const_int 38))
257 (const_int 32)))]) 313 (const_int 32)))])
258 314
259 ;; Same goes for this. 315 (define_expand "usmulusa3"
260 316 [(parallel [(set (match_operand:USA 0 "s_register_operand")
261 (define_insn "usmulusa3" 317 (us_mult:USA (match_operand:USA 1 "s_register_operand")
318 (match_operand:USA 2 "s_register_operand")))
319 (clobber (match_scratch:DI 3))
320 (clobber (match_scratch:SI 4))
321 (clobber (reg:CC CC_REGNUM))])]
322 "TARGET_32BIT && arm_arch6"
323 {
324 if (ARM_Q_BIT_READ)
325 FAIL;
326 }
327 )
328
329 (define_insn "*arm_usmulusa3"
262 [(set (match_operand:USA 0 "s_register_operand" "=r") 330 [(set (match_operand:USA 0 "s_register_operand" "=r")
263 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r") 331 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r")
264 (match_operand:USA 2 "s_register_operand" "r"))) 332 (match_operand:USA 2 "s_register_operand" "r")))
265 (clobber (match_scratch:DI 3 "=r")) 333 (clobber (match_scratch:DI 3 "=r"))
266 (clobber (match_scratch:SI 4 "=r")) 334 (clobber (match_scratch:SI 4 "=r"))
267 (clobber (reg:CC CC_REGNUM))] 335 (clobber (reg:CC CC_REGNUM))]
268 "TARGET_32BIT && arm_arch6" 336 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
269 { 337 {
270 /* 16.16 * 16.16 -> 32.32. */ 338 /* 16.16 * 16.16 -> 32.32. */
271 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands); 339 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands);
272 340
273 if (TARGET_ARM) 341 if (TARGET_ARM)
315 (const_int 40) 383 (const_int 40)
316 (const_int 38)) 384 (const_int 38))
317 (const_int 32)))]) 385 (const_int 32)))])
318 386
319 (define_expand "mulha3" 387 (define_expand "mulha3"
320 [(set (match_operand:HA 0 "s_register_operand" "") 388 [(set (match_operand:HA 0 "s_register_operand")
321 (mult:HA (match_operand:HA 1 "s_register_operand" "") 389 (mult:HA (match_operand:HA 1 "s_register_operand")
322 (match_operand:HA 2 "s_register_operand" "")))] 390 (match_operand:HA 2 "s_register_operand")))]
323 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 391 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
324 { 392 {
325 rtx tmp = gen_reg_rtx (SImode); 393 rtx tmp = gen_reg_rtx (SImode);
326 394
327 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 395 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
331 399
332 DONE; 400 DONE;
333 }) 401 })
334 402
335 (define_expand "muluha3" 403 (define_expand "muluha3"
336 [(set (match_operand:UHA 0 "s_register_operand" "") 404 [(set (match_operand:UHA 0 "s_register_operand")
337 (mult:UHA (match_operand:UHA 1 "s_register_operand" "") 405 (mult:UHA (match_operand:UHA 1 "s_register_operand")
338 (match_operand:UHA 2 "s_register_operand" "")))] 406 (match_operand:UHA 2 "s_register_operand")))]
339 "TARGET_DSP_MULTIPLY" 407 "TARGET_DSP_MULTIPLY"
340 { 408 {
341 rtx tmp1 = gen_reg_rtx (SImode); 409 rtx tmp1 = gen_reg_rtx (SImode);
342 rtx tmp2 = gen_reg_rtx (SImode); 410 rtx tmp2 = gen_reg_rtx (SImode);
343 rtx tmp3 = gen_reg_rtx (SImode); 411 rtx tmp3 = gen_reg_rtx (SImode);
351 419
352 DONE; 420 DONE;
353 }) 421 })
354 422
355 (define_expand "ssmulha3" 423 (define_expand "ssmulha3"
356 [(set (match_operand:HA 0 "s_register_operand" "") 424 [(set (match_operand:HA 0 "s_register_operand")
357 (ss_mult:HA (match_operand:HA 1 "s_register_operand" "") 425 (ss_mult:HA (match_operand:HA 1 "s_register_operand")
358 (match_operand:HA 2 "s_register_operand" "")))] 426 (match_operand:HA 2 "s_register_operand")))]
359 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6" 427 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
360 { 428 {
429 if (ARM_Q_BIT_READ)
430 FAIL;
361 rtx tmp = gen_reg_rtx (SImode); 431 rtx tmp = gen_reg_rtx (SImode);
362 rtx rshift; 432 rtx rshift;
363 433
364 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 434 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
365 gen_lowpart (HImode, operands[2]))); 435 gen_lowpart (HImode, operands[2])));
371 441
372 DONE; 442 DONE;
373 }) 443 })
374 444
375 (define_expand "usmuluha3" 445 (define_expand "usmuluha3"
376 [(set (match_operand:UHA 0 "s_register_operand" "") 446 [(set (match_operand:UHA 0 "s_register_operand")
377 (us_mult:UHA (match_operand:UHA 1 "s_register_operand" "") 447 (us_mult:UHA (match_operand:UHA 1 "s_register_operand")
378 (match_operand:UHA 2 "s_register_operand" "")))] 448 (match_operand:UHA 2 "s_register_operand")))]
379 "TARGET_INT_SIMD" 449 "TARGET_INT_SIMD"
380 { 450 {
451 if (ARM_Q_BIT_READ)
452 FAIL;
453
381 rtx tmp1 = gen_reg_rtx (SImode); 454 rtx tmp1 = gen_reg_rtx (SImode);
382 rtx tmp2 = gen_reg_rtx (SImode); 455 rtx tmp2 = gen_reg_rtx (SImode);
383 rtx tmp3 = gen_reg_rtx (SImode); 456 rtx tmp3 = gen_reg_rtx (SImode);
384 rtx rshift_tmp = gen_reg_rtx (SImode); 457 rtx rshift_tmp = gen_reg_rtx (SImode);
385 458
403 (define_insn "arm_ssatsihi_shift" 476 (define_insn "arm_ssatsihi_shift"
404 [(set (match_operand:HI 0 "s_register_operand" "=r") 477 [(set (match_operand:HI 0 "s_register_operand" "=r")
405 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator" 478 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator"
406 [(match_operand:SI 2 "s_register_operand" "r") 479 [(match_operand:SI 2 "s_register_operand" "r")
407 (match_operand:SI 3 "immediate_operand" "I")])))] 480 (match_operand:SI 3 "immediate_operand" "I")])))]
408 "TARGET_32BIT && arm_arch6" 481 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
409 "ssat%?\\t%0, #16, %2%S1" 482 "ssat%?\\t%0, #16, %2%S1"
410 [(set_attr "predicable" "yes") 483 [(set_attr "predicable" "yes")
411 (set_attr "shift" "1") 484 (set_attr "shift" "1")
412 (set_attr "type" "alu_shift_imm")]) 485 (set_attr "type" "alu_shift_imm")])
413 486
414 (define_insn "arm_usatsihi" 487 (define_insn "arm_usatsihi"
415 [(set (match_operand:HI 0 "s_register_operand" "=r") 488 [(set (match_operand:HI 0 "s_register_operand" "=r")
416 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))] 489 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
417 "TARGET_INT_SIMD" 490 "TARGET_INT_SIMD && !ARM_Q_BIT_READ"
418 "usat%?\\t%0, #16, %1" 491 "usat%?\\t%0, #16, %1"
419 [(set_attr "predicable" "yes") 492 [(set_attr "predicable" "yes")
420 (set_attr "type" "alu_imm")] 493 (set_attr "type" "alu_imm")]
421 ) 494 )