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1 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
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111
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2 ;;
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3 ;; This file is part of GCC.
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4 ;;
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5 ;; GCC is free software; you can redistribute it and/or modify it
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6 ;; under the terms of the GNU General Public License as published
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7 ;; by the Free Software Foundation; either version 3, or (at your
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8 ;; option) any later version.
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9 ;;
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10 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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11 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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13 ;; License for more details.
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14 ;;
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15 ;; You should have received a copy of the GNU General Public License
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16 ;; along with GCC; see the file COPYING3. If not see
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17 ;; <http://www.gnu.org/licenses/>.
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18 ;;
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19 ;; This file contains ARM instructions that support fixed-point operations.
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20
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21 (define_insn "add<mode>3"
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22 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
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23 (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
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24 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
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25 "TARGET_32BIT"
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26 "add%?\\t%0, %1, %2"
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27 [(set_attr "predicable" "yes")
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28 (set_attr "predicable_short_it" "yes,no")
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29 (set_attr "type" "alu_sreg")])
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30
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145
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31 (define_expand "add<mode>3"
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32 [(set (match_operand:ADDSUB 0 "s_register_operand")
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33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand")
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34 (match_operand:ADDSUB 2 "s_register_operand")))]
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35 "TARGET_INT_SIMD"
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36 {
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37 if (ARM_GE_BITS_READ)
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38 FAIL;
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39 }
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40 )
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41
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42 (define_insn "*arm_add<mode>3"
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111
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43 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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44 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
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45 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
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145
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46 "TARGET_INT_SIMD && !ARM_GE_BITS_READ"
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111
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47 "sadd<qaddsub_suf>%?\\t%0, %1, %2"
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48 [(set_attr "predicable" "yes")
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49 (set_attr "type" "alu_dsp_reg")])
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50
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51 (define_insn "usadd<mode>3"
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52 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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53 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r")
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54 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
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55 "TARGET_INT_SIMD"
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56 "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
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57 [(set_attr "predicable" "yes")
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58 (set_attr "type" "alu_dsp_reg")])
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59
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145
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60 (define_expand "ssadd<mode>3"
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61 [(set (match_operand:QADDSUB 0 "s_register_operand")
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62 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand")
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63 (match_operand:QADDSUB 2 "s_register_operand")))]
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64 "TARGET_INT_SIMD"
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65 {
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66 if (<qaddsub_clob_q>)
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67 FAIL;
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68 }
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69 )
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70
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71 (define_insn "*arm_ssadd<mode>3"
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111
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72 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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73 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
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74 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
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145
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75 "TARGET_INT_SIMD && !<qaddsub_clob_q>"
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111
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76 "qadd<qaddsub_suf>%?\\t%0, %1, %2"
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77 [(set_attr "predicable" "yes")
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78 (set_attr "type" "alu_dsp_reg")])
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79
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80 (define_insn "sub<mode>3"
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81 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
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82 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
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83 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
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84 "TARGET_32BIT"
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85 "sub%?\\t%0, %1, %2"
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86 [(set_attr "predicable" "yes")
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87 (set_attr "predicable_short_it" "yes,no")
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88 (set_attr "type" "alu_sreg")])
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89
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145
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90 (define_expand "sub<mode>3"
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91 [(set (match_operand:ADDSUB 0 "s_register_operand")
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92 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand")
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93 (match_operand:ADDSUB 2 "s_register_operand")))]
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94 "TARGET_INT_SIMD"
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95 {
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96 if (ARM_GE_BITS_READ)
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97 FAIL;
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98 }
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99 )
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100
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101 (define_insn "*arm_sub<mode>3"
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111
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102 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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103 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
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104 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
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145
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105 "TARGET_INT_SIMD && !ARM_GE_BITS_READ"
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111
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106 "ssub<qaddsub_suf>%?\\t%0, %1, %2"
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107 [(set_attr "predicable" "yes")
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108 (set_attr "type" "alu_dsp_reg")])
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109
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110 (define_insn "ussub<mode>3"
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111 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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112 (us_minus:UQADDSUB
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113 (match_operand:UQADDSUB 1 "s_register_operand" "r")
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114 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
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115 "TARGET_INT_SIMD"
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116 "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
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117 [(set_attr "predicable" "yes")
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118 (set_attr "type" "alu_dsp_reg")])
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119
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145
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120 (define_expand "sssub<mode>3"
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121 [(set (match_operand:QADDSUB 0 "s_register_operand")
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122 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand")
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123 (match_operand:QADDSUB 2 "s_register_operand")))]
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124 "TARGET_INT_SIMD"
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125 {
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126 if (<qaddsub_clob_q>)
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127 FAIL;
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128 }
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129 )
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130
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131 (define_insn "*arm_sssub<mode>3"
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111
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132 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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133 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
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134 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
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145
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135 "TARGET_INT_SIMD && !<qaddsub_clob_q>"
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111
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136 "qsub<qaddsub_suf>%?\\t%0, %1, %2"
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137 [(set_attr "predicable" "yes")
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138 (set_attr "type" "alu_dsp_reg")])
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139
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140 ;; Fractional multiplies.
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141
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142 ; Note: none of these do any rounding.
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143
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144 (define_expand "mulqq3"
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145
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145 [(set (match_operand:QQ 0 "s_register_operand")
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146 (mult:QQ (match_operand:QQ 1 "s_register_operand")
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147 (match_operand:QQ 2 "s_register_operand")))]
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111
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148 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
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149 {
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150 rtx tmp1 = gen_reg_rtx (HImode);
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151 rtx tmp2 = gen_reg_rtx (HImode);
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152 rtx tmp3 = gen_reg_rtx (SImode);
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153
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154 emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1])));
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155 emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2])));
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156 emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2));
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157 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp3, GEN_INT (8),
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158 GEN_INT (7)));
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159 DONE;
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160 })
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161
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162 (define_expand "mulhq3"
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145
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163 [(set (match_operand:HQ 0 "s_register_operand")
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164 (mult:HQ (match_operand:HQ 1 "s_register_operand")
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165 (match_operand:HQ 2 "s_register_operand")))]
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111
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166 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
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167 {
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168 rtx tmp = gen_reg_rtx (SImode);
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169
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170 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
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171 gen_lowpart (HImode, operands[2])));
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172 /* We're doing a s.15 * s.15 multiplication, getting an s.30 result. Extract
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173 an s.15 value from that. This won't overflow/saturate for _Fract
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174 values. */
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175 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp,
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176 GEN_INT (16), GEN_INT (15)));
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177 DONE;
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178 })
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179
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180 (define_expand "mulsq3"
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145
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181 [(set (match_operand:SQ 0 "s_register_operand")
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182 (mult:SQ (match_operand:SQ 1 "s_register_operand")
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183 (match_operand:SQ 2 "s_register_operand")))]
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131
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184 "TARGET_32BIT"
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111
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185 {
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186 rtx tmp1 = gen_reg_rtx (DImode);
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187 rtx tmp2 = gen_reg_rtx (SImode);
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188 rtx tmp3 = gen_reg_rtx (SImode);
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189
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190 /* s.31 * s.31 -> s.62 multiplication. */
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191 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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192 gen_lowpart (SImode, operands[2])));
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193 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (31)));
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194 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (1)));
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195 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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196
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197 DONE;
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198 })
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199
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200 ;; Accumulator multiplies.
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201
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202 (define_expand "mulsa3"
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145
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203 [(set (match_operand:SA 0 "s_register_operand")
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204 (mult:SA (match_operand:SA 1 "s_register_operand")
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205 (match_operand:SA 2 "s_register_operand")))]
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131
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206 "TARGET_32BIT"
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111
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207 {
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208 rtx tmp1 = gen_reg_rtx (DImode);
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209 rtx tmp2 = gen_reg_rtx (SImode);
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210 rtx tmp3 = gen_reg_rtx (SImode);
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211
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212 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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213 gen_lowpart (SImode, operands[2])));
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214 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15)));
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215 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (17)));
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216 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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217
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218 DONE;
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219 })
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220
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221 (define_expand "mulusa3"
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145
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222 [(set (match_operand:USA 0 "s_register_operand")
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223 (mult:USA (match_operand:USA 1 "s_register_operand")
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224 (match_operand:USA 2 "s_register_operand")))]
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131
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225 "TARGET_32BIT"
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111
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226 {
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227 rtx tmp1 = gen_reg_rtx (DImode);
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228 rtx tmp2 = gen_reg_rtx (SImode);
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229 rtx tmp3 = gen_reg_rtx (SImode);
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230
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231 emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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232 gen_lowpart (SImode, operands[2])));
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233 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16)));
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234 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16)));
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235 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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236
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237 DONE;
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238 })
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239
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145
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240 ;; The code sequence emitted by this insn pattern uses the Q flag, so we need
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241 ;; to bail out when ARM_Q_BIT_READ and resort to a library sequence instead.
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111
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242
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145
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243 (define_expand "ssmulsa3"
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244 [(parallel [(set (match_operand:SA 0 "s_register_operand")
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245 (ss_mult:SA (match_operand:SA 1 "s_register_operand")
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246 (match_operand:SA 2 "s_register_operand")))
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247 (clobber (match_scratch:DI 3))
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248 (clobber (match_scratch:SI 4))
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249 (clobber (reg:CC CC_REGNUM))])]
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250 "TARGET_32BIT && arm_arch6"
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251 {
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252 if (ARM_Q_BIT_READ)
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253 FAIL;
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254 }
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255 )
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256
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257 (define_insn "*arm_ssmulsa3"
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111
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258 [(set (match_operand:SA 0 "s_register_operand" "=r")
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259 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r")
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260 (match_operand:SA 2 "s_register_operand" "r")))
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261 (clobber (match_scratch:DI 3 "=r"))
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262 (clobber (match_scratch:SI 4 "=r"))
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263 (clobber (reg:CC CC_REGNUM))]
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145
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264 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
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111
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265 {
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266 /* s16.15 * s16.15 -> s32.30. */
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267 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands);
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268
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269 if (TARGET_ARM)
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270 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
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271 else
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272 {
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273 output_asm_insn ("mov\\t%4, #0", operands);
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274 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
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275 }
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276
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277 /* We have:
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278 31 high word 0 31 low word 0
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279
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280 [ S i i .... i i i ] [ i f f f ... f f ]
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281 |
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282 v
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283 [ S i ... i f ... f f ]
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284
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285 Need 16 integral bits, so saturate at 15th bit of high word. */
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286
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287 output_asm_insn ("ssat\\t%R3, #15, %R3", operands);
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288 output_asm_insn ("mrs\\t%4, APSR", operands);
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289 output_asm_insn ("tst\\t%4, #1<<27", operands);
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290 if (arm_restrict_it)
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291 {
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292 output_asm_insn ("mvn\\t%4, %R3, asr #32", operands);
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293 output_asm_insn ("it\\tne", operands);
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294 output_asm_insn ("movne\\t%Q3, %4", operands);
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295 }
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296 else
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297 {
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298 if (TARGET_THUMB2)
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299 output_asm_insn ("it\\tne", operands);
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300 output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands);
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301 }
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302 output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands);
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303 output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands);
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304 return "";
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305 }
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306 [(set_attr "conds" "clob")
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307 (set_attr "type" "multiple")
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308 (set (attr "length")
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309 (if_then_else (eq_attr "is_thumb" "yes")
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310 (if_then_else (match_test "arm_restrict_it")
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311 (const_int 40)
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312 (const_int 38))
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313 (const_int 32)))])
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314
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145
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315 (define_expand "usmulusa3"
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316 [(parallel [(set (match_operand:USA 0 "s_register_operand")
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317 (us_mult:USA (match_operand:USA 1 "s_register_operand")
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318 (match_operand:USA 2 "s_register_operand")))
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319 (clobber (match_scratch:DI 3))
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320 (clobber (match_scratch:SI 4))
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321 (clobber (reg:CC CC_REGNUM))])]
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322 "TARGET_32BIT && arm_arch6"
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323 {
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324 if (ARM_Q_BIT_READ)
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325 FAIL;
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326 }
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327 )
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111
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328
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145
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329 (define_insn "*arm_usmulusa3"
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111
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330 [(set (match_operand:USA 0 "s_register_operand" "=r")
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331 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r")
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332 (match_operand:USA 2 "s_register_operand" "r")))
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333 (clobber (match_scratch:DI 3 "=r"))
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334 (clobber (match_scratch:SI 4 "=r"))
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335 (clobber (reg:CC CC_REGNUM))]
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145
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336 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
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111
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337 {
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338 /* 16.16 * 16.16 -> 32.32. */
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339 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands);
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340
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341 if (TARGET_ARM)
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342 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
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343 else
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344 {
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345 output_asm_insn ("mov\\t%4, #0", operands);
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346 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
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347 }
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348
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349 /* We have:
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350 31 high word 0 31 low word 0
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351
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352 [ i i i .... i i i ] [ f f f f ... f f ]
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353 |
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354 v
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355 [ i i ... i f ... f f ]
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356
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357 Need 16 integral bits, so saturate at 16th bit of high word. */
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358
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359 output_asm_insn ("usat\\t%R3, #16, %R3", operands);
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360 output_asm_insn ("mrs\\t%4, APSR", operands);
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361 output_asm_insn ("tst\\t%4, #1<<27", operands);
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362 if (arm_restrict_it)
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363 {
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364 output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands);
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365 output_asm_insn ("it\\tne", operands);
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366 output_asm_insn ("movne\\t%Q3, %4", operands);
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367 }
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368 else
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369 {
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370 if (TARGET_THUMB2)
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371 output_asm_insn ("it\\tne", operands);
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372 output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands);
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373 }
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374 output_asm_insn ("lsr\\t%0, %Q3, #16", operands);
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375 output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands);
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376 return "";
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377 }
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378 [(set_attr "conds" "clob")
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379 (set_attr "type" "multiple")
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380 (set (attr "length")
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381 (if_then_else (eq_attr "is_thumb" "yes")
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382 (if_then_else (match_test "arm_restrict_it")
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383 (const_int 40)
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384 (const_int 38))
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385 (const_int 32)))])
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386
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387 (define_expand "mulha3"
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145
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388 [(set (match_operand:HA 0 "s_register_operand")
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389 (mult:HA (match_operand:HA 1 "s_register_operand")
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390 (match_operand:HA 2 "s_register_operand")))]
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111
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391 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
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392 {
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393 rtx tmp = gen_reg_rtx (SImode);
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394
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395 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
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396 gen_lowpart (HImode, operands[2])));
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397 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16),
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398 GEN_INT (7)));
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399
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400 DONE;
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401 })
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402
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403 (define_expand "muluha3"
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145
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404 [(set (match_operand:UHA 0 "s_register_operand")
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405 (mult:UHA (match_operand:UHA 1 "s_register_operand")
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406 (match_operand:UHA 2 "s_register_operand")))]
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111
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407 "TARGET_DSP_MULTIPLY"
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408 {
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409 rtx tmp1 = gen_reg_rtx (SImode);
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410 rtx tmp2 = gen_reg_rtx (SImode);
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411 rtx tmp3 = gen_reg_rtx (SImode);
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412
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413 /* 8.8 * 8.8 -> 16.16 multiply. */
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414 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
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415 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
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416 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
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417 emit_insn (gen_extzv (gen_lowpart (SImode, operands[0]), tmp3,
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418 GEN_INT (16), GEN_INT (8)));
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419
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420 DONE;
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421 })
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422
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423 (define_expand "ssmulha3"
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145
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424 [(set (match_operand:HA 0 "s_register_operand")
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425 (ss_mult:HA (match_operand:HA 1 "s_register_operand")
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426 (match_operand:HA 2 "s_register_operand")))]
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111
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427 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
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428 {
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145
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429 if (ARM_Q_BIT_READ)
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430 FAIL;
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111
|
431 rtx tmp = gen_reg_rtx (SImode);
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432 rtx rshift;
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433
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434 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
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435 gen_lowpart (HImode, operands[2])));
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436
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437 rshift = gen_rtx_ASHIFTRT (SImode, tmp, GEN_INT (7));
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438
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439 emit_insn (gen_rtx_SET (gen_lowpart (HImode, operands[0]),
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440 gen_rtx_SS_TRUNCATE (HImode, rshift)));
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441
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442 DONE;
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443 })
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444
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445 (define_expand "usmuluha3"
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|
145
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446 [(set (match_operand:UHA 0 "s_register_operand")
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447 (us_mult:UHA (match_operand:UHA 1 "s_register_operand")
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448 (match_operand:UHA 2 "s_register_operand")))]
|
|
111
|
449 "TARGET_INT_SIMD"
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|
|
450 {
|
|
145
|
451 if (ARM_Q_BIT_READ)
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|
|
452 FAIL;
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453
|
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111
|
454 rtx tmp1 = gen_reg_rtx (SImode);
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455 rtx tmp2 = gen_reg_rtx (SImode);
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456 rtx tmp3 = gen_reg_rtx (SImode);
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457 rtx rshift_tmp = gen_reg_rtx (SImode);
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458
|
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459 /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a
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|
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460 normal 32x32->32-bit multiply instead. */
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461 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
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462 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
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|
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463
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464 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
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465
|
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466 /* The operand to "usat" is signed, so we cannot use the "..., asr #8"
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|
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467 form of that instruction since the multiplication result TMP3 may have the
|
|
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468 top bit set, thus be negative and saturate to zero. Use a separate
|
|
|
469 logical right-shift instead. */
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|
|
470 emit_insn (gen_lshrsi3 (rshift_tmp, tmp3, GEN_INT (8)));
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|
|
471 emit_insn (gen_arm_usatsihi (gen_lowpart (HImode, operands[0]), rshift_tmp));
|
|
|
472
|
|
|
473 DONE;
|
|
|
474 })
|
|
|
475
|
|
|
476 (define_insn "arm_ssatsihi_shift"
|
|
|
477 [(set (match_operand:HI 0 "s_register_operand" "=r")
|
|
|
478 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator"
|
|
|
479 [(match_operand:SI 2 "s_register_operand" "r")
|
|
|
480 (match_operand:SI 3 "immediate_operand" "I")])))]
|
|
145
|
481 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ"
|
|
111
|
482 "ssat%?\\t%0, #16, %2%S1"
|
|
|
483 [(set_attr "predicable" "yes")
|
|
|
484 (set_attr "shift" "1")
|
|
|
485 (set_attr "type" "alu_shift_imm")])
|
|
|
486
|
|
|
487 (define_insn "arm_usatsihi"
|
|
|
488 [(set (match_operand:HI 0 "s_register_operand" "=r")
|
|
|
489 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
|
|
145
|
490 "TARGET_INT_SIMD && !ARM_Q_BIT_READ"
|
|
111
|
491 "usat%?\\t%0, #16, %1"
|
|
|
492 [(set_attr "predicable" "yes")
|
|
|
493 (set_attr "type" "alu_imm")]
|
|
|
494 )
|
