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comparison gcc/config/pdp11/pdp11.h @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
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131:84e7813d76e9 145:1830386684a0
1 /* Definitions of target machine for GNU compiler, for the pdp-11 1 /* Definitions of target machine for GNU compiler, for the pdp-11
2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). 3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
4 4
5 This file is part of GCC. 5 This file is part of GCC.
6 6
7 GCC is free software; you can redistribute it and/or modify 7 GCC is free software; you can redistribute it and/or modify
30 30
31 #define TARGET_CPU_CPP_BUILTINS() \ 31 #define TARGET_CPU_CPP_BUILTINS() \
32 do \ 32 do \
33 { \ 33 { \
34 builtin_define_std ("pdp11"); \ 34 builtin_define_std ("pdp11"); \
35 if (TARGET_INT16) \
36 builtin_define_with_int_value ("__pdp11_int", 16); \
37 else \
38 builtin_define_with_int_value ("__pdp11_int", 32); \
39 if (TARGET_40) \
40 builtin_define_with_int_value ("__pdp11_model", 40); \
41 else if (TARGET_45) \
42 builtin_define_with_int_value ("__pdp11_model", 45); \
43 else \
44 builtin_define_with_int_value ("__pdp11_model", 10); \
45 if (TARGET_FPU) \
46 builtin_define ("__pdp11_fpu"); \
47 if (TARGET_AC0) \
48 builtin_define ("__pdp11_ac0"); \
35 } \ 49 } \
36 while (0) 50 while (0)
37 51
38 52
39 /* Generate DBX debugging information. */ 53 /* Generate DBX debugging information. */
127 #define BIGGEST_ALIGNMENT 16 141 #define BIGGEST_ALIGNMENT 16
128 142
129 /* Define this if move instructions will actually fail to work 143 /* Define this if move instructions will actually fail to work
130 when given unaligned data. */ 144 when given unaligned data. */
131 #define STRICT_ALIGNMENT 1 145 #define STRICT_ALIGNMENT 1
146
147 /* "HW_DIVIDE" actually means 64 by 32 bit divide. While some PDP11
148 models have hardware divide, it is for 32 by 16 bits only, so we
149 call this platform "no hardware divide". */
150 #define TARGET_HAS_NO_HW_DIVIDE 1
132 151
133 /* Standard register usage. */ 152 /* Standard register usage. */
134 153
135 /* Number of actual hardware registers. 154 /* Number of actual hardware registers.
136 The hardware registers are assigned numbers for the compiler 155 The hardware registers are assigned numbers for the compiler
151 */ 170 */
152 171
153 #define FIXED_REGISTERS \ 172 #define FIXED_REGISTERS \
154 {0, 0, 0, 0, 0, 0, 1, 1, \ 173 {0, 0, 0, 0, 0, 0, 1, 1, \
155 0, 0, 0, 0, 0, 0, 1, 1, \ 174 0, 0, 0, 0, 0, 0, 1, 1, \
156 1, 1 } 175 1 }
157 176
158 177
159 178
160 /* 1 for registers not available across function calls. 179 /* 1 for registers not available across function calls.
161 These must include the FIXED_REGISTERS and also any 180 These must include the FIXED_REGISTERS and also any
166 185
167 /* don't know about fp */ 186 /* don't know about fp */
168 #define CALL_USED_REGISTERS \ 187 #define CALL_USED_REGISTERS \
169 {1, 1, 0, 0, 0, 0, 1, 1, \ 188 {1, 1, 0, 0, 0, 0, 1, 1, \
170 0, 0, 0, 0, 0, 0, 1, 1, \ 189 0, 0, 0, 0, 0, 0, 1, 1, \
171 1, 1 } 190 1 }
172 191
173 192
174 /* Specify the registers used for certain standard purposes. 193 /* Specify the registers used for certain standard purposes.
175 The values of these macros are register numbers. */ 194 The values of these macros are register numbers. */
176 195
209 CC_REGS is the condition codes (CPU and FPU) 228 CC_REGS is the condition codes (CPU and FPU)
210 */ 229 */
211 230
212 enum reg_class 231 enum reg_class
213 { NO_REGS, 232 { NO_REGS,
233 NOTR0_REG,
234 NOTR1_REG,
235 NOTR2_REG,
236 NOTR3_REG,
237 NOTR4_REG,
238 NOTR5_REG,
239 NOTSP_REG,
214 MUL_REGS, 240 MUL_REGS,
215 GENERAL_REGS, 241 GENERAL_REGS,
216 LOAD_FPU_REGS, 242 LOAD_FPU_REGS,
217 NO_LOAD_FPU_REGS, 243 NO_LOAD_FPU_REGS,
218 FPU_REGS, 244 FPU_REGS,
227 253
228 /* Give names of register classes as strings for dump file. */ 254 /* Give names of register classes as strings for dump file. */
229 255
230 #define REG_CLASS_NAMES \ 256 #define REG_CLASS_NAMES \
231 { "NO_REGS", \ 257 { "NO_REGS", \
258 "NOTR0_REG", \
259 "NOTR1_REG", \
260 "NOTR2_REG", \
261 "NOTR3_REG", \
262 "NOTR4_REG", \
263 "NOTR5_REG", \
264 "SP_REG", \
232 "MUL_REGS", \ 265 "MUL_REGS", \
233 "GENERAL_REGS", \ 266 "GENERAL_REGS", \
234 "LOAD_FPU_REGS", \ 267 "LOAD_FPU_REGS", \
235 "NO_LOAD_FPU_REGS", \ 268 "NO_LOAD_FPU_REGS", \
236 "FPU_REGS", \ 269 "FPU_REGS", \
241 This is an initializer for a vector of HARD_REG_SET 274 This is an initializer for a vector of HARD_REG_SET
242 of length N_REG_CLASSES. */ 275 of length N_REG_CLASSES. */
243 276
244 #define REG_CLASS_CONTENTS \ 277 #define REG_CLASS_CONTENTS \
245 { {0x00000}, /* NO_REGS */ \ 278 { {0x00000}, /* NO_REGS */ \
246 {0x000aa}, /* MUL_REGS */ \ 279 {0x000fe}, /* NOTR0_REG */ \
247 {0x0c0ff}, /* GENERAL_REGS */ \ 280 {0x000fd}, /* NOTR1_REG */ \
281 {0x000fb}, /* NOTR2_REG */ \
282 {0x000f7}, /* NOTR3_REG */ \
283 {0x000ef}, /* NOTR4_REG */ \
284 {0x000df}, /* NOTR5_REG */ \
285 {0x000bf}, /* NOTSP_REG */ \
286 {0x0002a}, /* MUL_REGS */ \
287 {0x040ff}, /* GENERAL_REGS */ \
248 {0x00f00}, /* LOAD_FPU_REGS */ \ 288 {0x00f00}, /* LOAD_FPU_REGS */ \
249 {0x03000}, /* NO_LOAD_FPU_REGS */ \ 289 {0x03000}, /* NO_LOAD_FPU_REGS */ \
250 {0x03f00}, /* FPU_REGS */ \ 290 {0x03f00}, /* FPU_REGS */ \
251 {0x30000}, /* CC_REGS */ \ 291 {0x18000}, /* CC_REGS */ \
252 {0x3ffff}} /* ALL_REGS */ 292 {0x1ffff}} /* ALL_REGS */
253 293
254 /* The same information, inverted: 294 /* The same information, inverted:
255 Return the class number of the smallest class containing 295 Return the class number of the smallest class containing
256 reg number REGNO. This could be a conditional expression 296 reg number REGNO. This could be a conditional expression
257 or could index an array. */ 297 or could index an array. */
260 300
261 /* The class value for index registers, and the one for base regs. */ 301 /* The class value for index registers, and the one for base regs. */
262 #define INDEX_REG_CLASS GENERAL_REGS 302 #define INDEX_REG_CLASS GENERAL_REGS
263 #define BASE_REG_CLASS GENERAL_REGS 303 #define BASE_REG_CLASS GENERAL_REGS
264 304
305 /* Return TRUE if the class is a CPU register. */
306 #define CPU_REG_CLASS(CLASS) \
307 (CLASS >= NOTR0_REG && CLASS <= GENERAL_REGS)
308
265 /* Return the maximum number of consecutive registers 309 /* Return the maximum number of consecutive registers
266 needed to represent mode MODE in a register of class CLASS. */ 310 needed to represent mode MODE in a register of class CLASS. */
267 #define CLASS_MAX_NREGS(CLASS, MODE) \ 311 #define CLASS_MAX_NREGS(CLASS, MODE) \
268 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ 312 (CPU_REG_CLASS (CLASS) ? \
269 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ 313 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \
270 1 \ 314 1 \
271 ) 315 )
272 316
273 /* Stack layout; function entry, exit and calling. */ 317 /* Stack layout; function entry, exit and calling. */
274 318
275 /* Define this if pushing a word on the stack 319 /* Define this if pushing a word on the stack
276 makes the stack pointer a smaller address. */ 320 makes the stack pointer a smaller address. */
326 ((CUM) = 0) 370 ((CUM) = 0)
327 371
328 /* Output assembler code to FILE to increment profiler label # LABELNO 372 /* Output assembler code to FILE to increment profiler label # LABELNO
329 for profiling a function entry. */ 373 for profiling a function entry. */
330 374
331 #define FUNCTION_PROFILER(FILE, LABELNO) \ 375 #define FUNCTION_PROFILER(FILE, LABELNO)
332 gcc_unreachable ();
333 376
334 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 377 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
335 the stack pointer does not matter. The value is tested only in 378 the stack pointer does not matter. The value is tested only in
336 functions that have frame pointers. 379 functions that have frame pointers.
337 No definition is equivalent to always zero. */ 380 No definition is equivalent to always zero. */
338 381
339 extern int may_call_alloca;
340
341 #define EXIT_IGNORE_STACK 1 382 #define EXIT_IGNORE_STACK 1
342 383
343 /* Definitions for register eliminations. 384 /* Definitions for register eliminations.
344 385
345 This is an array of structures. Each structure initializes one pair 386 This is an array of structures. Each structure initializes one pair
346 of eliminable registers. The "from" register number is given first, 387 of eliminable registers. The "from" register number is given first,
347 followed by "to". Eliminations of the same "from" register are listed 388 followed by "to". Eliminations of the same "from" register are listed
348 in order of preference. 389 in order of preference.
349 390
350 There are two registers that can always be eliminated on the pdp11. 391 There are two registers that can be eliminated on the pdp11. The
351 The frame pointer and the arg pointer can be replaced by either the 392 arg pointer can be replaced by the frame pointer; the frame pointer
352 hard frame pointer or to the stack pointer, depending upon the 393 can often be replaced by the stack pointer. */
353 circumstances. The hard frame pointer is not used before reload and
354 so it is not eligible for elimination. */
355 394
356 #define ELIMINABLE_REGS \ 395 #define ELIMINABLE_REGS \
357 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 396 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
358 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 397 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
359 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 398 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
360 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
361 399
362 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 400 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
363 ((OFFSET) = pdp11_initial_elimination_offset ((FROM), (TO))) 401 ((OFFSET) = pdp11_initial_elimination_offset ((FROM), (TO)))
364 402
365 403
512 /* How to refer to registers in assembler output. 550 /* How to refer to registers in assembler output.
513 This sequence is indexed by compiler's hard-register-number (see above). */ 551 This sequence is indexed by compiler's hard-register-number (see above). */
514 552
515 #define REGISTER_NAMES \ 553 #define REGISTER_NAMES \
516 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ 554 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \
517 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5", "fp", "ap", \ 555 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5", "ap", "cc", \
518 "cc", "fcc" } 556 "fcc" }
519 557
520 /* Globalizing directive for a label. */ 558 /* Globalizing directive for a label. */
521 #define GLOBAL_ASM_OP "\t.globl\t" 559 #define GLOBAL_ASM_OP "\t.globl\t"
522 560
523 /* The prefix to add to user-visible assembler symbols. For the DEC 561 /* The prefix to add to user-visible assembler symbols. For the DEC
566 /* This is how to output an element of a case-vector that is absolute. */ 604 /* This is how to output an element of a case-vector that is absolute. */
567 605
568 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 606 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
569 pdp11_output_addr_vec_elt (FILE, VALUE) 607 pdp11_output_addr_vec_elt (FILE, VALUE)
570 608
571 /* This is how to output an assembler line 609 /* This is how to output an assembler line that says to advance the
572 that says to advance the location counter 610 location counter to a multiple of 2**LOG bytes. Only values 0 and
573 to a multiple of 2**LOG bytes. 611 1 should appear, but due to PR87795 larger values (which are not
612 supported) can also appear. So we treat all alignment of LOG >= 1
613 as word (2 byte) alignment.
574 */ 614 */
575 615
576 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 616 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
577 switch (LOG) \ 617 if (LOG != 0) \
578 { \ 618 fprintf (FILE, "\t.even\n")
579 case 0: \
580 break; \
581 case 1: \
582 fprintf (FILE, "\t.even\n"); \
583 break; \
584 default: \
585 gcc_unreachable (); \
586 }
587 619
588 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 620 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
589 if (TARGET_DEC_ASM) \ 621 if (TARGET_DEC_ASM) \
590 fprintf (FILE, "\t.blkb\t%ho\n", (SIZE) & 0xffff); \ 622 fprintf (FILE, "\t.blkb\t%o\n", (SIZE) & 0xffff); \
591 else \ 623 else \
592 fprintf (FILE, "\t.=.+ %#ho\n", (SIZE) & 0xffff); 624 fprintf (FILE, "\t.=.+ %#o\n", (SIZE) & 0xffff);
593 625
594 /* This says how to output an assembler line 626 /* This says how to output an assembler line
595 to define a global common symbol. */ 627 to define a global common symbol. */
596 628
597 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 629 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
598 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, true) 630 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, true)
599
600 631
601 /* This says how to output an assembler line 632 /* This says how to output an assembler line
602 to define a local common symbol. */ 633 to define a local common symbol. */
603 634
604 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 635 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \