CbC/CbC_gcc: gcc/doc/rtl.texi comparison

comparison gcc/doc/rtl.texi @ 145:1830386684a0

gcc-9.2.0

author	anatofuz
date	Thu, 13 Feb 2020 11:34:05 +0900
parents	84e7813d76e9
children

comparison

equal deleted inserted replaced

-:84e7813d76e9
+:1830386684a0
-@c Copyright (C) 1988-2018 Free Software Foundation, Inc.
+@c Copyright (C) 1988-2020 Free Software Foundation, Inc.
 @c This is part of the GCC manual.
 @c For copying conditions, see the file gcc.texi.
 @node RTL
 @chapter RTL Representation
 The number of @code{HOST_WIDE_INT}s used to represent the number.
 Note that this generally is smaller than the number of
 @code{HOST_WIDE_INT}s implied by the mode size.
 @findex CONST_WIDE_INT_ELT
-@item CONST_WIDE_INT_NUNITS (@var{code},@var{i})
+@item CONST_WIDE_INT_ELT (@var{code},@var{i})
 Returns the @code{i}th element of the array.   Element 0 is contains
 the low order bits of the constant.
 @findex const_fixed
 @item (const_fixed:@var{m} @dots{})
 @end smallexample
 Thus the first 6 elements (@samp{@{ 0, 1, 2, 6, 3, 8 @}}) are enough
 to determine the whole sequence; we refer to them as the ``encoded''
 elements.  They are the only elements present in the square brackets
-for variable-length @code{const_vector}s (i.e. for
+for variable-length @code{const_vector}s (i.e.@: for
 @code{const_vector}s whose mode @var{m} has a variable number of
 elements).  However, as a convenience to code that needs to handle
 both @code{const_vector}s and @code{parallel}s, all elements are
 present in the square brackets for fixed-length @code{const_vector}s;
 the encoding scheme simply reduces the amount of work involved in
 @code{unspec}s are target-specific and typically represent some form
 of relocation operator.  @var{m} should be a valid address mode.
 @findex high
 @item (high:@var{m} @var{exp})
-Represents the high-order bits of @var{exp}, usually a
+Represents the high-order bits of @var{exp}.
-@code{symbol_ref}.  The number of bits is machine-dependent and is
+The number of bits is machine-dependent and is
 normally the number of bits specified in an instruction that initializes
 the high order bits of a register.  It is used with @code{lo_sum} to
 represent the typical two-instruction sequence used in RISC machines to
-reference a global memory location.
+reference large immediate values and/or link-time constants such
+as global memory addresses.  In the latter case, @var{m} is @code{Pmode}
-@var{m} should be @code{Pmode}.
+and @var{exp} is usually a constant expression involving @code{symbol_ref}.
 @end table
 @findex CONST0_RTX
 @findex CONST1_RTX
 @findex CONST2_RTX
 @findex lo_sum
 @item (lo_sum:@var{m} @var{x} @var{y})
 This expression represents the sum of @var{x} and the low-order bits
 of @var{y}.  It is used with @code{high} (@pxref{Constants}) to
-represent the typical two-instruction sequence used in RISC machines
+represent the typical two-instruction sequence used in RISC machines to
-to reference a global memory location.
+reference large immediate values and/or link-time constants such
+as global memory addresses.  In the latter case, @var{m} is @code{Pmode}
+and @var{y} is usually a constant expression involving @code{symbol_ref}.
 The number of low order bits is machine-dependent but is
-normally the number of bits in a @code{Pmode} item minus the number of
+normally the number of bits in mode @var{m} minus the number of
 bits set by @code{high}.
-@var{m} should be @code{Pmode}.
 @findex minus
 @findex ss_minus
 @findex us_minus
 @cindex RTL difference
 in the @code{insv} or @code{extv} pattern.
 The mode @var{m} is the same as the mode that would be used for
 @var{loc} if it were a register.
-A @code{sign_extract} can not appear as an lvalue, or part thereof,
+A @code{sign_extract} cannot appear as an lvalue, or part thereof,
 in RTL.
 @findex zero_extract
 @item (zero_extract:@var{m} @var{loc} @var{size} @var{pos})
 Like @code{sign_extract} but refers to an unsigned or zero-extended
 given the value @var{x} and the rest of the register is not changed.
 If @var{lval} is a @code{zero_extract}, then the referenced part of
 the bit-field (a memory or register reference) specified by the
 @code{zero_extract} is given the value @var{x} and the rest of the
-bit-field is not changed.  Note that @code{sign_extract} can not
+bit-field is not changed.  Note that @code{sign_extract} cannot
 appear in @var{lval}.
 If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may
 be either a @code{compare} expression or a value that may have any mode.
 The latter case represents a ``test'' instruction.  The expression
 There is one other known use for clobbering a pseudo register in a
 @code{parallel}: when one of the input operands of the insn is also
 clobbered by the insn.  In this case, using the same pseudo register in
 the clobber and elsewhere in the insn produces the expected results.
-@findex clobber_high
-@item (clobber_high @var{x})
-Represents the storing or possible storing of an unpredictable,
-undescribed value into the upper parts of @var{x}. The mode of the expression
-represents the lower parts of the register which will not be overwritten.
-@code{reg} must be a reg expression.
-One place this is used is when calling into functions where the registers are
-preserved, but only up to a given number of bits.  For example when using
-Aarch64 SVE, calling a TLS descriptor will cause only the lower 128 bits of
-each of the vector registers to be preserved.
 @findex use
 @item (use @var{x})
 Represents the use of the value of @var{x}.  It indicates that the
 value in @var{x} at this point in the program is needed, even though
 it may not be apparent why this is so.  Therefore, the compiler will
 that the register is live.  You should think twice before adding
 @code{use} statements, more often you will want to use @code{unspec}
 instead.  The @code{use} RTX is most commonly useful to describe that
 a fixed register is implicitly used in an insn.  It is also safe to use
 in patterns where the compiler knows for other reasons that the result
-of the whole pattern is variable, such as @samp{movmem@var{m}} or
+of the whole pattern is variable, such as @samp{cpymem@var{m}} or
 @samp{call} patterns.
 During the reload phase, an insn that has a @code{use} as pattern
 can carry a reg_equal note.  These @code{use} insns will be deleted
 before the reload phase exits.
 @item (parallel [@var{x0} @var{x1} @dots{}])
 Represents several side effects performed in parallel.  The square
 brackets stand for a vector; the operand of @code{parallel} is a
 vector of expressions.  @var{x0}, @var{x1} and so on are individual
 side effect expressions---expressions of code @code{set}, @code{call},
-@code{return}, @code{simple_return}, @code{clobber} @code{use} or
+@code{return}, @code{simple_return}, @code{clobber} or @code{use}.
-@code{clobber_high}.
 ``In parallel'' means that first all the values used in the individual
 side-effects are computed, and second all the actual side-effects are
 performed.  For example,
 @findex sequence
 @item (sequence [@var{insns} @dots{}])
 Represents a sequence of insns.  If a @code{sequence} appears in the
 chain of insns, then each of the @var{insns} that appears in the sequence
-must be suitable for appearing in the chain of insns, i.e. must satisfy
+must be suitable for appearing in the chain of insns, i.e.@: must satisfy
 the @code{INSN_P} predicate.
 After delay-slot scheduling is completed, an insn and all the insns that
 reside in its delay slots are grouped together into a @code{sequence}.
 The insn requiring the delay slot is the first insn in the vector;

Mercurial > hg > CbC > CbC_gcc

comparison gcc/doc/rtl.texi @ 145:1830386684a0