--- a/gcc/doc/rtl.texi	Thu Oct 25 07:37:49 2018 +0900
+++ b/gcc/doc/rtl.texi	Thu Feb 13 11:34:05 2020 +0900
@@ -1,4 +1,4 @@
-@c Copyright (C) 1988-2018 Free Software Foundation, Inc.
+@c Copyright (C) 1988-2020 Free Software Foundation, Inc.
 @c This is part of the GCC manual.
 @c For copying conditions, see the file gcc.texi.
 
@@ -1732,7 +1732,7 @@
 @code{HOST_WIDE_INT}s implied by the mode size.
 
 @findex CONST_WIDE_INT_ELT
-@item CONST_WIDE_INT_NUNITS (@var{code},@var{i})
+@item CONST_WIDE_INT_ELT (@var{code},@var{i})
 Returns the @code{i}th element of the array.   Element 0 is contains
 the low order bits of the constant.
 
@@ -1806,7 +1806,7 @@
 Thus the first 6 elements (@samp{@{ 0, 1, 2, 6, 3, 8 @}}) are enough
 to determine the whole sequence; we refer to them as the ``encoded''
 elements.  They are the only elements present in the square brackets
-for variable-length @code{const_vector}s (i.e. for
+for variable-length @code{const_vector}s (i.e.@: for
 @code{const_vector}s whose mode @var{m} has a variable number of
 elements).  However, as a convenience to code that needs to handle
 both @code{const_vector}s and @code{parallel}s, all elements are
@@ -1883,14 +1883,14 @@
 
 @findex high
 @item (high:@var{m} @var{exp})
-Represents the high-order bits of @var{exp}, usually a
-@code{symbol_ref}.  The number of bits is machine-dependent and is
+Represents the high-order bits of @var{exp}.  
+The number of bits is machine-dependent and is
 normally the number of bits specified in an instruction that initializes
 the high order bits of a register.  It is used with @code{lo_sum} to
 represent the typical two-instruction sequence used in RISC machines to
-reference a global memory location.
-
-@var{m} should be @code{Pmode}.
+reference large immediate values and/or link-time constants such
+as global memory addresses.  In the latter case, @var{m} is @code{Pmode}
+and @var{exp} is usually a constant expression involving @code{symbol_ref}.
 @end table
 
 @findex CONST0_RTX
@@ -2429,15 +2429,15 @@
 
 This expression represents the sum of @var{x} and the low-order bits
 of @var{y}.  It is used with @code{high} (@pxref{Constants}) to
-represent the typical two-instruction sequence used in RISC machines
-to reference a global memory location.
+represent the typical two-instruction sequence used in RISC machines to
+reference large immediate values and/or link-time constants such
+as global memory addresses.  In the latter case, @var{m} is @code{Pmode}
+and @var{y} is usually a constant expression involving @code{symbol_ref}.
 
 The number of low order bits is machine-dependent but is
-normally the number of bits in a @code{Pmode} item minus the number of
+normally the number of bits in mode @var{m} minus the number of
 bits set by @code{high}.
 
-@var{m} should be @code{Pmode}.
-
 @findex minus
 @findex ss_minus
 @findex us_minus
@@ -2897,7 +2897,7 @@
 The mode @var{m} is the same as the mode that would be used for
 @var{loc} if it were a register.
 
-A @code{sign_extract} can not appear as an lvalue, or part thereof,
+A @code{sign_extract} cannot appear as an lvalue, or part thereof,
 in RTL.
 
 @findex zero_extract
@@ -3157,7 +3157,7 @@
 If @var{lval} is a @code{zero_extract}, then the referenced part of
 the bit-field (a memory or register reference) specified by the
 @code{zero_extract} is given the value @var{x} and the rest of the
-bit-field is not changed.  Note that @code{sign_extract} can not
+bit-field is not changed.  Note that @code{sign_extract} cannot
 appear in @var{lval}.
 
 If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may
@@ -3295,18 +3295,6 @@
 clobbered by the insn.  In this case, using the same pseudo register in
 the clobber and elsewhere in the insn produces the expected results.
 
-@findex clobber_high
-@item (clobber_high @var{x})
-Represents the storing or possible storing of an unpredictable,
-undescribed value into the upper parts of @var{x}. The mode of the expression
-represents the lower parts of the register which will not be overwritten.
-@code{reg} must be a reg expression.
-
-One place this is used is when calling into functions where the registers are
-preserved, but only up to a given number of bits.  For example when using
-Aarch64 SVE, calling a TLS descriptor will cause only the lower 128 bits of
-each of the vector registers to be preserved.
-
 @findex use
 @item (use @var{x})
 Represents the use of the value of @var{x}.  It indicates that the
@@ -3341,7 +3329,7 @@
 instead.  The @code{use} RTX is most commonly useful to describe that
 a fixed register is implicitly used in an insn.  It is also safe to use
 in patterns where the compiler knows for other reasons that the result
-of the whole pattern is variable, such as @samp{movmem@var{m}} or
+of the whole pattern is variable, such as @samp{cpymem@var{m}} or
 @samp{call} patterns.
 
 During the reload phase, an insn that has a @code{use} as pattern
@@ -3360,8 +3348,7 @@
 brackets stand for a vector; the operand of @code{parallel} is a
 vector of expressions.  @var{x0}, @var{x1} and so on are individual
 side effect expressions---expressions of code @code{set}, @code{call},
-@code{return}, @code{simple_return}, @code{clobber} @code{use} or
-@code{clobber_high}.
+@code{return}, @code{simple_return}, @code{clobber} or @code{use}.
 
 ``In parallel'' means that first all the values used in the individual
 side-effects are computed, and second all the actual side-effects are
@@ -3417,7 +3404,7 @@
 @item (sequence [@var{insns} @dots{}])
 Represents a sequence of insns.  If a @code{sequence} appears in the
 chain of insns, then each of the @var{insns} that appears in the sequence
-must be suitable for appearing in the chain of insns, i.e. must satisfy
+must be suitable for appearing in the chain of insns, i.e.@: must satisfy
 the @code{INSN_P} predicate.
 
 After delay-slot scheduling is completed, an insn and all the insns that