CbC/CbC_gcc: gcc/lra-constraints.c comparison

comparison gcc/lra-constraints.c @ 145:1830386684a0

gcc-9.2.0

author	anatofuz
date	Thu, 13 Feb 2020 11:34:05 +0900
parents	84e7813d76e9
children

comparison

equal deleted inserted replaced

-:84e7813d76e9
+:1830386684a0
 /* Code for RTL transformations to satisfy insn constraints.
-Copyright (C) 2010-2018 Free Software Foundation, Inc.
+Copyright (C) 2010-2020 Free Software Foundation, Inc.
 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify it under
 #include "output.h"
 #include "addresses.h"
 #include "expr.h"
 #include "cfgrtl.h"
 #include "rtl-error.h"
-#include "params.h"
 #include "lra.h"
 #include "lra-int.h"
 #include "print-rtl.h"
+#include "function-abi.h"
 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
 insn.  Remember that LRA_CURR_RELOAD_NUM is the number of emitted
 reload insns.  */
 static int bb_reload_num;
 m_index_reg (NULL_RTX)
 {
 if (m_base_loc != NULL)
 {
 m_base_reg = *m_base_loc;
-lra_eliminate_reg_if_possible (m_base_loc);
+/* If we have non-legitimate address which is decomposed not in
+	 the way we expected, don't do elimination here.  In such case
+	 the address will be reloaded and elimination will be done in
+	 reload insn finally.  */
+if (REG_P (m_base_reg))
+	lra_eliminate_reg_if_possible (m_base_loc);
 if (m_ad->base_term2 != NULL)
 	*m_ad->base_term2 = *m_ad->base_term;
 }
 if (m_index_loc != NULL)
 {
 m_index_reg = *m_index_loc;
-lra_eliminate_reg_if_possible (m_index_loc);
+if (REG_P (m_index_reg))
+	lra_eliminate_reg_if_possible (m_index_loc);
 }
 }
 address_eliminator::~address_eliminator ()
 {
 }
 if (m_index_loc && *m_index_loc != m_index_reg)
 *m_index_loc = m_index_reg;
 }
-/* Return true if the eliminated form of AD is a legitimate target address.  */
+/* Return true if the eliminated form of AD is a legitimate target address.
+If OP is a MEM, AD is the address within OP, otherwise OP should be
+ignored.  CONSTRAINT is one constraint that the operand may need
+to meet.  */
 static bool
-valid_address_p (struct address_info *ad)
+valid_address_p (rtx op, struct address_info *ad,
+		 enum constraint_num constraint)
 {
 address_eliminator eliminator (ad);
+/* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
+forgiving than "m".  */
+if (MEM_P (op)
+&& (insn_extra_memory_constraint (constraint)
+	  || insn_extra_special_memory_constraint (constraint))
+&& constraint_satisfied_p (op, constraint))
+return true;
 return valid_address_p (ad->mode, *ad->outer, ad->as);
 }
 /* Return true if the eliminated form of memory reference OP satisfies
 extra (special) memory constraint CONSTRAINT.  */
 	 have a situation like "a <- a op b", where the constraints
 	 force the second input operand ("b") to match the output
 	 operand ("a").  "b" must then be copied into a new register
 	 so that it doesn't clobber the current value of "a".
-	 We can not use the same value if the output pseudo is
+	 We cannot use the same value if the output pseudo is
 	 early clobbered or the input pseudo is mentioned in the
 	 output, e.g. as an address part in memory, because
 	 output reload will actually extend the pseudo liveness.
 	 We don't care about eliminable hard regs here as we are
 	 interesting only in pseudos.  */
 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
 for (i = 0; (in = ins[i]) >= 0; i++)
-{
+if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
-lra_assert
+	|| GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]))
-	(GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
-	 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
 *curr_id->operand_loc[in] = new_in_reg;
-}
+else
+{
+	lra_assert
+	  (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in]));
+	*curr_id->operand_loc[in] = new_out_reg;
+}
 lra_update_dups (curr_id, ins);
 if (out < 0)
 return;
 /* See a comment for the input operand above.  */
 narrow_reload_pseudo_class (out_rtx, goal_class);
 const bool addr_was_valid
 	= valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
 alter_subreg (curr_id->operand_loc[nop], false);
 rtx subst = *curr_id->operand_loc[nop];
 lra_assert (MEM_P (subst));
+const bool addr_is_valid = valid_address_p (GET_MODE (subst),
+						  XEXP (subst, 0),
+						  MEM_ADDR_SPACE (subst));
 if (!addr_was_valid
-	  || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
+	  || addr_is_valid
-			      MEM_ADDR_SPACE (subst))
 	  || ((get_constraint_type (lookup_constraint
 				    (curr_static_id->operand[nop].constraint))
 	       != CT_SPECIAL_MEMORY)
 	      /* We still can reload address and if the address is
 		 valid, we can remove subreg without reloading its
 	     However, do not blindly simplify a (subreg (mem ...)) for
 	     WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
 	     data into a register when the inner is narrower than outer or
 	     missing important data from memory when the inner is wider than
 	     outer.  This rule only applies to modes that are no wider than
-	     a word.  */
+	     a word.
-	  if (!(maybe_ne (GET_MODE_PRECISION (mode),
-			  GET_MODE_PRECISION (innermode))
+	     If valid memory becomes invalid after subreg elimination
-		&& known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
+	     and address might be different we still have to reload
-		&& known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
+	     memory.
-		&& WORD_REGISTER_OPERATIONS)
+	  */
+	  if ((! addr_was_valid
+	       || addr_is_valid
+	       || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode)))
+	      && !(maybe_ne (GET_MODE_PRECISION (mode),
+			     GET_MODE_PRECISION (innermode))
+		   && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
+		   && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
+		   && WORD_REGISTER_OPERATIONS)
 	      && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
 		    && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
 		  || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
 		      && targetm.slow_unaligned_access (innermode,
 							MEM_ALIGN (reg)))))
 	  /* INNERMODE is fast, MODE slow.  Reload the mem in INNERMODE.  */
 	  enum reg_class rclass
 	    = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
 	  if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
-			      reg, rclass, TRUE, "slow mem", &new_reg))
+			      reg, rclass, TRUE, "slow/invalid mem", &new_reg))
 	    {
 	      bool insert_before, insert_after;
 	      bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
 	      insert_before = (type != OP_OUT
 	  /* Convert to MODE.  */
 	  reg = operand;
 	  rclass
 	    = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
 	  if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
-			      rclass, TRUE, "slow mem", &new_reg))
+			      rclass, TRUE, "slow/invalid mem", &new_reg))
 	    {
 	      bool insert_before, insert_after;
 	      bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
 	      insert_before = type != OP_OUT;
 				      insert_after ? &after : NULL,
 				      reg, new_reg);
 	    }
 	  *curr_id->operand_loc[nop] = new_reg;
 	  lra_process_new_insns (curr_insn, before, after,
-				 "Inserting slow mem reload");
+				 "Inserting slow/invalid mem reload");
 	  return true;
 	}
 /* If the address was valid and became invalid, prefer to reload
 	 the memory.  Typical case is when the index scale should
 if (x == NULL_RTX)
 return false;
 code = GET_CODE (x);
 mode = GET_MODE (x);
 if (code == SUBREG)
 {
+/* For all SUBREGs we want to check whether the full multi-register
+	 overlaps the set.  For normal SUBREGs this means 'get_hard_regno' of
+	 the inner register, for paradoxical SUBREGs this means the
+	 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
+	 fine.  Use the wider mode for all cases.  */
+rtx subreg = SUBREG_REG (x);
 mode = wider_subreg_mode (x);
-x = SUBREG_REG (x);
+if (mode == GET_MODE (subreg))
-code = GET_CODE (x);
+	{
-}
+	  x = subreg;
+	  code = GET_CODE (x);
-if (REG_P (x))
+	}
+}
+if (REG_P (x) || SUBREG_P (x))
 {
 x_hard_regno = get_hard_regno (x, true);
 return (x_hard_regno >= 0
 	      && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
 }
 				 machine_mode mode)
 {
 HARD_REG_SET temp;
 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
-COPY_HARD_REG_SET (temp, set);
+temp = set & ~lra_no_alloc_regs;
-AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
 return (hard_reg_set_subset_p
 	  (temp, ira_prohibited_class_mode_regs[rclass][mode]));
 }
 /* Used to check validity info about small class input operands.  It
 should be incremented at start of processing an insn
 alternative.  */
 static unsigned int curr_small_class_check = 0;
-/* Update number of used inputs of class OP_CLASS for operand NOP.
+/* Update number of used inputs of class OP_CLASS for operand NOP
-Return true if we have more such class operands than the number of
+of alternative NALT.  Return true if we have more such class operands
-available regs.  */
+than the number of available regs.  */
 static bool
-update_and_check_small_class_inputs (int nop, enum reg_class op_class)
+update_and_check_small_class_inputs (int nop, int nalt,
+				     enum reg_class op_class)
 {
 static unsigned int small_class_check[LIM_REG_CLASSES];
 static int small_class_input_nums[LIM_REG_CLASSES];
 if (SMALL_REGISTER_CLASS_P (op_class)
 /* We are interesting in classes became small because of fixing
 	 some hard regs, e.g. by an user through GCC options.  */
 && hard_reg_set_intersect_p (reg_class_contents[op_class],
 				   ira_no_alloc_regs)
 && (curr_static_id->operand[nop].type != OP_OUT
-	  || curr_static_id->operand[nop].early_clobber))
+	  || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt)))
 {
 if (small_class_check[op_class] == curr_small_class_check)
 	small_class_input_nums[op_class]++;
 else
 	{
 }
 /* Major function to choose the current insn alternative and what
 operands should be reloaded and how.	 If ONLY_ALTERNATIVE is not
 negative we should consider only this alternative.  Return false if
-we can not choose the alternative or find how to reload the
+we cannot choose the alternative or find how to reload the
 operands.  */
 static bool
 process_alt_operands (int only_alternative)
 {
 bool ok_p = false;
 					  *curr_id->operand_loc[m], m_hregno))
 		      {
 			/* We should reject matching of an early
 			   clobber operand if the matching operand is
 			   not dying in the insn.  */
-			if (! curr_static_id->operand[m].early_clobber
+			if (!TEST_BIT (curr_static_id->operand[m]
+				       .early_clobber_alts, nalt)
 			    || operand_reg[nop] == NULL_RTX
 			    || (find_regno_note (curr_insn, REG_DEAD,
 						 REGNO (op))
 				|| REGNO (op) == REGNO (operand_reg[m])))
 			  match_p = true;
 			    && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
 			  continue;
 		      }
 		    else
 		      {
-			/* Operands don't match.  Both operands must
+			/* If the operands do not match and one
-			   allow a reload register, otherwise we
+			   operand is INOUT, we can not match them.
-			   cannot make them match.  */
+			   Try other possibilities, e.g. other
+			   alternatives or commutative operand
+			   exchange.  */
+			if (curr_static_id->operand[nop].type == OP_INOUT
+			    || curr_static_id->operand[m].type == OP_INOUT)
+			  break;
+			/* Operands don't match.  If the operands are
+			   different user defined explicit hard
+			   registers, then we cannot make them match
+			   when one is early clobber operand.  */
+			if ((REG_P (*curr_id->operand_loc[nop])
+			     || SUBREG_P (*curr_id->operand_loc[nop]))
+			    && (REG_P (*curr_id->operand_loc[m])
+				|| SUBREG_P (*curr_id->operand_loc[m])))
+			  {
+			    rtx nop_reg = *curr_id->operand_loc[nop];
+			    if (SUBREG_P (nop_reg))
+			      nop_reg = SUBREG_REG (nop_reg);
+			    rtx m_reg = *curr_id->operand_loc[m];
+			    if (SUBREG_P (m_reg))
+			      m_reg = SUBREG_REG (m_reg);
+			    if (REG_P (nop_reg)
+				&& HARD_REGISTER_P (nop_reg)
+				&& REG_USERVAR_P (nop_reg)
+				&& REG_P (m_reg)
+				&& HARD_REGISTER_P (m_reg)
+				&& REG_USERVAR_P (m_reg))
+			      {
+				int i;
+				for (i = 0; i < early_clobbered_regs_num; i++)
+				  if (m == early_clobbered_nops[i])
+				    break;
+				if (i < early_clobbered_regs_num
+				    || early_clobber_p)
+				  break;
+			      }
+			  }
+			/* Both operands must allow a reload register,
+			   otherwise we cannot make them match.  */
 			if (curr_alt[m] == NO_REGS)
 			  break;
 			/* Retroactively mark the operand we had to
 			   match as a loser, if it wasn't already and
 			   it wasn't matched to a register constraint
 			/* Prefer matching earlyclobber alternative as
 			   it results in less hard regs required for
 			   the insn than a non-matching earlyclobber
 			   alternative.  */
-			if (curr_static_id->operand[m].early_clobber)
+			if (TEST_BIT (curr_static_id->operand[m]
+				      .early_clobber_alts, nalt))
 			  {
 			    if (lra_dump_file != NULL)
 			      fprintf
 				(lra_dump_file,
 				 "            %d Matching earlyclobber alt:"
 		    /* This can be fixed with reloads if the operand
 		       we are supposed to match can be fixed with
 		       reloads. */
 		    badop = false;
 		    this_alternative = curr_alt[m];
-		    COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
+		    this_alternative_set = curr_alt_set[m];
 		    winreg = this_alternative != NO_REGS;
 		    break;
 		  }
 		case 'g':
 		      break;
 		    }
 		  break;
 		reg:
+		  if (mode == BLKmode)
+		    break;
 		  this_alternative = reg_class_subunion[this_alternative][cl];
-		  IOR_HARD_REG_SET (this_alternative_set,
+		  this_alternative_set |= reg_class_contents[cl];
-				    reg_class_contents[cl]);
 		  if (costly_p)
 		    {
 		      this_costly_alternative
 			= reg_class_subunion[this_costly_alternative][cl];
-		      IOR_HARD_REG_SET (this_costly_alternative_set,
+		      this_costly_alternative_set |= reg_class_contents[cl];
-					reg_class_contents[cl]);
 		    }
-		  if (mode == BLKmode)
-		    break;
 		  winreg = true;
 		  if (REG_P (op))
 		    {
 		      if (hard_regno[nop] >= 0
 			  && in_hard_reg_set_p (this_alternative_set,
 		  goto fail;
 		}
 	      if (this_alternative != NO_REGS)
 		{
-		  HARD_REG_SET available_regs;
+		  HARD_REG_SET available_regs
+		    = (reg_class_contents[this_alternative]
-		  COPY_HARD_REG_SET (available_regs,
+		       & ~((ira_prohibited_class_mode_regs
-				     reg_class_contents[this_alternative]);
+			    [this_alternative][mode])
-		  AND_COMPL_HARD_REG_SET
+			   | lra_no_alloc_regs));
-		    (available_regs,
-		     ira_prohibited_class_mode_regs[this_alternative][mode]);
-		  AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
 		  if (hard_reg_set_empty_p (available_regs))
 		    {
 		      /* There are no hard regs holding a value of given
 			 mode.  */
 		      if (offmemok)
 		       "            alt=%d: No input/otput reload -- refuse\n",
 		       nalt);
 		  goto fail;
 		}
-	      /* Alternative loses if it required class pseudo can not
+	      /* Alternative loses if it required class pseudo cannot
 		 hold value of required mode.  Such insns can be
 		 described by insn definitions with mode iterators.  */
 	      if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
 		  && ! hard_reg_set_empty_p (this_alternative_set)
 		  /* It is common practice for constraints to use a
 		     class which does not have actually enough regs to
 		     hold the value (e.g. x86 AREG for mode requiring
 		     more one general reg).  Therefore we have 2
-		     conditions to check that the reload pseudo can
+		     conditions to check that the reload pseudo cannot
-		     not hold the mode value.  */
+		     hold the mode value.  */
 		  && (!targetm.hard_regno_mode_ok
 		      (ira_class_hard_regs[this_alternative][0],
 		       GET_MODE (*curr_id->operand_loc[nop])))
 		  /* The above condition is not enough as the first
 		     reg in ira_class_hard_regs can be not aligned for
 		       GET_MODE (*curr_id->operand_loc[nop]))))
 		{
 		  if (lra_dump_file != NULL)
 		    fprintf (lra_dump_file,
 			     "            alt=%d: reload pseudo for op %d "
-			     " can not hold the mode value -- refuse\n",
+			     "cannot hold the mode value -- refuse\n",
 			     nalt, nop);
 		  goto fail;
 		}
 	      /* Check strong discouragement of reload of non-constant
 		      (op, this_alternative) == NO_REGS
 		      || (curr_static_id->operand[nop].type == OP_OUT
 			  && (targetm.preferred_output_reload_class
 			      (op, this_alternative) == NO_REGS))))
 		{
-		  if (lra_dump_file != NULL)
+		  if (offmemok && REG_P (op))
-		    fprintf (lra_dump_file,
+		    {
-			     "            %d Non-prefered reload: reject+=%d\n",
+		      if (lra_dump_file != NULL)
-			     nop, LRA_MAX_REJECT);
+			fprintf
-		  reject += LRA_MAX_REJECT;
+			  (lra_dump_file,
+			   "            %d Spill pseudo into memory: reject+=3\n",
+			   nop);
+		      reject += 3;
+		    }
+		  else
+		    {
+		      if (lra_dump_file != NULL)
+			fprintf
+			  (lra_dump_file,
+			   "            %d Non-prefered reload: reject+=%d\n",
+			   nop, LRA_MAX_REJECT);
+		      reject += LRA_MAX_REJECT;
+		    }
 		}
 	      if (! (MEM_P (op) && offmemok)
 		  && ! (const_to_mem && constmemok))
 		{
 		      || (curr_static_id->operand[nop].type != OP_IN
 			  && (targetm.secondary_memory_needed
 			      (GET_MODE (op), this_alternative, cl)))))
 		losers++;
-	      /* Input reloads can be inherited more often than output
-		 reloads can be removed, so penalize output
-		 reloads.  */
-	      if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
-		{
-		  if (lra_dump_file != NULL)
-		    fprintf
-		      (lra_dump_file,
-		       "            %d Non input pseudo reload: reject++\n",
-		       nop);
-		  reject++;
-		}
 	      if (MEM_P (op) && offmemok)
 		addr_losers++;
-	      else if (curr_static_id->operand[nop].type == OP_INOUT)
+	      else
 		{
-		  if (lra_dump_file != NULL)
+		  /* Input reloads can be inherited more often than
-		    fprintf
+		     output reloads can be removed, so penalize output
-		      (lra_dump_file,
+		     reloads.  */
-		       "            %d Input/Output reload: reject+=%d\n",
+		  if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
-		       nop, LRA_LOSER_COST_FACTOR);
+		    {
-		  reject += LRA_LOSER_COST_FACTOR;
+		      if (lra_dump_file != NULL)
+			fprintf
+			  (lra_dump_file,
+			   "            %d Non input pseudo reload: reject++\n",
+			   nop);
+		      reject++;
+		    }
+		  if (curr_static_id->operand[nop].type == OP_INOUT)
+		    {
+		      if (lra_dump_file != NULL)
+			fprintf
+			  (lra_dump_file,
+			   "            %d Input/Output reload: reject+=%d\n",
+			   nop, LRA_LOSER_COST_FACTOR);
+		      reject += LRA_LOSER_COST_FACTOR;
+		    }
 		}
 	    }
 	  if (early_clobber_p && ! scratch_p)
 	    {
 			 "            alt=%d,overall=%d,losers=%d -- refuse\n",
 			 nalt, overall, losers);
 goto fail;
 }
-	  if (update_and_check_small_class_inputs (nop, this_alternative))
+	  if (update_and_check_small_class_inputs (nop, nalt,
+						   this_alternative))
 	    {
 	      if (lra_dump_file != NULL)
 		fprintf (lra_dump_file,
 			 "            alt=%d, not enough small class regs -- refuse\n",
 			 nalt);
 	      goto fail;
 	    }
 	  curr_alt[nop] = this_alternative;
-	  COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
+	  curr_alt_set[nop] = this_alternative_set;
 	  curr_alt_win[nop] = this_alternative_win;
 	  curr_alt_match_win[nop] = this_alternative_match_win;
 	  curr_alt_offmemok[nop] = this_alternative_offmemok;
 	  curr_alt_matches[nop] = this_alternative_matches;
 		     && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
 	      {
 		if (first_conflict_j < 0)
 		  first_conflict_j = j;
 		last_conflict_j = j;
+		/* Both the earlyclobber operand and conflicting operand
+		   cannot both be user defined hard registers.  */
+		if (HARD_REGISTER_P (operand_reg[i])
+		    && REG_USERVAR_P (operand_reg[i])
+		    && operand_reg[j] != NULL_RTX
+		    && HARD_REGISTER_P (operand_reg[j])
+		    && REG_USERVAR_P (operand_reg[j]))
+		  fatal_insn ("unable to generate reloads for "
+			      "impossible constraints:", curr_insn);
 	      }
 	  if (last_conflict_j < 0)
 	    continue;
-	  /* If earlyclobber operand conflicts with another
-	     non-matching operand which is actually the same register
+	  /* If an earlyclobber operand conflicts with another non-matching
-	     as the earlyclobber operand, it is better to reload the
+	     operand (ie, they have been assigned the same hard register),
-	     another operand as an operand matching the earlyclobber
+	     then it is better to reload the other operand, as there may
-	     operand can be also the same.  */
+	     exist yet another operand with a matching constraint associated
-	  if (first_conflict_j == last_conflict_j
+	     with the earlyclobber operand.  However, if one of the operands
-	      && operand_reg[last_conflict_j] != NULL_RTX
+	     is an explicit use of a hard register, then we must reload the
-	      && ! curr_alt_match_win[last_conflict_j]
+	     other non-hard register operand.  */
-	      && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
+	  if (HARD_REGISTER_P (operand_reg[i])
+	      || (first_conflict_j == last_conflict_j
+		  && operand_reg[last_conflict_j] != NULL_RTX
+		  && !curr_alt_match_win[last_conflict_j]
+		  && !HARD_REGISTER_P (operand_reg[last_conflict_j])))
 	    {
 	      curr_alt_win[last_conflict_j] = false;
 	      curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
 		= last_conflict_j;
 	      losers++;
 4) the address is a frame address with an invalid base.
 All these cases involve a non-autoinc address, so there is no
 point revalidating other types.  */
-if (ad.autoinc_p || valid_address_p (&ad))
+if (ad.autoinc_p || valid_address_p (op, &ad, cn))
 return change_p;
 /* Any index existed before LRA started, so we can assume that the
 presence and shape of the index is valid.  */
 push_to_sequence (*before);
 				 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
 	      code = recog_memoized (insn);
 	      if (code >= 0)
 		{
 		  *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
-		  if (! valid_address_p (ad.mode, *ad.outer, ad.as))
+		  if (!valid_address_p (op, &ad, cn))
 		    {
 		      /* Try to put lo_sum into register.  */
 		      insn = emit_insn (gen_rtx_SET
 					(new_reg,
 					 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
 		      code = recog_memoized (insn);
 		      if (code >= 0)
 			{
 			  *ad.inner = new_reg;
-			  if (! valid_address_p (ad.mode, *ad.outer, ad.as))
+			  if (!valid_address_p (op, &ad, cn))
 			    {
 			      *ad.inner = addr;
 			      code = -1;
 			    }
 			}
 	  && GET_CODE (SET_SRC (set)) == PLUS
 	  && REG_P (XEXP (SET_SRC (set), 0))
 	  && CONSTANT_P (XEXP (SET_SRC (set), 1)))
 	{
 	  *ad.inner = SET_SRC (set);
-	  if (valid_address_p (ad.mode, *ad.outer, ad.as))
+	  if (valid_address_p (op, &ad, cn))
 	    {
 	      *ad.base_term = XEXP (SET_SRC (set), 0);
 	      *ad.disp_term = XEXP (SET_SRC (set), 1);
 	      cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
 				   get_index_code (&ad));
 /* No alternative works with reloads??  */
 if (INSN_CODE (curr_insn) >= 0)
 	fatal_insn ("unable to generate reloads for:", curr_insn);
 error_for_asm (curr_insn,
 		     "inconsistent operand constraints in an %<asm%>");
+lra_asm_error_p = true;
 /* Avoid further trouble with this insn.  Don't generate use
 	 pattern here as we could use the insn SP offset.  */
 lra_set_insn_deleted (curr_insn);
 return true;
 }
 /* If the mode is changed, it should be wider.  */
 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
 if (sec_mode != rld_mode)
 {
 	  /* If the target says specifically to use another mode for
-	     secondary memory moves we can not reuse the original
+	     secondary memory moves we cannot reuse the original
 	     insn.  */
 	  after = emit_spill_move (false, new_reg, dest);
 	  lra_process_new_insns (curr_insn, NULL, after,
 				 "Inserting the sec. move");
 	  /* We may have non null BEFORE here (e.g. after address
 			|| GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
 		       && (REG_P (SET_DEST (curr_insn_set))
 			   || MEM_P (SET_DEST (curr_insn_set))
 			   || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
 	    optional_p = true;
+	  else if (goal_alt_matched[i][0] != -1
+		   && curr_static_id->operand[i].type == OP_OUT
+		   && (curr_static_id->operand_alternative
+		       [goal_alt_number * n_operands + i].earlyclobber)
+		   && REG_P (op))
+	    {
+	      for (j = 0; goal_alt_matched[i][j] != -1; j++)
+		{
+		  rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]];
+		  if (REG_P (op2) && REGNO (op) != REGNO (op2))
+		    break;
+		}
+	      if (goal_alt_matched[i][j] != -1)
+		{
+		  /* Generate reloads for different output and matched
+		     input registers.  This is the easiest way to avoid
+		     creation of non-existing register conflicts in
+		     lra-lives.c.  */
+		  match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
+				&after, TRUE);
+		  outputs[n_outputs++] = i;
+		  outputs[n_outputs] = -1;
+		}
+	      continue;
+	    }
 	  else
 	    continue;
 	}
 /* Operands that match previous ones have already been handled.  */
 	{
 	  if (regno >= FIRST_PSEUDO_REGISTER)
 	    regno = lra_get_regno_hard_regno (regno);
 	  if (regno < 0)
 	    return false;
-	  COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
+	  alloc_regs = ~lra_no_alloc_regs;
 	  return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
 	}
 else
 	{
 	  if (regno < FIRST_PSEUDO_REGISTER)
 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
 /* The current iteration number of this LRA pass.  */
 int lra_constraint_iter;
-/* True if we substituted equiv which needs checking register
+/* True if we should during assignment sub-pass check assignment
-allocation correctness because the equivalent value contains
+correctness for all pseudos and spill some of them to correct
-allocatable hard registers or when we restore multi-register
+conflicts.  It can be necessary when we substitute equiv which
-pseudo.  */
+needs checking register allocation correctness because the
-bool lra_risky_transformations_p;
+equivalent value contains allocatable hard registers, or when we
+restore multi-register pseudo, or when we change the insn code and
+its operand became INOUT operand when it was IN one before.  */
+bool check_and_force_assignment_correctness_p;
 /* Return true if REGNO is referenced in more than one block.  */
 static bool
 multi_block_pseudo_p (int regno)
 {
 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
 	     lra_constraint_iter);
 changed_p = false;
 if (pic_offset_table_rtx
 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
-lra_risky_transformations_p = true;
+check_and_force_assignment_correctness_p = true;
-else
+else if (first_p)
 /* On the first iteration we should check IRA assignment
 correctness.  In rare cases, the assignments can be wrong as
-early clobbers operands are ignored in IRA.  */
+early clobbers operands are ignored in IRA or usages of
-lra_risky_transformations_p = first_p;
+paradoxical sub-registers are not taken into account by
+IRA.  */
+check_and_force_assignment_correctness_p = true;
 new_insn_uid_start = get_max_uid ();
 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
 /* Mark used hard regs for target stack size calulations.  */
 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
 if (lra_reg_info[i].nrefs != 0
 	reg = regno_reg_rtx[i];
 	if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
 	  {
 	    bool pseudo_p = contains_reg_p (x, false, false);
-	    /* After RTL transformation, we can not guarantee that
+	    /* After RTL transformation, we cannot guarantee that
 	       pseudo in the substitution was not reloaded which might
 	       make equivalence invalid.  For example, in reverse
 	       equiv of p0
 	       p0 <- ...
 		   constant, the right hand side of the init insn can
 		   be a pseudo.  */
 		|| (! reverse_equiv_p (i)
 		    && (init_insn_rhs_dead_pseudo_p (i)
 			/* If we reloaded the pseudo in an equivalence
-			   init insn, we can not remove the equiv init
+			   init insn, we cannot remove the equiv init
 			   insns and the init insns might write into
 			   const memory in this case.  */
 			|| contains_reloaded_insn_p (i)))
 		/* Prevent access beyond equivalent memory for
 		   paradoxical subregs.  */
 	  min_len = new_min_len;
 	  new_insns_num = 0;
 	}
 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
 	internal_error
-	  ("Max. number of generated reload insns per insn is achieved (%d)\n",
+	  ("maximum number of generated reload insns per insn achieved (%d)",
 	   MAX_RELOAD_INSNS_NUMBER);
 new_insns_num++;
 if (DEBUG_INSN_P (curr_insn))
 	{
 	  /* We need to check equivalence in debug insn and change
 	      if (GET_CODE (dest_reg) == SUBREG)
 		dest_reg = SUBREG_REG (dest_reg);
 	      if ((REG_P (dest_reg)
 		   && (x = get_equiv (dest_reg)) != dest_reg
 		   /* Remove insns which set up a pseudo whose value
-		      can not be changed.  Such insns might be not in
+		      cannot be changed.  Such insns might be not in
 		      init_insns because we don't update equiv data
 		      during insn transformations.
 		      As an example, let suppose that a pseudo got
 		      hard register and on the 1st pass was not
 			       INSN_UID (curr_insn),
 			       REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
 		      dump_insn_slim (lra_dump_file, curr_insn);
 		    }
 		  if (contains_reg_p (x, true, false))
-		    lra_risky_transformations_p = true;
+		    check_and_force_assignment_correctness_p = true;
 		  lra_set_insn_deleted (curr_insn);
 		  continue;
 		}
 	    }
 	  curr_id = lra_get_insn_recog_data (curr_insn);
 /* Number of reloads passed so far in current EBB.  */
 static int reloads_num;
 /* Number of calls passed so far in current EBB.  */
 static int calls_num;
+/* Index ID is the CALLS_NUM associated the last call we saw with
+ABI identifier ID.  */
+static int last_call_for_abi[NUM_ABI_IDS];
+/* Which registers have been fully or partially clobbered by a call
+since they were last used.  */
+static HARD_REG_SET full_and_partial_call_clobbers;
 /* Current reload pseudo check for validity of elements in
 USAGE_INSNS.	 */
 static int curr_usage_insns_check;
 usage_insns[regno].check = curr_usage_insns_check;
 usage_insns[regno].insns = insn;
 usage_insns[regno].reloads_num = reloads_num;
 usage_insns[regno].calls_num = calls_num;
 usage_insns[regno].after_p = after_p;
+if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0)
+remove_from_hard_reg_set (&full_and_partial_call_clobbers,
+			      PSEUDO_REGNO_MODE (regno),
+			      reg_renumber[regno]);
 }
 /* The function is used to form list REGNO usages which consists of
 optional debug insns finished by a non-debug insn using REGNO.
 RELOADS_NUM is current number of reload insns processed so far.  */
 /* Registers involved in inheritance/split in the current EBB
 (inheritance/split pseudos and original registers).	*/
 static bitmap_head check_only_regs;
-/* Reload pseudos can not be involded in invariant inheritance in the
+/* Reload pseudos cannot be involded in invariant inheritance in the
 current EBB.  */
 static bitmap_head invalid_invariant_regs;
 /* Do inheritance transformations for insn INSN, which defines (if
 DEF_P) or uses ORIGINAL_REGNO.  NEXT_USAGE_INSNS specifies which
 was assigned to a hard register.  */
 static inline bool
 need_for_call_save_p (int regno)
 {
 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
-return (usage_insns[regno].calls_num < calls_num
+if (usage_insns[regno].calls_num < calls_num)
-	  && (overlaps_hard_reg_set_p
+{
-	      ((flag_ipa_ra &&
+unsigned int abis = 0;
-		! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
+for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
-	       ? lra_reg_info[regno].actual_call_used_reg_set
+	if (last_call_for_abi[i] > usage_insns[regno].calls_num)
-	       : call_used_reg_set,
+	  abis |= 1 << i;
-	       PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
+gcc_assert (abis);
-	      || (targetm.hard_regno_call_part_clobbered
+if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers,
-		  (reg_renumber[regno], PSEUDO_REGNO_MODE (regno)))));
+				      PSEUDO_REGNO_MODE (regno),
+				      reg_renumber[regno]))
+	return true;
+}
+return false;
 }
 /* Global registers occurring in the current EBB.  */
 static bitmap_head ebb_global_regs;
 	       || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
 	   && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
 	   /* Don't split call clobbered hard regs living through
 	      calls, otherwise we might have a check problem in the
 	      assign sub-pass as in the most cases (exception is a
-	      situation when lra_risky_transformations_p value is
+	      situation when check_and_force_assignment_correctness_p value is
 	      true) the assign pass assumes that all pseudos living
 	      through calls are assigned to call saved hard regs.  */
 	   && (regno >= FIRST_PSEUDO_REGISTER
-	       || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
+	       || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno))
-	       || usage_insns[regno].calls_num == calls_num)
 	   /* We need at least 2 reloads to make pseudo splitting
 	      profitable.  We should provide hard regno splitting in
 	      any case to solve 1st insn scheduling problem when
 	      moving hard register definition up might result in
 	      impossibility to find hard register for reload pseudo of
 /* Do split transformations for insn INSN, which defines or uses
 ORIGINAL_REGNO.  NEXT_USAGE_INSNS specifies which instruction in
 the EBB next uses ORIGINAL_REGNO; it has the same form as the
 "insns" field of usage_insns.  If TO is not NULL, we don't use
-usage_insns, we put restore insns after TO insn.
+usage_insns, we put restore insns after TO insn.  It is a case when
+we call it from lra_split_hard_reg_for, outside the inheritance
+pass.
 The transformations look like:
 p <- ...		  p <- ...
 ...		  s <- p    (new insn -- save)
 rematerializing the original value instead of spilling to the stack.  */
 if (!HARD_REGISTER_NUM_P (original_regno)
 && mode == PSEUDO_REGNO_MODE (original_regno))
 lra_copy_reg_equiv (new_regno, original_regno);
 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
-bitmap_set_bit (&check_only_regs, new_regno);
-bitmap_set_bit (&check_only_regs, original_regno);
 bitmap_set_bit (&lra_split_regs, new_regno);
 if (to != NULL)
 {
+lra_assert (next_usage_insns == NULL);
 usage_insn = to;
 after_p = TRUE;
 }
 else
 {
+/* We need check_only_regs only inside the inheritance pass.  */
+bitmap_set_bit (&check_only_regs, new_regno);
+bitmap_set_bit (&check_only_regs, original_regno);
 after_p = usage_insns[original_regno].after_p;
 for (;;)
 	{
 	  if (GET_CODE (next_usage_insns) != INSN_LIST)
 	    {
 /* If we are trying to split multi-register.  We should check
 conflicts on the next assignment sub-pass.  IRA can allocate on
 sub-register levels, LRA do this on pseudos level right now and
 this discrepancy may create allocation conflicts after
 splitting.  */
-lra_risky_transformations_p = true;
+check_and_force_assignment_correctness_p = true;
 if (lra_dump_file != NULL)
 fprintf (lra_dump_file,
 	     "	  ))))))))))))))))))))))))))))))))))))))))))))))))\n");
 return true;
 }
 {
 machine_mode mode;
 const char *fmt;
 enum rtx_code code;
 int i, j;
+if (side_effects_p (x))
+return false;
 code = GET_CODE (x);
 mode = GET_MODE (x);
 if (code == SUBREG)
 {
 change_p = false;
 curr_usage_insns_check++;
 clear_invariants ();
 reloads_num = calls_num = 0;
+for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
+last_call_for_abi[i] = 0;
+CLEAR_HARD_REG_SET (full_and_partial_call_clobbers);
 bitmap_clear (&check_only_regs);
 bitmap_clear (&invalid_invariant_regs);
 last_processed_bb = NULL;
 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
-COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
+live_hard_regs = eliminable_regset | lra_no_alloc_regs;
-IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
 /* We don't process new insns generated in the loop.	*/
 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
 {
 prev_insn = PREV_INSN (curr_insn);
 if (BLOCK_FOR_INSN (curr_insn) != NULL)
 	  if (succ_p)
 	    change_p = true;
 	  else
 	    setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
-	    IOR_HARD_REG_SET (potential_reload_hard_regs,
+	    potential_reload_hard_regs |= reg_class_contents[cl];
-			      reg_class_contents[cl]);
 	}
 else if (src_regno < 0
 	       && dst_regno >= lra_constraint_new_regno_start
 	       && invariant_p (SET_SRC (curr_set))
 	       && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
 	    reloads_num++;
 	  update_reloads_num_p = false;
 	  if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
 	    change_p = true;
 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
-	    IOR_HARD_REG_SET (potential_reload_hard_regs,
+	    potential_reload_hard_regs |= reg_class_contents[cl];
-			      reg_class_contents[cl]);
 	}
 else if (src_regno >= lra_constraint_new_regno_start
 	       && dst_regno < lra_constraint_new_regno_start
 	       && dst_regno >= FIRST_PSEUDO_REGISTER
 	       && reg_renumber[dst_regno] < 0
 				     curr_insn, next_usage_insns))
 	    change_p = true;
 	  /* Invalidate.  */
 	  usage_insns[dst_regno].check = 0;
 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
-	    IOR_HARD_REG_SET (potential_reload_hard_regs,
+	    potential_reload_hard_regs |= reg_class_contents[cl];
-			      reg_class_contents[cl]);
 	}
 else if (INSN_P (curr_insn))
 	{
 	  int iter;
 	  int max_uid = get_max_uid ();
 			if (r->type != OP_OUT && r->regno == dst_regno)
 			  break;
 		      /* Don't do inheritance if the pseudo is also
 			 used in the insn.  */
 		      if (r == NULL)
-			/* We can not do inheritance right now
+			/* We cannot do inheritance right now
 			   because the current insn reg info (chain
 			   regs) can change after that.  */
 			add_to_inherit (dst_regno, next_usage_insns);
 		    }
-		  /* We can not process one reg twice here because of
+		  /* We cannot process one reg twice here because of
 		     usage_insns invalidation.  */
 		  if ((dst_regno < FIRST_PSEUDO_REGISTER
 		       || reg_renumber[dst_regno] >= 0)
 		      && ! reg->subreg_p && reg->type != OP_IN)
 		    {
 		      if (dst_regno < FIRST_PSEUDO_REGISTER)
 			add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
 		      else
 			add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
 					     reg_renumber[dst_regno]);
-		      AND_COMPL_HARD_REG_SET (live_hard_regs, s);
+		      live_hard_regs &= ~s;
+		      potential_reload_hard_regs &= ~s;
 		    }
 		  /* We should invalidate potential inheritance or
 		     splitting for the current insn usages to the next
 		     usage insns (see code below) as the output pseudo
 		     prevents this.  */
 	      rtx cheap, pat, dest;
 	      rtx_insn *restore;
 	      int regno, hard_regno;
 	      calls_num++;
+	      function_abi callee_abi = insn_callee_abi (curr_insn);
+	      last_call_for_abi[callee_abi.id ()] = calls_num;
+	      full_and_partial_call_clobbers
+		|= callee_abi.full_and_partial_reg_clobbers ();
 	      if ((cheap = find_reg_note (curr_insn,
 					  REG_RETURNED, NULL_RTX)) != NULL_RTX
 		  && ((cheap = XEXP (cheap, 0)), true)
 		  && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
 		  && (hard_regno = reg_renumber[regno]) >= 0
 		  && usage_insns[regno].check == curr_usage_insns_check
 		  /* If there are pending saves/restores, the
 		     optimization is not worth.	 */
 		  && usage_insns[regno].calls_num == calls_num - 1
-		  && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
+		  && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno))
 		{
 		  /* Restore the pseudo from the call result as
 		     REG_RETURNED note says that the pseudo value is
 		     in the call result and the pseudo is an argument
 		     of the call.  */
 		      lra_process_new_insns (curr_insn, NULL, restore,
 					     "Inserting call parameter restore");
 		      /* We don't need to save/restore of the pseudo from
 			 this call.	 */
 		      usage_insns[regno].calls_num = calls_num;
+		      remove_from_hard_reg_set
+			(&full_and_partial_call_clobbers,
+			 GET_MODE (cheap), hard_regno);
 		      bitmap_set_bit (&check_only_regs, regno);
 		    }
 		}
 	    }
 	  to_inherit_num = 0;
 			  && split_if_necessary (src_regno, reg->biggest_mode,
 						 potential_reload_hard_regs,
 						 before_p, curr_insn, max_uid))
 			{
 			  if (reg->subreg_p)
-			    lra_risky_transformations_p = true;
+			    check_and_force_assignment_correctness_p = true;
 			  change_p = true;
 			  /* Invalidate. */
 			  usage_insns[src_regno].check = 0;
 			  if (before_p)
 			    use_insn = PREV_INSN (curr_insn);
 	          && (cl = lra_get_allocno_class (regno)) != NO_REGS))
 	    {
 	      if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
 		reloads_num++;
 	      if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
-		IOR_HARD_REG_SET (potential_reload_hard_regs,
+		potential_reload_hard_regs |= reg_class_contents[cl];
-	                          reg_class_contents[cl]);
 	    }
 	}
 if (NONDEBUG_INSN_P (curr_insn))
 	{
 	  int regno;
 /* This value affects EBB forming.  If probability of edge from EBB to
 a BB is not greater than the following value, we don't add the BB
 to EBB.  */
 #define EBB_PROBABILITY_CUTOFF \
-((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
+((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
 /* Current number of inheritance/split iteration.  */
 int lra_inheritance_iter;
 /* Entry function for inheritance/split pass.  */
 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
 	/* Remember that the EBB head and tail can change in
 	   inherit_in_ebb.  */
 	update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
 }
-bitmap_clear (&ebb_global_regs);
+bitmap_release (&ebb_global_regs);
-bitmap_clear (&temp_bitmap);
+bitmap_release (&temp_bitmap);
-bitmap_clear (&live_regs);
+bitmap_release (&live_regs);
-bitmap_clear (&invalid_invariant_regs);
+bitmap_release (&invalid_invariant_regs);
-bitmap_clear (&check_only_regs);
+bitmap_release (&check_only_regs);
 free (usage_insns);
 timevar_pop (TV_LRA_INHERITANCE);
 }
 rtx set, prev_set;
 rtx_insn *prev_insn;
 bool change_p, done_p;
 change_p = ! bitmap_empty_p (remove_pseudos);
-/* We can not finish the function right away if CHANGE_P is true
+/* We cannot finish the function right away if CHANGE_P is true
 because we need to marks insns affected by previous
 inheritance/split pass for processing by the subsequent
 constraint pass.  */
 FOR_EACH_BB_FN (bb, cfun)
 {
 	      else if (bitmap_bit_p (remove_pseudos, sregno)
 		       && ! REG_P (lra_reg_info[sregno].restore_rtx))
 		{
 		  /* reload pseudo <- invariant inheritance pseudo */
 		  start_sequence ();
-		  /* We can not just change the source.  It might be
+		  /* We cannot just change the source.  It might be
 		     an insn different from the move.  */
 		  emit_insn (lra_reg_info[sregno].restore_rtx);
 		  rtx_insn *new_insns = get_insns ();
 		  end_sequence ();
 		  lra_assert (single_set (new_insns) != NULL

Mercurial > hg > CbC > CbC_gcc

comparison gcc/lra-constraints.c @ 145:1830386684a0