Mercurial > hg > CbC > CbC_gcc
diff gcc/lra-constraints.c @ 145:1830386684a0
gcc-9.2.0
| author | anatofuz |
|---|---|
| date | Thu, 13 Feb 2020 11:34:05 +0900 |
| parents | 84e7813d76e9 |
| children |
line wrap: on
line diff
--- a/gcc/lra-constraints.c Thu Oct 25 07:37:49 2018 +0900 +++ b/gcc/lra-constraints.c Thu Feb 13 11:34:05 2020 +0900 @@ -1,5 +1,5 @@ /* Code for RTL transformations to satisfy insn constraints. - Copyright (C) 2010-2018 Free Software Foundation, Inc. + Copyright (C) 2010-2020 Free Software Foundation, Inc. Contributed by Vladimir Makarov <vmakarov@redhat.com>. This file is part of GCC. @@ -127,10 +127,10 @@ #include "expr.h" #include "cfgrtl.h" #include "rtl-error.h" -#include "params.h" #include "lra.h" #include "lra-int.h" #include "print-rtl.h" +#include "function-abi.h" /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted @@ -359,14 +359,20 @@ if (m_base_loc != NULL) { m_base_reg = *m_base_loc; - lra_eliminate_reg_if_possible (m_base_loc); + /* If we have non-legitimate address which is decomposed not in + the way we expected, don't do elimination here. In such case + the address will be reloaded and elimination will be done in + reload insn finally. */ + if (REG_P (m_base_reg)) + lra_eliminate_reg_if_possible (m_base_loc); if (m_ad->base_term2 != NULL) *m_ad->base_term2 = *m_ad->base_term; } if (m_index_loc != NULL) { m_index_reg = *m_index_loc; - lra_eliminate_reg_if_possible (m_index_loc); + if (REG_P (m_index_reg)) + lra_eliminate_reg_if_possible (m_index_loc); } } @@ -382,11 +388,24 @@ *m_index_loc = m_index_reg; } -/* Return true if the eliminated form of AD is a legitimate target address. */ +/* Return true if the eliminated form of AD is a legitimate target address. + If OP is a MEM, AD is the address within OP, otherwise OP should be + ignored. CONSTRAINT is one constraint that the operand may need + to meet. */ static bool -valid_address_p (struct address_info *ad) +valid_address_p (rtx op, struct address_info *ad, + enum constraint_num constraint) { address_eliminator eliminator (ad); + + /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more + forgiving than "m". */ + if (MEM_P (op) + && (insn_extra_memory_constraint (constraint) + || insn_extra_special_memory_constraint (constraint)) + && constraint_satisfied_p (op, constraint)) + return true; + return valid_address_p (ad->mode, *ad->outer, ad->as); } @@ -979,7 +998,7 @@ operand ("a"). "b" must then be copied into a new register so that it doesn't clobber the current value of "a". - We can not use the same value if the output pseudo is + We cannot use the same value if the output pseudo is early clobbered or the input pseudo is mentioned in the output, e.g. as an address part in memory, because output reload will actually extend the pseudo liveness. @@ -1035,12 +1054,15 @@ curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; for (i = 0; (in = ins[i]) >= 0; i++) - { - lra_assert - (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode - || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); + if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode + || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])) *curr_id->operand_loc[in] = new_in_reg; - } + else + { + lra_assert + (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in])); + *curr_id->operand_loc[in] = new_out_reg; + } lra_update_dups (curr_id, ins); if (out < 0) return; @@ -1491,10 +1513,11 @@ alter_subreg (curr_id->operand_loc[nop], false); rtx subst = *curr_id->operand_loc[nop]; lra_assert (MEM_P (subst)); - + const bool addr_is_valid = valid_address_p (GET_MODE (subst), + XEXP (subst, 0), + MEM_ADDR_SPACE (subst)); if (!addr_was_valid - || valid_address_p (GET_MODE (subst), XEXP (subst, 0), - MEM_ADDR_SPACE (subst)) + || addr_is_valid || ((get_constraint_type (lookup_constraint (curr_static_id->operand[nop].constraint)) != CT_SPECIAL_MEMORY) @@ -1523,12 +1546,20 @@ data into a register when the inner is narrower than outer or missing important data from memory when the inner is wider than outer. This rule only applies to modes that are no wider than - a word. */ - if (!(maybe_ne (GET_MODE_PRECISION (mode), - GET_MODE_PRECISION (innermode)) - && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) - && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) - && WORD_REGISTER_OPERATIONS) + a word. + + If valid memory becomes invalid after subreg elimination + and address might be different we still have to reload + memory. + */ + if ((! addr_was_valid + || addr_is_valid + || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) + && !(maybe_ne (GET_MODE_PRECISION (mode), + GET_MODE_PRECISION (innermode)) + && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) + && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) + && WORD_REGISTER_OPERATIONS) && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) @@ -1547,7 +1578,7 @@ enum reg_class rclass = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); if (get_reload_reg (curr_static_id->operand[nop].type, innermode, - reg, rclass, TRUE, "slow mem", &new_reg)) + reg, rclass, TRUE, "slow/invalid mem", &new_reg)) { bool insert_before, insert_after; bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); @@ -1566,7 +1597,7 @@ rclass = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, - rclass, TRUE, "slow mem", &new_reg)) + rclass, TRUE, "slow/invalid mem", &new_reg)) { bool insert_before, insert_after; bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); @@ -1579,7 +1610,7 @@ } *curr_id->operand_loc[nop] = new_reg; lra_process_new_insns (curr_insn, before, after, - "Inserting slow mem reload"); + "Inserting slow/invalid mem reload"); return true; } @@ -1755,14 +1786,24 @@ return false; code = GET_CODE (x); mode = GET_MODE (x); + if (code == SUBREG) { + /* For all SUBREGs we want to check whether the full multi-register + overlaps the set. For normal SUBREGs this means 'get_hard_regno' of + the inner register, for paradoxical SUBREGs this means the + 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is + fine. Use the wider mode for all cases. */ + rtx subreg = SUBREG_REG (x); mode = wider_subreg_mode (x); - x = SUBREG_REG (x); - code = GET_CODE (x); + if (mode == GET_MODE (subreg)) + { + x = subreg; + code = GET_CODE (x); + } } - if (REG_P (x)) + if (REG_P (x) || SUBREG_P (x)) { x_hard_regno = get_hard_regno (x, true); return (x_hard_regno >= 0 @@ -1829,8 +1870,7 @@ HARD_REG_SET temp; lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); - COPY_HARD_REG_SET (temp, set); - AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); + temp = set & ~lra_no_alloc_regs; return (hard_reg_set_subset_p (temp, ira_prohibited_class_mode_regs[rclass][mode])); } @@ -1841,11 +1881,12 @@ alternative. */ static unsigned int curr_small_class_check = 0; -/* Update number of used inputs of class OP_CLASS for operand NOP. - Return true if we have more such class operands than the number of - available regs. */ +/* Update number of used inputs of class OP_CLASS for operand NOP + of alternative NALT. Return true if we have more such class operands + than the number of available regs. */ static bool -update_and_check_small_class_inputs (int nop, enum reg_class op_class) +update_and_check_small_class_inputs (int nop, int nalt, + enum reg_class op_class) { static unsigned int small_class_check[LIM_REG_CLASSES]; static int small_class_input_nums[LIM_REG_CLASSES]; @@ -1856,7 +1897,7 @@ && hard_reg_set_intersect_p (reg_class_contents[op_class], ira_no_alloc_regs) && (curr_static_id->operand[nop].type != OP_OUT - || curr_static_id->operand[nop].early_clobber)) + || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt))) { if (small_class_check[op_class] == curr_small_class_check) small_class_input_nums[op_class]++; @@ -1874,7 +1915,7 @@ /* Major function to choose the current insn alternative and what operands should be reloaded and how. If ONLY_ALTERNATIVE is not negative we should consider only this alternative. Return false if - we can not choose the alternative or find how to reload the + we cannot choose the alternative or find how to reload the operands. */ static bool process_alt_operands (int only_alternative) @@ -2125,7 +2166,8 @@ /* We should reject matching of an early clobber operand if the matching operand is not dying in the insn. */ - if (! curr_static_id->operand[m].early_clobber + if (!TEST_BIT (curr_static_id->operand[m] + .early_clobber_alts, nalt) || operand_reg[nop] == NULL_RTX || (find_regno_note (curr_insn, REG_DEAD, REGNO (op)) @@ -2146,9 +2188,49 @@ } else { - /* Operands don't match. Both operands must - allow a reload register, otherwise we - cannot make them match. */ + /* If the operands do not match and one + operand is INOUT, we can not match them. + Try other possibilities, e.g. other + alternatives or commutative operand + exchange. */ + if (curr_static_id->operand[nop].type == OP_INOUT + || curr_static_id->operand[m].type == OP_INOUT) + break; + /* Operands don't match. If the operands are + different user defined explicit hard + registers, then we cannot make them match + when one is early clobber operand. */ + if ((REG_P (*curr_id->operand_loc[nop]) + || SUBREG_P (*curr_id->operand_loc[nop])) + && (REG_P (*curr_id->operand_loc[m]) + || SUBREG_P (*curr_id->operand_loc[m]))) + { + rtx nop_reg = *curr_id->operand_loc[nop]; + if (SUBREG_P (nop_reg)) + nop_reg = SUBREG_REG (nop_reg); + rtx m_reg = *curr_id->operand_loc[m]; + if (SUBREG_P (m_reg)) + m_reg = SUBREG_REG (m_reg); + + if (REG_P (nop_reg) + && HARD_REGISTER_P (nop_reg) + && REG_USERVAR_P (nop_reg) + && REG_P (m_reg) + && HARD_REGISTER_P (m_reg) + && REG_USERVAR_P (m_reg)) + { + int i; + + for (i = 0; i < early_clobbered_regs_num; i++) + if (m == early_clobbered_nops[i]) + break; + if (i < early_clobbered_regs_num + || early_clobber_p) + break; + } + } + /* Both operands must allow a reload register, + otherwise we cannot make them match. */ if (curr_alt[m] == NO_REGS) break; /* Retroactively mark the operand we had to @@ -2169,7 +2251,8 @@ it results in less hard regs required for the insn than a non-matching earlyclobber alternative. */ - if (curr_static_id->operand[m].early_clobber) + if (TEST_BIT (curr_static_id->operand[m] + .early_clobber_alts, nalt)) { if (lra_dump_file != NULL) fprintf @@ -2220,7 +2303,7 @@ reloads. */ badop = false; this_alternative = curr_alt[m]; - COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); + this_alternative_set = curr_alt_set[m]; winreg = this_alternative != NO_REGS; break; } @@ -2302,18 +2385,16 @@ break; reg: + if (mode == BLKmode) + break; this_alternative = reg_class_subunion[this_alternative][cl]; - IOR_HARD_REG_SET (this_alternative_set, - reg_class_contents[cl]); + this_alternative_set |= reg_class_contents[cl]; if (costly_p) { this_costly_alternative = reg_class_subunion[this_costly_alternative][cl]; - IOR_HARD_REG_SET (this_costly_alternative_set, - reg_class_contents[cl]); + this_costly_alternative_set |= reg_class_contents[cl]; } - if (mode == BLKmode) - break; winreg = true; if (REG_P (op)) { @@ -2447,14 +2528,11 @@ if (this_alternative != NO_REGS) { - HARD_REG_SET available_regs; - - COPY_HARD_REG_SET (available_regs, - reg_class_contents[this_alternative]); - AND_COMPL_HARD_REG_SET - (available_regs, - ira_prohibited_class_mode_regs[this_alternative][mode]); - AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); + HARD_REG_SET available_regs + = (reg_class_contents[this_alternative] + & ~((ira_prohibited_class_mode_regs + [this_alternative][mode]) + | lra_no_alloc_regs)); if (hard_reg_set_empty_p (available_regs)) { /* There are no hard regs holding a value of given @@ -2609,7 +2687,7 @@ goto fail; } - /* Alternative loses if it required class pseudo can not + /* Alternative loses if it required class pseudo cannot hold value of required mode. Such insns can be described by insn definitions with mode iterators. */ if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode @@ -2618,8 +2696,8 @@ class which does not have actually enough regs to hold the value (e.g. x86 AREG for mode requiring more one general reg). Therefore we have 2 - conditions to check that the reload pseudo can - not hold the mode value. */ + conditions to check that the reload pseudo cannot + hold the mode value. */ && (!targetm.hard_regno_mode_ok (ira_class_hard_regs[this_alternative][0], GET_MODE (*curr_id->operand_loc[nop]))) @@ -2633,7 +2711,7 @@ if (lra_dump_file != NULL) fprintf (lra_dump_file, " alt=%d: reload pseudo for op %d " - " can not hold the mode value -- refuse\n", + "cannot hold the mode value -- refuse\n", nalt, nop); goto fail; } @@ -2647,11 +2725,24 @@ && (targetm.preferred_output_reload_class (op, this_alternative) == NO_REGS)))) { - if (lra_dump_file != NULL) - fprintf (lra_dump_file, - " %d Non-prefered reload: reject+=%d\n", - nop, LRA_MAX_REJECT); - reject += LRA_MAX_REJECT; + if (offmemok && REG_P (op)) + { + if (lra_dump_file != NULL) + fprintf + (lra_dump_file, + " %d Spill pseudo into memory: reject+=3\n", + nop); + reject += 3; + } + else + { + if (lra_dump_file != NULL) + fprintf + (lra_dump_file, + " %d Non-prefered reload: reject+=%d\n", + nop, LRA_MAX_REJECT); + reject += LRA_MAX_REJECT; + } } if (! (MEM_P (op) && offmemok) @@ -2758,29 +2849,32 @@ (GET_MODE (op), this_alternative, cl))))) losers++; - /* Input reloads can be inherited more often than output - reloads can be removed, so penalize output - reloads. */ - if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) - { - if (lra_dump_file != NULL) - fprintf - (lra_dump_file, - " %d Non input pseudo reload: reject++\n", - nop); - reject++; - } - if (MEM_P (op) && offmemok) addr_losers++; - else if (curr_static_id->operand[nop].type == OP_INOUT) + else { - if (lra_dump_file != NULL) - fprintf - (lra_dump_file, - " %d Input/Output reload: reject+=%d\n", - nop, LRA_LOSER_COST_FACTOR); - reject += LRA_LOSER_COST_FACTOR; + /* Input reloads can be inherited more often than + output reloads can be removed, so penalize output + reloads. */ + if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) + { + if (lra_dump_file != NULL) + fprintf + (lra_dump_file, + " %d Non input pseudo reload: reject++\n", + nop); + reject++; + } + + if (curr_static_id->operand[nop].type == OP_INOUT) + { + if (lra_dump_file != NULL) + fprintf + (lra_dump_file, + " %d Input/Output reload: reject+=%d\n", + nop, LRA_LOSER_COST_FACTOR); + reject += LRA_LOSER_COST_FACTOR; + } } } @@ -2807,7 +2901,8 @@ goto fail; } - if (update_and_check_small_class_inputs (nop, this_alternative)) + if (update_and_check_small_class_inputs (nop, nalt, + this_alternative)) { if (lra_dump_file != NULL) fprintf (lra_dump_file, @@ -2816,7 +2911,7 @@ goto fail; } curr_alt[nop] = this_alternative; - COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); + curr_alt_set[nop] = this_alternative_set; curr_alt_win[nop] = this_alternative_win; curr_alt_match_win[nop] = this_alternative_match_win; curr_alt_offmemok[nop] = this_alternative_offmemok; @@ -2910,18 +3005,31 @@ if (first_conflict_j < 0) first_conflict_j = j; last_conflict_j = j; + /* Both the earlyclobber operand and conflicting operand + cannot both be user defined hard registers. */ + if (HARD_REGISTER_P (operand_reg[i]) + && REG_USERVAR_P (operand_reg[i]) + && operand_reg[j] != NULL_RTX + && HARD_REGISTER_P (operand_reg[j]) + && REG_USERVAR_P (operand_reg[j])) + fatal_insn ("unable to generate reloads for " + "impossible constraints:", curr_insn); } if (last_conflict_j < 0) continue; - /* If earlyclobber operand conflicts with another - non-matching operand which is actually the same register - as the earlyclobber operand, it is better to reload the - another operand as an operand matching the earlyclobber - operand can be also the same. */ - if (first_conflict_j == last_conflict_j - && operand_reg[last_conflict_j] != NULL_RTX - && ! curr_alt_match_win[last_conflict_j] - && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) + + /* If an earlyclobber operand conflicts with another non-matching + operand (ie, they have been assigned the same hard register), + then it is better to reload the other operand, as there may + exist yet another operand with a matching constraint associated + with the earlyclobber operand. However, if one of the operands + is an explicit use of a hard register, then we must reload the + other non-hard register operand. */ + if (HARD_REGISTER_P (operand_reg[i]) + || (first_conflict_j == last_conflict_j + && operand_reg[last_conflict_j] != NULL_RTX + && !curr_alt_match_win[last_conflict_j] + && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) { curr_alt_win[last_conflict_j] = false; curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] @@ -3318,7 +3426,7 @@ All these cases involve a non-autoinc address, so there is no point revalidating other types. */ - if (ad.autoinc_p || valid_address_p (&ad)) + if (ad.autoinc_p || valid_address_p (op, &ad, cn)) return change_p; /* Any index existed before LRA started, so we can assume that the @@ -3347,7 +3455,7 @@ if (code >= 0) { *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); - if (! valid_address_p (ad.mode, *ad.outer, ad.as)) + if (!valid_address_p (op, &ad, cn)) { /* Try to put lo_sum into register. */ insn = emit_insn (gen_rtx_SET @@ -3357,7 +3465,7 @@ if (code >= 0) { *ad.inner = new_reg; - if (! valid_address_p (ad.mode, *ad.outer, ad.as)) + if (!valid_address_p (op, &ad, cn)) { *ad.inner = addr; code = -1; @@ -3452,7 +3560,7 @@ && CONSTANT_P (XEXP (SET_SRC (set), 1))) { *ad.inner = SET_SRC (set); - if (valid_address_p (ad.mode, *ad.outer, ad.as)) + if (valid_address_p (op, &ad, cn)) { *ad.base_term = XEXP (SET_SRC (set), 0); *ad.disp_term = XEXP (SET_SRC (set), 1); @@ -3898,6 +4006,7 @@ fatal_insn ("unable to generate reloads for:", curr_insn); error_for_asm (curr_insn, "inconsistent operand constraints in an %<asm%>"); + lra_asm_error_p = true; /* Avoid further trouble with this insn. Don't generate use pattern here as we could use the insn SP offset. */ lra_set_insn_deleted (curr_insn); @@ -3965,7 +4074,7 @@ if (sec_mode != rld_mode) { /* If the target says specifically to use another mode for - secondary memory moves we can not reuse the original + secondary memory moves we cannot reuse the original insn. */ after = emit_spill_move (false, new_reg, dest); lra_process_new_insns (curr_insn, NULL, after, @@ -4191,6 +4300,32 @@ || MEM_P (SET_DEST (curr_insn_set)) || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) optional_p = true; + else if (goal_alt_matched[i][0] != -1 + && curr_static_id->operand[i].type == OP_OUT + && (curr_static_id->operand_alternative + [goal_alt_number * n_operands + i].earlyclobber) + && REG_P (op)) + { + for (j = 0; goal_alt_matched[i][j] != -1; j++) + { + rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; + + if (REG_P (op2) && REGNO (op) != REGNO (op2)) + break; + } + if (goal_alt_matched[i][j] != -1) + { + /* Generate reloads for different output and matched + input registers. This is the easiest way to avoid + creation of non-existing register conflicts in + lra-lives.c. */ + match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, + &after, TRUE); + outputs[n_outputs++] = i; + outputs[n_outputs] = -1; + } + continue; + } else continue; } @@ -4448,7 +4583,7 @@ regno = lra_get_regno_hard_regno (regno); if (regno < 0) return false; - COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); + alloc_regs = ~lra_no_alloc_regs; return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); } else @@ -4546,11 +4681,14 @@ /* The current iteration number of this LRA pass. */ int lra_constraint_iter; -/* True if we substituted equiv which needs checking register - allocation correctness because the equivalent value contains - allocatable hard registers or when we restore multi-register - pseudo. */ -bool lra_risky_transformations_p; +/* True if we should during assignment sub-pass check assignment + correctness for all pseudos and spill some of them to correct + conflicts. It can be necessary when we substitute equiv which + needs checking register allocation correctness because the + equivalent value contains allocatable hard registers, or when we + restore multi-register pseudo, or when we change the insn code and + its operand became INOUT operand when it was IN one before. */ +bool check_and_force_assignment_correctness_p; /* Return true if REGNO is referenced in more than one block. */ static bool @@ -4692,12 +4830,14 @@ changed_p = false; if (pic_offset_table_rtx && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) - lra_risky_transformations_p = true; - else + check_and_force_assignment_correctness_p = true; + else if (first_p) /* On the first iteration we should check IRA assignment correctness. In rare cases, the assignments can be wrong as - early clobbers operands are ignored in IRA. */ - lra_risky_transformations_p = first_p; + early clobbers operands are ignored in IRA or usages of + paradoxical sub-registers are not taken into account by + IRA. */ + check_and_force_assignment_correctness_p = true; new_insn_uid_start = get_max_uid (); new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); /* Mark used hard regs for target stack size calulations. */ @@ -4724,7 +4864,7 @@ { bool pseudo_p = contains_reg_p (x, false, false); - /* After RTL transformation, we can not guarantee that + /* After RTL transformation, we cannot guarantee that pseudo in the substitution was not reloaded which might make equivalence invalid. For example, in reverse equiv of p0 @@ -4757,7 +4897,7 @@ || (! reverse_equiv_p (i) && (init_insn_rhs_dead_pseudo_p (i) /* If we reloaded the pseudo in an equivalence - init insn, we can not remove the equiv init + init insn, we cannot remove the equiv init insns and the init insns might write into const memory in this case. */ || contains_reloaded_insn_p (i))) @@ -4805,7 +4945,7 @@ } if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) internal_error - ("Max. number of generated reload insns per insn is achieved (%d)\n", + ("maximum number of generated reload insns per insn achieved (%d)", MAX_RELOAD_INSNS_NUMBER); new_insns_num++; if (DEBUG_INSN_P (curr_insn)) @@ -4839,7 +4979,7 @@ if ((REG_P (dest_reg) && (x = get_equiv (dest_reg)) != dest_reg /* Remove insns which set up a pseudo whose value - can not be changed. Such insns might be not in + cannot be changed. Such insns might be not in init_insns because we don't update equiv data during insn transformations. @@ -4873,7 +5013,7 @@ dump_insn_slim (lra_dump_file, curr_insn); } if (contains_reg_p (x, true, false)) - lra_risky_transformations_p = true; + check_and_force_assignment_correctness_p = true; lra_set_insn_deleted (curr_insn); continue; } @@ -5038,6 +5178,14 @@ /* Number of calls passed so far in current EBB. */ static int calls_num; +/* Index ID is the CALLS_NUM associated the last call we saw with + ABI identifier ID. */ +static int last_call_for_abi[NUM_ABI_IDS]; + +/* Which registers have been fully or partially clobbered by a call + since they were last used. */ +static HARD_REG_SET full_and_partial_call_clobbers; + /* Current reload pseudo check for validity of elements in USAGE_INSNS. */ static int curr_usage_insns_check; @@ -5081,6 +5229,10 @@ usage_insns[regno].reloads_num = reloads_num; usage_insns[regno].calls_num = calls_num; usage_insns[regno].after_p = after_p; + if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) + remove_from_hard_reg_set (&full_and_partial_call_clobbers, + PSEUDO_REGNO_MODE (regno), + reg_renumber[regno]); } /* The function is used to form list REGNO usages which consists of @@ -5152,7 +5304,7 @@ (inheritance/split pseudos and original registers). */ static bitmap_head check_only_regs; -/* Reload pseudos can not be involded in invariant inheritance in the +/* Reload pseudos cannot be involded in invariant inheritance in the current EBB. */ static bitmap_head invalid_invariant_regs; @@ -5326,15 +5478,19 @@ need_for_call_save_p (int regno) { lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); - return (usage_insns[regno].calls_num < calls_num - && (overlaps_hard_reg_set_p - ((flag_ipa_ra && - ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) - ? lra_reg_info[regno].actual_call_used_reg_set - : call_used_reg_set, - PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) - || (targetm.hard_regno_call_part_clobbered - (reg_renumber[regno], PSEUDO_REGNO_MODE (regno))))); + if (usage_insns[regno].calls_num < calls_num) + { + unsigned int abis = 0; + for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) + if (last_call_for_abi[i] > usage_insns[regno].calls_num) + abis |= 1 << i; + gcc_assert (abis); + if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers, + PSEUDO_REGNO_MODE (regno), + reg_renumber[regno])) + return true; + } + return false; } /* Global registers occurring in the current EBB. */ @@ -5370,12 +5526,11 @@ /* Don't split call clobbered hard regs living through calls, otherwise we might have a check problem in the assign sub-pass as in the most cases (exception is a - situation when lra_risky_transformations_p value is + situation when check_and_force_assignment_correctness_p value is true) the assign pass assumes that all pseudos living through calls are assigned to call saved hard regs. */ && (regno >= FIRST_PSEUDO_REGISTER - || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) - || usage_insns[regno].calls_num == calls_num) + || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno)) /* We need at least 2 reloads to make pseudo splitting profitable. We should provide hard regno splitting in any case to solve 1st insn scheduling problem when @@ -5454,7 +5609,9 @@ ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in the EBB next uses ORIGINAL_REGNO; it has the same form as the "insns" field of usage_insns. If TO is not NULL, we don't use - usage_insns, we put restore insns after TO insn. + usage_insns, we put restore insns after TO insn. It is a case when + we call it from lra_split_hard_reg_for, outside the inheritance + pass. The transformations look like: @@ -5610,16 +5767,18 @@ && mode == PSEUDO_REGNO_MODE (original_regno)) lra_copy_reg_equiv (new_regno, original_regno); lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; - bitmap_set_bit (&check_only_regs, new_regno); - bitmap_set_bit (&check_only_regs, original_regno); bitmap_set_bit (&lra_split_regs, new_regno); if (to != NULL) { + lra_assert (next_usage_insns == NULL); usage_insn = to; after_p = TRUE; } else { + /* We need check_only_regs only inside the inheritance pass. */ + bitmap_set_bit (&check_only_regs, new_regno); + bitmap_set_bit (&check_only_regs, original_regno); after_p = usage_insns[original_regno].after_p; for (;;) { @@ -5659,7 +5818,7 @@ sub-register levels, LRA do this on pseudos level right now and this discrepancy may create allocation conflicts after splitting. */ - lra_risky_transformations_p = true; + check_and_force_assignment_correctness_p = true; if (lra_dump_file != NULL) fprintf (lra_dump_file, " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); @@ -5767,6 +5926,9 @@ enum rtx_code code; int i, j; + if (side_effects_p (x)) + return false; + code = GET_CODE (x); mode = GET_MODE (x); if (code == SUBREG) @@ -6120,12 +6282,14 @@ curr_usage_insns_check++; clear_invariants (); reloads_num = calls_num = 0; + for (unsigned int i = 0; i < NUM_ABI_IDS; ++i) + last_call_for_abi[i] = 0; + CLEAR_HARD_REG_SET (full_and_partial_call_clobbers); bitmap_clear (&check_only_regs); bitmap_clear (&invalid_invariant_regs); last_processed_bb = NULL; CLEAR_HARD_REG_SET (potential_reload_hard_regs); - COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); - IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); + live_hard_regs = eliminable_regset | lra_no_alloc_regs; /* We don't process new insns generated in the loop. */ for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) { @@ -6195,8 +6359,7 @@ else setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) - IOR_HARD_REG_SET (potential_reload_hard_regs, - reg_class_contents[cl]); + potential_reload_hard_regs |= reg_class_contents[cl]; } else if (src_regno < 0 && dst_regno >= lra_constraint_new_regno_start @@ -6213,8 +6376,7 @@ if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) change_p = true; if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) - IOR_HARD_REG_SET (potential_reload_hard_regs, - reg_class_contents[cl]); + potential_reload_hard_regs |= reg_class_contents[cl]; } else if (src_regno >= lra_constraint_new_regno_start && dst_regno < lra_constraint_new_regno_start @@ -6236,8 +6398,7 @@ /* Invalidate. */ usage_insns[dst_regno].check = 0; if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) - IOR_HARD_REG_SET (potential_reload_hard_regs, - reg_class_contents[cl]); + potential_reload_hard_regs |= reg_class_contents[cl]; } else if (INSN_P (curr_insn)) { @@ -6269,12 +6430,12 @@ /* Don't do inheritance if the pseudo is also used in the insn. */ if (r == NULL) - /* We can not do inheritance right now + /* We cannot do inheritance right now because the current insn reg info (chain regs) can change after that. */ add_to_inherit (dst_regno, next_usage_insns); } - /* We can not process one reg twice here because of + /* We cannot process one reg twice here because of usage_insns invalidation. */ if ((dst_regno < FIRST_PSEUDO_REGISTER || reg_renumber[dst_regno] >= 0) @@ -6292,7 +6453,8 @@ else add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), reg_renumber[dst_regno]); - AND_COMPL_HARD_REG_SET (live_hard_regs, s); + live_hard_regs &= ~s; + potential_reload_hard_regs &= ~s; } /* We should invalidate potential inheritance or splitting for the current insn usages to the next @@ -6336,6 +6498,10 @@ int regno, hard_regno; calls_num++; + function_abi callee_abi = insn_callee_abi (curr_insn); + last_call_for_abi[callee_abi.id ()] = calls_num; + full_and_partial_call_clobbers + |= callee_abi.full_and_partial_reg_clobbers (); if ((cheap = find_reg_note (curr_insn, REG_RETURNED, NULL_RTX)) != NULL_RTX && ((cheap = XEXP (cheap, 0)), true) @@ -6345,7 +6511,7 @@ /* If there are pending saves/restores, the optimization is not worth. */ && usage_insns[regno].calls_num == calls_num - 1 - && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) + && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno)) { /* Restore the pseudo from the call result as REG_RETURNED note says that the pseudo value is @@ -6368,6 +6534,9 @@ /* We don't need to save/restore of the pseudo from this call. */ usage_insns[regno].calls_num = calls_num; + remove_from_hard_reg_set + (&full_and_partial_call_clobbers, + GET_MODE (cheap), hard_regno); bitmap_set_bit (&check_only_regs, regno); } } @@ -6411,7 +6580,7 @@ before_p, curr_insn, max_uid)) { if (reg->subreg_p) - lra_risky_transformations_p = true; + check_and_force_assignment_correctness_p = true; change_p = true; /* Invalidate. */ usage_insns[src_regno].check = 0; @@ -6471,8 +6640,7 @@ if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) reloads_num++; if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) - IOR_HARD_REG_SET (potential_reload_hard_regs, - reg_class_contents[cl]); + potential_reload_hard_regs |= reg_class_contents[cl]; } } if (NONDEBUG_INSN_P (curr_insn)) @@ -6545,7 +6713,7 @@ a BB is not greater than the following value, we don't add the BB to EBB. */ #define EBB_PROBABILITY_CUTOFF \ - ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) + ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100) /* Current number of inheritance/split iteration. */ int lra_inheritance_iter; @@ -6605,11 +6773,11 @@ inherit_in_ebb. */ update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); } - bitmap_clear (&ebb_global_regs); - bitmap_clear (&temp_bitmap); - bitmap_clear (&live_regs); - bitmap_clear (&invalid_invariant_regs); - bitmap_clear (&check_only_regs); + bitmap_release (&ebb_global_regs); + bitmap_release (&temp_bitmap); + bitmap_release (&live_regs); + bitmap_release (&invalid_invariant_regs); + bitmap_release (&check_only_regs); free (usage_insns); timevar_pop (TV_LRA_INHERITANCE); @@ -6694,7 +6862,7 @@ bool change_p, done_p; change_p = ! bitmap_empty_p (remove_pseudos); - /* We can not finish the function right away if CHANGE_P is true + /* We cannot finish the function right away if CHANGE_P is true because we need to marks insns affected by previous inheritance/split pass for processing by the subsequent constraint pass. */ @@ -6735,7 +6903,7 @@ { /* reload pseudo <- invariant inheritance pseudo */ start_sequence (); - /* We can not just change the source. It might be + /* We cannot just change the source. It might be an insn different from the move. */ emit_insn (lra_reg_info[sregno].restore_rtx); rtx_insn *new_insns = get_insns ();