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comparison gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c @ 152:2b5abeee2509

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update gcc11
author anatofuz
date Mon, 25 May 2020 07:50:57 +0900
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145:1830386684a0 152:2b5abeee2509
1 /* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
2
3 /* shorten_memrefs should rewrite these load/stores into a compressible
4 format. */
5
6 void
7 store1a (int *array, int a)
8 {
9 array[200] = a;
10 array[201] = a;
11 array[202] = a;
12 array[203] = a;
13 }
14
15 void
16 store2a (long long *array, long long a)
17 {
18 array[200] = a;
19 array[201] = a;
20 array[202] = a;
21 array[203] = a;
22 }
23
24 int
25 load1r (int *array)
26 {
27 int a = 0;
28 a += array[200];
29 a += array[201];
30 a += array[202];
31 a += array[203];
32 return a;
33 }
34
35 long long
36 load2r (long long *array)
37 {
38 int a = 0;
39 a += array[200];
40 a += array[201];
41 a += array[202];
42 a += array[203];
43 return a;
44 }
45
46 /* { dg-final { scan-assembler "store1a:\n\taddi" } } */
47 /* The sd insns in store2a are not rewritten because shorten_memrefs currently
48 only optimizes lw and sw.
49 /* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */
50 /* { dg-final { scan-assembler "load1r:\n\taddi" } } */
51 /* The ld insns in load2r are not rewritten because shorten_memrefs currently
52 only optimizes lw and sw.
53 /* { dg-final { scan-assembler "load2r:\n\taddi" { xfail riscv*-*-* } } } */