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152
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1 /* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
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2
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3 /* shorten_memrefs should rewrite these load/stores into a compressible
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4 format. */
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5
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6 void
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7 store1a (int *array, int a)
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8 {
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9 array[200] = a;
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10 array[201] = a;
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11 array[202] = a;
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12 array[203] = a;
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13 }
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14
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15 void
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16 store2a (long long *array, long long a)
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17 {
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18 array[200] = a;
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19 array[201] = a;
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20 array[202] = a;
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21 array[203] = a;
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22 }
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23
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24 int
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25 load1r (int *array)
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26 {
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27 int a = 0;
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28 a += array[200];
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29 a += array[201];
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30 a += array[202];
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31 a += array[203];
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32 return a;
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33 }
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34
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35 long long
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36 load2r (long long *array)
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37 {
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38 int a = 0;
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39 a += array[200];
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40 a += array[201];
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41 a += array[202];
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42 a += array[203];
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43 return a;
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44 }
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45
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46 /* { dg-final { scan-assembler "store1a:\n\taddi" } } */
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47 /* The sd insns in store2a are not rewritten because shorten_memrefs currently
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48 only optimizes lw and sw.
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49 /* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */
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50 /* { dg-final { scan-assembler "load1r:\n\taddi" } } */
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51 /* The ld insns in load2r are not rewritten because shorten_memrefs currently
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52 only optimizes lw and sw.
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53 /* { dg-final { scan-assembler "load2r:\n\taddi" { xfail riscv*-*-* } } } */
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