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comparison gcc/config/arm/vfp.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
49 ;; SImode moves 49 ;; SImode moves
50 ;; ??? For now do not allow loading constants into vfp regs. This causes 50 ;; ??? For now do not allow loading constants into vfp regs. This causes
51 ;; problems because small constants get converted into adds. 51 ;; problems because small constants get converted into adds.
52 (define_insn "*arm_movsi_vfp" 52 (define_insn "*arm_movsi_vfp"
53 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv") 53 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
54 (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))] 54 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
55 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT 55 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
56 && ( s_register_operand (operands[0], SImode) 56 && ( s_register_operand (operands[0], SImode)
57 || s_register_operand (operands[1], SImode))" 57 || s_register_operand (operands[1], SImode))"
58 "* 58 "*
59 switch (which_alternative) 59 switch (which_alternative)
86 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] 86 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
87 ) 87 )
88 88
89 (define_insn "*thumb2_movsi_vfp" 89 (define_insn "*thumb2_movsi_vfp"
90 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv") 90 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
91 (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))] 91 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
92 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT 92 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
93 && ( s_register_operand (operands[0], SImode) 93 && ( s_register_operand (operands[0], SImode)
94 || s_register_operand (operands[1], SImode))" 94 || s_register_operand (operands[1], SImode))"
95 "* 95 "*
96 switch (which_alternative) 96 switch (which_alternative)
143 case 3: 143 case 3:
144 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; 144 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
145 case 4: 145 case 4:
146 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; 146 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
147 case 5: 147 case 5:
148 return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; 148 if (TARGET_VFP_SINGLE)
149 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
150 else
151 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
149 case 6: case 7: 152 case 6: case 7:
150 return output_move_vfp (operands); 153 return output_move_vfp (operands);
151 default: 154 default:
152 gcc_unreachable (); 155 gcc_unreachable ();
153 } 156 }
154 " 157 "
155 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") 158 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
156 (set_attr "length" "8,8,8,4,4,4,4,4") 159 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
160 (eq_attr "alternative" "5")
161 (if_then_else
162 (eq (symbol_ref "TARGET_VFP_SINGLE")
163 (const_int 1))
164 (const_int 8)
165 (const_int 4))]
166 (const_int 4)))
167 (set_attr "predicable" "yes")
157 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") 168 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
158 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] 169 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
159 ) 170 )
160 171
161 (define_insn "*thumb2_movdi_vfp" 172 (define_insn "*thumb2_movdi_vfp"
170 case 3: 181 case 3:
171 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; 182 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
172 case 4: 183 case 4:
173 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; 184 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
174 case 5: 185 case 5:
175 return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; 186 if (TARGET_VFP_SINGLE)
187 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
188 else
189 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
176 case 6: case 7: 190 case 6: case 7:
177 return output_move_vfp (operands); 191 return output_move_vfp (operands);
178 default: 192 default:
179 abort (); 193 abort ();
180 } 194 }
181 " 195 "
182 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store") 196 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
183 (set_attr "length" "8,8,8,4,4,4,4,4") 197 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
198 (eq_attr "alternative" "5")
199 (if_then_else
200 (eq (symbol_ref "TARGET_VFP_SINGLE")
201 (const_int 1))
202 (const_int 8)
203 (const_int 4))]
204 (const_int 4)))
184 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*") 205 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*")
185 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")] 206 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")]
207 )
208
209 ;; HFmode moves
210 (define_insn "*movhf_vfp_neon"
211 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
212 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
213 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
214 && ( s_register_operand (operands[0], HFmode)
215 || s_register_operand (operands[1], HFmode))"
216 "*
217 switch (which_alternative)
218 {
219 case 0: /* S register from memory */
220 return \"vld1.16\\t{%z0}, %A1\";
221 case 1: /* memory from S register */
222 return \"vst1.16\\t{%z1}, %A0\";
223 case 2: /* ARM register from memory */
224 return \"ldrh\\t%0, %1\\t%@ __fp16\";
225 case 3: /* memory from ARM register */
226 return \"strh\\t%1, %0\\t%@ __fp16\";
227 case 4: /* S register from S register */
228 return \"fcpys\\t%0, %1\";
229 case 5: /* ARM register from ARM register */
230 return \"mov\\t%0, %1\\t%@ __fp16\";
231 case 6: /* S register from ARM register */
232 return \"fmsr\\t%0, %1\";
233 case 7: /* ARM register from S register */
234 return \"fmrs\\t%0, %1\";
235 case 8: /* ARM register from constant */
236 {
237 REAL_VALUE_TYPE r;
238 long bits;
239 rtx ops[4];
240
241 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
242 bits = real_to_target (NULL, &r, HFmode);
243 ops[0] = operands[0];
244 ops[1] = GEN_INT (bits);
245 ops[2] = GEN_INT (bits & 0xff00);
246 ops[3] = GEN_INT (bits & 0x00ff);
247
248 if (arm_arch_thumb2)
249 output_asm_insn (\"movw\\t%0, %1\", ops);
250 else
251 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
252 return \"\";
253 }
254 default:
255 gcc_unreachable ();
256 }
257 "
258 [(set_attr "conds" "unconditional")
259 (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
260 (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
261 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
262 )
263
264 ;; FP16 without element load/store instructions.
265 (define_insn "*movhf_vfp"
266 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
267 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
268 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
269 && ( s_register_operand (operands[0], HFmode)
270 || s_register_operand (operands[1], HFmode))"
271 "*
272 switch (which_alternative)
273 {
274 case 0: /* ARM register from memory */
275 return \"ldrh\\t%0, %1\\t%@ __fp16\";
276 case 1: /* memory from ARM register */
277 return \"strh\\t%1, %0\\t%@ __fp16\";
278 case 2: /* S register from S register */
279 return \"fcpys\\t%0, %1\";
280 case 3: /* ARM register from ARM register */
281 return \"mov\\t%0, %1\\t%@ __fp16\";
282 case 4: /* S register from ARM register */
283 return \"fmsr\\t%0, %1\";
284 case 5: /* ARM register from S register */
285 return \"fmrs\\t%0, %1\";
286 case 6: /* ARM register from constant */
287 {
288 REAL_VALUE_TYPE r;
289 long bits;
290 rtx ops[4];
291
292 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
293 bits = real_to_target (NULL, &r, HFmode);
294 ops[0] = operands[0];
295 ops[1] = GEN_INT (bits);
296 ops[2] = GEN_INT (bits & 0xff00);
297 ops[3] = GEN_INT (bits & 0x00ff);
298
299 if (arm_arch_thumb2)
300 output_asm_insn (\"movw\\t%0, %1\", ops);
301 else
302 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
303 return \"\";
304 }
305 default:
306 gcc_unreachable ();
307 }
308 "
309 [(set_attr "conds" "unconditional")
310 (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
311 (set_attr "length" "4,4,4,4,4,4,8")]
186 ) 312 )
187 313
188 314
189 ;; SFmode moves 315 ;; SFmode moves
190 ;; Disparage the w<->r cases because reloading an invalid address is 316 ;; Disparage the w<->r cases because reloading an invalid address is
265 391
266 ;; DFmode moves 392 ;; DFmode moves
267 393
268 (define_insn "*movdf_vfp" 394 (define_insn "*movdf_vfp"
269 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") 395 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
270 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))] 396 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
271 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP 397 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
272 && ( register_operand (operands[0], DFmode) 398 && ( register_operand (operands[0], DFmode)
273 || register_operand (operands[1], DFmode))" 399 || register_operand (operands[1], DFmode))"
274 "* 400 "*
275 { 401 {
278 case 0: 404 case 0:
279 return \"fmdrr%?\\t%P0, %Q1, %R1\"; 405 return \"fmdrr%?\\t%P0, %Q1, %R1\";
280 case 1: 406 case 1:
281 return \"fmrrd%?\\t%Q0, %R0, %P1\"; 407 return \"fmrrd%?\\t%Q0, %R0, %P1\";
282 case 2: 408 case 2:
409 gcc_assert (TARGET_VFP_DOUBLE);
283 return \"fconstd%?\\t%P0, #%G1\"; 410 return \"fconstd%?\\t%P0, #%G1\";
284 case 3: case 4: 411 case 3: case 4:
285 return output_move_double (operands); 412 return output_move_double (operands);
286 case 5: case 6: 413 case 5: case 6:
287 return output_move_vfp (operands); 414 return output_move_vfp (operands);
288 case 7: 415 case 7:
289 return \"fcpyd%?\\t%P0, %P1\"; 416 if (TARGET_VFP_SINGLE)
417 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
418 else
419 return \"fcpyd%?\\t%P0, %P1\";
290 case 8: 420 case 8:
291 return \"#\"; 421 return \"#\";
292 default: 422 default:
293 gcc_unreachable (); 423 gcc_unreachable ();
294 } 424 }
295 } 425 }
296 " 426 "
297 [(set_attr "type" 427 [(set_attr "type"
298 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") 428 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
299 (set_attr "length" "4,4,4,8,8,4,4,4,8") 429 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
430 (eq_attr "alternative" "7")
431 (if_then_else
432 (eq (symbol_ref "TARGET_VFP_SINGLE")
433 (const_int 1))
434 (const_int 8)
435 (const_int 4))]
436 (const_int 4)))
437 (set_attr "predicable" "yes")
300 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*") 438 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
301 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")] 439 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
302 ) 440 )
303 441
304 (define_insn "*thumb2_movdf_vfp" 442 (define_insn "*thumb2_movdf_vfp"
305 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") 443 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
306 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))] 444 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
307 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" 445 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
308 "* 446 "*
309 { 447 {
310 switch (which_alternative) 448 switch (which_alternative)
311 { 449 {
312 case 0: 450 case 0:
313 return \"fmdrr%?\\t%P0, %Q1, %R1\"; 451 return \"fmdrr%?\\t%P0, %Q1, %R1\";
314 case 1: 452 case 1:
315 return \"fmrrd%?\\t%Q0, %R0, %P1\"; 453 return \"fmrrd%?\\t%Q0, %R0, %P1\";
316 case 2: 454 case 2:
455 gcc_assert (TARGET_VFP_DOUBLE);
317 return \"fconstd%?\\t%P0, #%G1\"; 456 return \"fconstd%?\\t%P0, #%G1\";
318 case 3: case 4: case 8: 457 case 3: case 4: case 8:
319 return output_move_double (operands); 458 return output_move_double (operands);
320 case 5: case 6: 459 case 5: case 6:
321 return output_move_vfp (operands); 460 return output_move_vfp (operands);
322 case 7: 461 case 7:
323 return \"fcpyd%?\\t%P0, %P1\"; 462 if (TARGET_VFP_SINGLE)
463 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
464 else
465 return \"fcpyd%?\\t%P0, %P1\";
324 default: 466 default:
325 abort (); 467 abort ();
326 } 468 }
327 } 469 }
328 " 470 "
329 [(set_attr "type" 471 [(set_attr "type"
330 "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") 472 "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
331 (set_attr "length" "4,4,4,8,8,4,4,4,8") 473 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
474 (eq_attr "alternative" "7")
475 (if_then_else
476 (eq (symbol_ref "TARGET_VFP_SINGLE")
477 (const_int 1))
478 (const_int 8)
479 (const_int 4))]
480 (const_int 4)))
332 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*") 481 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
333 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")] 482 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
334 ) 483 )
335 484
336 485
387 (if_then_else:DF 536 (if_then_else:DF
388 (match_operator 3 "arm_comparison_operator" 537 (match_operator 3 "arm_comparison_operator"
389 [(match_operand 4 "cc_register" "") (const_int 0)]) 538 [(match_operand 4 "cc_register" "") (const_int 0)])
390 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") 539 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
391 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] 540 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
392 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP" 541 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
393 "@ 542 "@
394 fcpyd%D3\\t%P0, %P2 543 fcpyd%D3\\t%P0, %P2
395 fcpyd%d3\\t%P0, %P1 544 fcpyd%d3\\t%P0, %P1
396 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 545 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
397 fmdrr%D3\\t%P0, %Q2, %R2 546 fmdrr%D3\\t%P0, %Q2, %R2
410 (if_then_else:DF 559 (if_then_else:DF
411 (match_operator 3 "arm_comparison_operator" 560 (match_operator 3 "arm_comparison_operator"
412 [(match_operand 4 "cc_register" "") (const_int 0)]) 561 [(match_operand 4 "cc_register" "") (const_int 0)])
413 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") 562 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
414 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] 563 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
415 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" 564 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
416 "@ 565 "@
417 it\\t%D3\;fcpyd%D3\\t%P0, %P2 566 it\\t%D3\;fcpyd%D3\\t%P0, %P2
418 it\\t%d3\;fcpyd%d3\\t%P0, %P1 567 it\\t%d3\;fcpyd%d3\\t%P0, %P1
419 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1 568 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
420 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2 569 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
441 ) 590 )
442 591
443 (define_insn "*absdf2_vfp" 592 (define_insn "*absdf2_vfp"
444 [(set (match_operand:DF 0 "s_register_operand" "=w") 593 [(set (match_operand:DF 0 "s_register_operand" "=w")
445 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] 594 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
446 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 595 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
447 "fabsd%?\\t%P0, %P1" 596 "fabsd%?\\t%P0, %P1"
448 [(set_attr "predicable" "yes") 597 [(set_attr "predicable" "yes")
449 (set_attr "type" "ffarithd")] 598 (set_attr "type" "ffarithd")]
450 ) 599 )
451 600
461 ) 610 )
462 611
463 (define_insn_and_split "*negdf2_vfp" 612 (define_insn_and_split "*negdf2_vfp"
464 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r") 613 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
465 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))] 614 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
466 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 615 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
467 "@ 616 "@
468 fnegd%?\\t%P0, %P1 617 fnegd%?\\t%P0, %P1
469 # 618 #
470 #" 619 #"
471 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed 620 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
472 && arm_general_register_operand (operands[0], DFmode)" 621 && arm_general_register_operand (operands[0], DFmode)"
473 [(set (match_dup 0) (match_dup 1))] 622 [(set (match_dup 0) (match_dup 1))]
474 " 623 "
475 if (REGNO (operands[0]) == REGNO (operands[1])) 624 if (REGNO (operands[0]) == REGNO (operands[1]))
476 { 625 {
521 670
522 (define_insn "*adddf3_vfp" 671 (define_insn "*adddf3_vfp"
523 [(set (match_operand:DF 0 "s_register_operand" "=w") 672 [(set (match_operand:DF 0 "s_register_operand" "=w")
524 (plus:DF (match_operand:DF 1 "s_register_operand" "w") 673 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
525 (match_operand:DF 2 "s_register_operand" "w")))] 674 (match_operand:DF 2 "s_register_operand" "w")))]
526 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 675 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
527 "faddd%?\\t%P0, %P1, %P2" 676 "faddd%?\\t%P0, %P1, %P2"
528 [(set_attr "predicable" "yes") 677 [(set_attr "predicable" "yes")
529 (set_attr "type" "faddd")] 678 (set_attr "type" "faddd")]
530 ) 679 )
531 680
542 691
543 (define_insn "*subdf3_vfp" 692 (define_insn "*subdf3_vfp"
544 [(set (match_operand:DF 0 "s_register_operand" "=w") 693 [(set (match_operand:DF 0 "s_register_operand" "=w")
545 (minus:DF (match_operand:DF 1 "s_register_operand" "w") 694 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
546 (match_operand:DF 2 "s_register_operand" "w")))] 695 (match_operand:DF 2 "s_register_operand" "w")))]
547 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 696 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
548 "fsubd%?\\t%P0, %P1, %P2" 697 "fsubd%?\\t%P0, %P1, %P2"
549 [(set_attr "predicable" "yes") 698 [(set_attr "predicable" "yes")
550 (set_attr "type" "faddd")] 699 (set_attr "type" "faddd")]
551 ) 700 )
552 701
565 714
566 (define_insn "*divdf3_vfp" 715 (define_insn "*divdf3_vfp"
567 [(set (match_operand:DF 0 "s_register_operand" "+w") 716 [(set (match_operand:DF 0 "s_register_operand" "+w")
568 (div:DF (match_operand:DF 1 "s_register_operand" "w") 717 (div:DF (match_operand:DF 1 "s_register_operand" "w")
569 (match_operand:DF 2 "s_register_operand" "w")))] 718 (match_operand:DF 2 "s_register_operand" "w")))]
570 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 719 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
571 "fdivd%?\\t%P0, %P1, %P2" 720 "fdivd%?\\t%P0, %P1, %P2"
572 [(set_attr "predicable" "yes") 721 [(set_attr "predicable" "yes")
573 (set_attr "type" "fdivd")] 722 (set_attr "type" "fdivd")]
574 ) 723 )
575 724
588 737
589 (define_insn "*muldf3_vfp" 738 (define_insn "*muldf3_vfp"
590 [(set (match_operand:DF 0 "s_register_operand" "+w") 739 [(set (match_operand:DF 0 "s_register_operand" "+w")
591 (mult:DF (match_operand:DF 1 "s_register_operand" "w") 740 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
592 (match_operand:DF 2 "s_register_operand" "w")))] 741 (match_operand:DF 2 "s_register_operand" "w")))]
593 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 742 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
594 "fmuld%?\\t%P0, %P1, %P2" 743 "fmuld%?\\t%P0, %P1, %P2"
595 [(set_attr "predicable" "yes") 744 [(set_attr "predicable" "yes")
596 (set_attr "type" "fmuld")] 745 (set_attr "type" "fmuld")]
597 ) 746 )
598 747
609 758
610 (define_insn "*muldf3negdf_vfp" 759 (define_insn "*muldf3negdf_vfp"
611 [(set (match_operand:DF 0 "s_register_operand" "+w") 760 [(set (match_operand:DF 0 "s_register_operand" "+w")
612 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w")) 761 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
613 (match_operand:DF 2 "s_register_operand" "w")))] 762 (match_operand:DF 2 "s_register_operand" "w")))]
614 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 763 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
615 "fnmuld%?\\t%P0, %P1, %P2" 764 "fnmuld%?\\t%P0, %P1, %P2"
616 [(set_attr "predicable" "yes") 765 [(set_attr "predicable" "yes")
617 (set_attr "type" "fmuld")] 766 (set_attr "type" "fmuld")]
618 ) 767 )
619 768
635 (define_insn "*muldf3adddf_vfp" 784 (define_insn "*muldf3adddf_vfp"
636 [(set (match_operand:DF 0 "s_register_operand" "=w") 785 [(set (match_operand:DF 0 "s_register_operand" "=w")
637 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") 786 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
638 (match_operand:DF 3 "s_register_operand" "w")) 787 (match_operand:DF 3 "s_register_operand" "w"))
639 (match_operand:DF 1 "s_register_operand" "0")))] 788 (match_operand:DF 1 "s_register_operand" "0")))]
640 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 789 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
641 "fmacd%?\\t%P0, %P2, %P3" 790 "fmacd%?\\t%P0, %P2, %P3"
642 [(set_attr "predicable" "yes") 791 [(set_attr "predicable" "yes")
643 (set_attr "type" "fmacd")] 792 (set_attr "type" "fmacd")]
644 ) 793 )
645 794
658 (define_insn "*muldf3subdf_vfp" 807 (define_insn "*muldf3subdf_vfp"
659 [(set (match_operand:DF 0 "s_register_operand" "=w") 808 [(set (match_operand:DF 0 "s_register_operand" "=w")
660 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w") 809 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
661 (match_operand:DF 3 "s_register_operand" "w")) 810 (match_operand:DF 3 "s_register_operand" "w"))
662 (match_operand:DF 1 "s_register_operand" "0")))] 811 (match_operand:DF 1 "s_register_operand" "0")))]
663 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 812 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
664 "fmscd%?\\t%P0, %P2, %P3" 813 "fmscd%?\\t%P0, %P2, %P3"
665 [(set_attr "predicable" "yes") 814 [(set_attr "predicable" "yes")
666 (set_attr "type" "fmacd")] 815 (set_attr "type" "fmacd")]
667 ) 816 )
668 817
681 (define_insn "*fmuldf3negdfadddf_vfp" 830 (define_insn "*fmuldf3negdfadddf_vfp"
682 [(set (match_operand:DF 0 "s_register_operand" "=w") 831 [(set (match_operand:DF 0 "s_register_operand" "=w")
683 (minus:DF (match_operand:DF 1 "s_register_operand" "0") 832 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
684 (mult:DF (match_operand:DF 2 "s_register_operand" "w") 833 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
685 (match_operand:DF 3 "s_register_operand" "w"))))] 834 (match_operand:DF 3 "s_register_operand" "w"))))]
686 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 835 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
687 "fnmacd%?\\t%P0, %P2, %P3" 836 "fnmacd%?\\t%P0, %P2, %P3"
688 [(set_attr "predicable" "yes") 837 [(set_attr "predicable" "yes")
689 (set_attr "type" "fmacd")] 838 (set_attr "type" "fmacd")]
690 ) 839 )
691 840
707 [(set (match_operand:DF 0 "s_register_operand" "=w") 856 [(set (match_operand:DF 0 "s_register_operand" "=w")
708 (minus:DF (mult:DF 857 (minus:DF (mult:DF
709 (neg:DF (match_operand:DF 2 "s_register_operand" "w")) 858 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
710 (match_operand:DF 3 "s_register_operand" "w")) 859 (match_operand:DF 3 "s_register_operand" "w"))
711 (match_operand:DF 1 "s_register_operand" "0")))] 860 (match_operand:DF 1 "s_register_operand" "0")))]
712 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 861 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
713 "fnmscd%?\\t%P0, %P2, %P3" 862 "fnmscd%?\\t%P0, %P2, %P3"
714 [(set_attr "predicable" "yes") 863 [(set_attr "predicable" "yes")
715 (set_attr "type" "fmacd")] 864 (set_attr "type" "fmacd")]
716 ) 865 )
717 866
719 ;; Conversion routines 868 ;; Conversion routines
720 869
721 (define_insn "*extendsfdf2_vfp" 870 (define_insn "*extendsfdf2_vfp"
722 [(set (match_operand:DF 0 "s_register_operand" "=w") 871 [(set (match_operand:DF 0 "s_register_operand" "=w")
723 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))] 872 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
724 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 873 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
725 "fcvtds%?\\t%P0, %1" 874 "fcvtds%?\\t%P0, %1"
726 [(set_attr "predicable" "yes") 875 [(set_attr "predicable" "yes")
727 (set_attr "type" "f_cvt")] 876 (set_attr "type" "f_cvt")]
728 ) 877 )
729 878
730 (define_insn "*truncdfsf2_vfp" 879 (define_insn "*truncdfsf2_vfp"
731 [(set (match_operand:SF 0 "s_register_operand" "=t") 880 [(set (match_operand:SF 0 "s_register_operand" "=t")
732 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))] 881 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
733 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 882 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
734 "fcvtsd%?\\t%0, %P1" 883 "fcvtsd%?\\t%0, %P1"
884 [(set_attr "predicable" "yes")
885 (set_attr "type" "f_cvt")]
886 )
887
888 (define_insn "extendhfsf2"
889 [(set (match_operand:SF 0 "s_register_operand" "=t")
890 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
891 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
892 "vcvtb%?.f32.f16\\t%0, %1"
893 [(set_attr "predicable" "yes")
894 (set_attr "type" "f_cvt")]
895 )
896
897 (define_insn "truncsfhf2"
898 [(set (match_operand:HF 0 "s_register_operand" "=t")
899 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
900 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
901 "vcvtb%?.f16.f32\\t%0, %1"
735 [(set_attr "predicable" "yes") 902 [(set_attr "predicable" "yes")
736 (set_attr "type" "f_cvt")] 903 (set_attr "type" "f_cvt")]
737 ) 904 )
738 905
739 (define_insn "*truncsisf2_vfp" 906 (define_insn "*truncsisf2_vfp"
746 ) 913 )
747 914
748 (define_insn "*truncsidf2_vfp" 915 (define_insn "*truncsidf2_vfp"
749 [(set (match_operand:SI 0 "s_register_operand" "=t") 916 [(set (match_operand:SI 0 "s_register_operand" "=t")
750 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))] 917 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
751 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 918 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
752 "ftosizd%?\\t%0, %P1" 919 "ftosizd%?\\t%0, %P1"
753 [(set_attr "predicable" "yes") 920 [(set_attr "predicable" "yes")
754 (set_attr "type" "f_cvt")] 921 (set_attr "type" "f_cvt")]
755 ) 922 )
756 923
765 ) 932 )
766 933
767 (define_insn "fixuns_truncdfsi2" 934 (define_insn "fixuns_truncdfsi2"
768 [(set (match_operand:SI 0 "s_register_operand" "=t") 935 [(set (match_operand:SI 0 "s_register_operand" "=t")
769 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))] 936 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
770 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 937 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
771 "ftouizd%?\\t%0, %P1" 938 "ftouizd%?\\t%0, %P1"
772 [(set_attr "predicable" "yes") 939 [(set_attr "predicable" "yes")
773 (set_attr "type" "f_cvt")] 940 (set_attr "type" "f_cvt")]
774 ) 941 )
775 942
784 ) 951 )
785 952
786 (define_insn "*floatsidf2_vfp" 953 (define_insn "*floatsidf2_vfp"
787 [(set (match_operand:DF 0 "s_register_operand" "=w") 954 [(set (match_operand:DF 0 "s_register_operand" "=w")
788 (float:DF (match_operand:SI 1 "s_register_operand" "t")))] 955 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
789 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 956 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
790 "fsitod%?\\t%P0, %1" 957 "fsitod%?\\t%P0, %1"
791 [(set_attr "predicable" "yes") 958 [(set_attr "predicable" "yes")
792 (set_attr "type" "f_cvt")] 959 (set_attr "type" "f_cvt")]
793 ) 960 )
794 961
803 ) 970 )
804 971
805 (define_insn "floatunssidf2" 972 (define_insn "floatunssidf2"
806 [(set (match_operand:DF 0 "s_register_operand" "=w") 973 [(set (match_operand:DF 0 "s_register_operand" "=w")
807 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))] 974 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
808 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 975 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
809 "fuitod%?\\t%P0, %1" 976 "fuitod%?\\t%P0, %1"
810 [(set_attr "predicable" "yes") 977 [(set_attr "predicable" "yes")
811 (set_attr "type" "f_cvt")] 978 (set_attr "type" "f_cvt")]
812 ) 979 )
813 980
824 ) 991 )
825 992
826 (define_insn "*sqrtdf2_vfp" 993 (define_insn "*sqrtdf2_vfp"
827 [(set (match_operand:DF 0 "s_register_operand" "=w") 994 [(set (match_operand:DF 0 "s_register_operand" "=w")
828 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))] 995 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
829 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 996 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
830 "fsqrtd%?\\t%P0, %P1" 997 "fsqrtd%?\\t%P0, %P1"
831 [(set_attr "predicable" "yes") 998 [(set_attr "predicable" "yes")
832 (set_attr "type" "fdivd")] 999 (set_attr "type" "fdivd")]
833 ) 1000 )
834 1001
876 1043
877 (define_insn_and_split "*cmpdf_split_vfp" 1044 (define_insn_and_split "*cmpdf_split_vfp"
878 [(set (reg:CCFP CC_REGNUM) 1045 [(set (reg:CCFP CC_REGNUM)
879 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w") 1046 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
880 (match_operand:DF 1 "vfp_compare_operand" "wG")))] 1047 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
881 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1048 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
882 "#" 1049 "#"
883 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1050 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
884 [(set (reg:CCFP VFPCC_REGNUM) 1051 [(set (reg:CCFP VFPCC_REGNUM)
885 (compare:CCFP (match_dup 0) 1052 (compare:CCFP (match_dup 0)
886 (match_dup 1))) 1053 (match_dup 1)))
887 (set (reg:CCFP CC_REGNUM) 1054 (set (reg:CCFP CC_REGNUM)
888 (reg:CCFPE VFPCC_REGNUM))] 1055 (reg:CCFP VFPCC_REGNUM))]
889 "" 1056 ""
890 ) 1057 )
891 1058
892 (define_insn_and_split "*cmpdf_trap_split_vfp" 1059 (define_insn_and_split "*cmpdf_trap_split_vfp"
893 [(set (reg:CCFPE CC_REGNUM) 1060 [(set (reg:CCFPE CC_REGNUM)
894 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w") 1061 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
895 (match_operand:DF 1 "vfp_compare_operand" "wG")))] 1062 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
896 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1063 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
897 "#" 1064 "#"
898 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1065 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
899 [(set (reg:CCFPE VFPCC_REGNUM) 1066 [(set (reg:CCFPE VFPCC_REGNUM)
900 (compare:CCFPE (match_dup 0) 1067 (compare:CCFPE (match_dup 0)
901 (match_dup 1))) 1068 (match_dup 1)))
902 (set (reg:CCFPE CC_REGNUM) 1069 (set (reg:CCFPE CC_REGNUM)
903 (reg:CCFPE VFPCC_REGNUM))] 1070 (reg:CCFPE VFPCC_REGNUM))]
933 1100
934 (define_insn "*cmpdf_vfp" 1101 (define_insn "*cmpdf_vfp"
935 [(set (reg:CCFP VFPCC_REGNUM) 1102 [(set (reg:CCFP VFPCC_REGNUM)
936 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w") 1103 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
937 (match_operand:DF 1 "vfp_compare_operand" "w,G")))] 1104 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
938 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1105 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
939 "@ 1106 "@
940 fcmpd%?\\t%P0, %P1 1107 fcmpd%?\\t%P0, %P1
941 fcmpzd%?\\t%P0" 1108 fcmpzd%?\\t%P0"
942 [(set_attr "predicable" "yes") 1109 [(set_attr "predicable" "yes")
943 (set_attr "type" "fcmpd")] 1110 (set_attr "type" "fcmpd")]
945 1112
946 (define_insn "*cmpdf_trap_vfp" 1113 (define_insn "*cmpdf_trap_vfp"
947 [(set (reg:CCFPE VFPCC_REGNUM) 1114 [(set (reg:CCFPE VFPCC_REGNUM)
948 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w") 1115 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
949 (match_operand:DF 1 "vfp_compare_operand" "w,G")))] 1116 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
950 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" 1117 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
951 "@ 1118 "@
952 fcmped%?\\t%P0, %P1 1119 fcmped%?\\t%P0, %P1
953 fcmpezd%?\\t%P0" 1120 fcmpezd%?\\t%P0"
954 [(set_attr "predicable" "yes") 1121 [(set_attr "predicable" "yes")
955 (set_attr "type" "fcmpd")] 1122 (set_attr "type" "fcmpd")]