Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/arm/vfp.md @ 55:77e2b8dfacca gcc-4.4.5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children b7f97abdc517
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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1 ;; ARM VFP instruction patterns
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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21 ;; Additional register numbers
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22 (define_constants
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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23 [(VFPCC_REGNUM 127)]
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24 )
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25
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26 ;; The VFP "type" attributes differ from those used in the FPA model.
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27 ;; fcpys Single precision cpy.
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28 ;; ffariths Single precision abs, neg.
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29 ;; ffarithd Double precision abs, neg, cpy.
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30 ;; fadds Single precision add/sub.
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31 ;; faddd Double precision add/sub.
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32 ;; fconsts Single precision load immediate.
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33 ;; fconstd Double precision load immediate.
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34 ;; fcmps Single precision comparison.
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35 ;; fcmpd Double precision comparison.
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36 ;; fmuls Single precision multiply.
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37 ;; fmuld Double precision multiply.
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38 ;; fmacs Single precision multiply-accumulate.
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39 ;; fmacd Double precision multiply-accumulate.
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40 ;; fdivs Single precision sqrt or division.
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41 ;; fdivd Double precision sqrt or division.
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42 ;; f_flag fmstat operation
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43 ;; f_load[sd] Floating point load from memory.
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44 ;; f_store[sd] Floating point store to memory.
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45 ;; f_2_r Transfer vfp to arm reg.
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46 ;; r_2_f Transfer arm to vfp reg.
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47 ;; f_cvt Convert floating<->integral
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48
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49 ;; SImode moves
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50 ;; ??? For now do not allow loading constants into vfp regs. This causes
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51 ;; problems because small constants get converted into adds.
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52 (define_insn "*arm_movsi_vfp"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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53 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
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77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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54 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
0
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55 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
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56 && ( s_register_operand (operands[0], SImode)
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57 || s_register_operand (operands[1], SImode))"
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58 "*
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59 switch (which_alternative)
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60 {
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61 case 0: case 1:
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62 return \"mov%?\\t%0, %1\";
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63 case 2:
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64 return \"mvn%?\\t%0, #%B1\";
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65 case 3:
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66 return \"movw%?\\t%0, %1\";
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67 case 4:
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68 return \"ldr%?\\t%0, %1\";
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69 case 5:
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70 return \"str%?\\t%1, %0\";
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71 case 6:
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72 return \"fmsr%?\\t%0, %1\\t%@ int\";
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73 case 7:
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74 return \"fmrs%?\\t%0, %1\\t%@ int\";
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75 case 8:
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76 return \"fcpys%?\\t%0, %1\\t%@ int\";
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77 case 9: case 10:
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78 return output_move_vfp (operands);
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79 default:
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80 gcc_unreachable ();
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81 }
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82 "
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83 [(set_attr "predicable" "yes")
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84 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
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85 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
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86 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
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87 )
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88
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89 (define_insn "*thumb2_movsi_vfp"
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90 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
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91 (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
0
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92 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
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93 && ( s_register_operand (operands[0], SImode)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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94 || s_register_operand (operands[1], SImode))"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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95 "*
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96 switch (which_alternative)
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97 {
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98 case 0: case 1:
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99 return \"mov%?\\t%0, %1\";
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100 case 2:
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101 return \"mvn%?\\t%0, #%B1\";
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102 case 3:
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103 return \"movw%?\\t%0, %1\";
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104 case 4:
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105 return \"ldr%?\\t%0, %1\";
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106 case 5:
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107 return \"str%?\\t%1, %0\";
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108 case 6:
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109 return \"fmsr%?\\t%0, %1\\t%@ int\";
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110 case 7:
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111 return \"fmrs%?\\t%0, %1\\t%@ int\";
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112 case 8:
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113 return \"fcpys%?\\t%0, %1\\t%@ int\";
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114 case 9: case 10:
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115 return output_move_vfp (operands);
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116 default:
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117 gcc_unreachable ();
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118 }
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119 "
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120 [(set_attr "predicable" "yes")
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121 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
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122 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
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123 (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")]
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124 )
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125
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126
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127 ;; DImode moves
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128
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129 (define_insn "*arm_movdi_vfp"
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130 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
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131 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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132 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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133 && ( register_operand (operands[0], DImode)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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134 || register_operand (operands[1], DImode))"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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135 "*
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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136 switch (which_alternative)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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137 {
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138 case 0:
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139 return \"#\";
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140 case 1:
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141 case 2:
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142 return output_move_double (operands);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 case 3:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 case 4:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 case 5:
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
148 if (TARGET_VFP_SINGLE)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
149 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
150 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
151 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 case 6: case 7:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 return output_move_vfp (operands);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 default:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 gcc_unreachable ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
159 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
160 (eq_attr "alternative" "5")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
161 (if_then_else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
162 (eq (symbol_ref "TARGET_VFP_SINGLE")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
163 (const_int 1))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
164 (const_int 8)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
165 (const_int 4))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
166 (const_int 4)))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
167 (set_attr "predicable" "yes")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 (define_insn "*thumb2_movdi_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 "*
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 switch (which_alternative)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 case 0: case 1: case 2:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 return (output_move_double (operands));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 case 3:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 case 4:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 case 5:
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
186 if (TARGET_VFP_SINGLE)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
188 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
189 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 case 6: case 7:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 return output_move_vfp (operands);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 default:
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 abort ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
197 (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
198 (eq_attr "alternative" "5")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
199 (if_then_else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
200 (eq (symbol_ref "TARGET_VFP_SINGLE")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
201 (const_int 1))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
202 (const_int 8)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
203 (const_int 4))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204 (const_int 4)))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
209 ;; HFmode moves
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
210 (define_insn "*movhf_vfp_neon"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
211 [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
212 (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
213 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
214 && ( s_register_operand (operands[0], HFmode)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
215 || s_register_operand (operands[1], HFmode))"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
216 "*
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
217 switch (which_alternative)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219 case 0: /* S register from memory */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 return \"vld1.16\\t{%z0}, %A1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 case 1: /* memory from S register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222 return \"vst1.16\\t{%z1}, %A0\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
223 case 2: /* ARM register from memory */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
224 return \"ldrh\\t%0, %1\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 case 3: /* memory from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 return \"strh\\t%1, %0\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 case 4: /* S register from S register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 return \"fcpys\\t%0, %1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 case 5: /* ARM register from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 return \"mov\\t%0, %1\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
231 case 6: /* S register from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
232 return \"fmsr\\t%0, %1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 case 7: /* ARM register from S register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234 return \"fmrs\\t%0, %1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
235 case 8: /* ARM register from constant */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236 {
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 REAL_VALUE_TYPE r;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238 long bits;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
239 rtx ops[4];
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
240
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
241 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
242 bits = real_to_target (NULL, &r, HFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
243 ops[0] = operands[0];
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
244 ops[1] = GEN_INT (bits);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
245 ops[2] = GEN_INT (bits & 0xff00);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
246 ops[3] = GEN_INT (bits & 0x00ff);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
247
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
248 if (arm_arch_thumb2)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
249 output_asm_insn (\"movw\\t%0, %1\", ops);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
250 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
251 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
252 return \"\";
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
253 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
254 default:
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 gcc_unreachable ();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
256 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
257 "
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
258 [(set_attr "conds" "unconditional")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
259 (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
260 (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
261 (set_attr "length" "4,4,4,4,4,4,4,4,8")]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
262 )
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
263
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
264 ;; FP16 without element load/store instructions.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
265 (define_insn "*movhf_vfp"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
266 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
267 (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
268 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
269 && ( s_register_operand (operands[0], HFmode)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
270 || s_register_operand (operands[1], HFmode))"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
271 "*
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
272 switch (which_alternative)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
273 {
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
274 case 0: /* ARM register from memory */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
275 return \"ldrh\\t%0, %1\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
276 case 1: /* memory from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
277 return \"strh\\t%1, %0\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
278 case 2: /* S register from S register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
279 return \"fcpys\\t%0, %1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
280 case 3: /* ARM register from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
281 return \"mov\\t%0, %1\\t%@ __fp16\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
282 case 4: /* S register from ARM register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
283 return \"fmsr\\t%0, %1\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
284 case 5: /* ARM register from S register */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
285 return \"fmrs\\t%0, %1\";
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
286 case 6: /* ARM register from constant */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
287 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
288 REAL_VALUE_TYPE r;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
289 long bits;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
290 rtx ops[4];
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
291
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
292 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
293 bits = real_to_target (NULL, &r, HFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
294 ops[0] = operands[0];
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
295 ops[1] = GEN_INT (bits);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
296 ops[2] = GEN_INT (bits & 0xff00);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
297 ops[3] = GEN_INT (bits & 0x00ff);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
298
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
299 if (arm_arch_thumb2)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
300 output_asm_insn (\"movw\\t%0, %1\", ops);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
301 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
302 output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
303 return \"\";
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
304 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
305 default:
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
306 gcc_unreachable ();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
307 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
308 "
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
309 [(set_attr "conds" "unconditional")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
310 (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
311 (set_attr "length" "4,4,4,4,4,4,8")]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
312 )
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
313
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
314
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 ;; SFmode moves
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 ;; Disparage the w<->r cases because reloading an invalid address is
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 ;; preferable to loading the value via integer registers.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
318
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 (define_insn "*movsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
323 && ( s_register_operand (operands[0], SFmode)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 || s_register_operand (operands[1], SFmode))"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 "*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 switch (which_alternative)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 case 0:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 return \"fmsr%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 case 1:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 return \"fmrs%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 case 2:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 return \"fconsts%?\\t%0, #%G1\";
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 case 3: case 4:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 return output_move_vfp (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 case 5:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 return \"ldr%?\\t%0, %1\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 case 6:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
339 return \"str%?\\t%1, %0\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
340 case 7:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
341 return \"fcpys%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 case 8:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
343 return \"mov%?\\t%0, %1\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
344 default:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 gcc_unreachable ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
346 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
348 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 (set_attr "type"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
352 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
353 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
354
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
355 (define_insn "*thumb2_movsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
356 [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
357 (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
358 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
359 && ( s_register_operand (operands[0], SFmode)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
360 || s_register_operand (operands[1], SFmode))"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
361 "*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 switch (which_alternative)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
364 case 0:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 return \"fmsr%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 case 1:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 return \"fmrs%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 case 2:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
369 return \"fconsts%?\\t%0, #%G1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
370 case 3: case 4:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 return output_move_vfp (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
372 case 5:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
373 return \"ldr%?\\t%0, %1\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 case 6:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 return \"str%?\\t%1, %0\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
376 case 7:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 return \"fcpys%?\\t%0, %1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 case 8:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 return \"mov%?\\t%0, %1\\t%@ float\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 default:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 gcc_unreachable ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
385 (set_attr "type"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
386 "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
387 (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
388 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
390
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
391
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 ;; DFmode moves
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
393
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 (define_insn "*movdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
396 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 && ( register_operand (operands[0], DFmode)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 || register_operand (operands[1], DFmode))"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 "*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 switch (which_alternative)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 case 0:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 return \"fmdrr%?\\t%P0, %Q1, %R1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 case 1:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 return \"fmrrd%?\\t%Q0, %R0, %P1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 case 2:
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
409 gcc_assert (TARGET_VFP_DOUBLE);
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 return \"fconstd%?\\t%P0, #%G1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 case 3: case 4:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 return output_move_double (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 case 5: case 6:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 return output_move_vfp (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 case 7:
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
416 if (TARGET_VFP_SINGLE)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
417 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
418 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
419 return \"fcpyd%?\\t%P0, %P1\";
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 case 8:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 return \"#\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 default:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 gcc_unreachable ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 [(set_attr "type"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
429 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
430 (eq_attr "alternative" "7")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
431 (if_then_else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
432 (eq (symbol_ref "TARGET_VFP_SINGLE")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
433 (const_int 1))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
434 (const_int 8)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
435 (const_int 4))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
436 (const_int 4)))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
437 (set_attr "predicable" "yes")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 (define_insn "*thumb2_movdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
444 (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 "*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 switch (which_alternative)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 case 0:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 return \"fmdrr%?\\t%P0, %Q1, %R1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 case 1:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 return \"fmrrd%?\\t%Q0, %R0, %P1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 case 2:
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
455 gcc_assert (TARGET_VFP_DOUBLE);
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 return \"fconstd%?\\t%P0, #%G1\";
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 case 3: case 4: case 8:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
458 return output_move_double (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
459 case 5: case 6:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 return output_move_vfp (operands);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
461 case 7:
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
462 if (TARGET_VFP_SINGLE)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
463 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
464 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
465 return \"fcpyd%?\\t%P0, %P1\";
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 default:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 abort ();
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 [(set_attr "type"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
473 (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
474 (eq_attr "alternative" "7")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
475 (if_then_else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
476 (eq (symbol_ref "TARGET_VFP_SINGLE")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
477 (const_int 1))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
478 (const_int 8)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
479 (const_int 4))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
480 (const_int 4)))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
484
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
485
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
486 ;; Conditional move patterns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
487
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 (define_insn "*movsfcc_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 (if_then_else:SF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 (match_operator 3 "arm_comparison_operator"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
492 [(match_operand 4 "cc_register" "") (const_int 0)])
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 fcpys%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 fcpys%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
500 fmsr%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
501 fmsr%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
502 fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
503 fmrs%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 fmrs%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 [(set_attr "conds" "use")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 (set_attr "length" "4,4,8,4,4,8,4,4,8")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
510
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
511 (define_insn "*thumb2_movsfcc_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
512 [(set (match_operand:SF 0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
513 (if_then_else:SF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
514 (match_operator 3 "arm_comparison_operator"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
515 [(match_operand 4 "cc_register" "") (const_int 0)])
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
516 (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
517 (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
519 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 it\\t%D3\;fcpys%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 it\\t%d3\;fcpys%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
522 ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
523 it\\t%D3\;fmsr%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 it\\t%d3\;fmsr%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
525 ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
526 it\\t%D3\;fmrs%D3\\t%0, %2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
527 it\\t%d3\;fmrs%d3\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
528 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
529 [(set_attr "conds" "use")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
530 (set_attr "length" "6,6,10,6,6,10,6,6,10")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
531 (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
532 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
533
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 (define_insn "*movdfcc_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
535 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
536 (if_then_else:DF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
537 (match_operator 3 "arm_comparison_operator"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 [(match_operand 4 "cc_register" "") (const_int 0)])
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
539 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
540 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
541 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
542 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
543 fcpyd%D3\\t%P0, %P2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
544 fcpyd%d3\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
545 fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
546 fmdrr%D3\\t%P0, %Q2, %R2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
547 fmdrr%d3\\t%P0, %Q1, %R1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
548 fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
549 fmrrd%D3\\t%Q0, %R0, %P2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
550 fmrrd%d3\\t%Q0, %R0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
551 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
552 [(set_attr "conds" "use")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
553 (set_attr "length" "4,4,8,4,4,8,4,4,8")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
554 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
555 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
556
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
557 (define_insn "*thumb2_movdfcc_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
558 [(set (match_operand:DF 0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
559 (if_then_else:DF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
560 (match_operator 3 "arm_comparison_operator"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
561 [(match_operand 4 "cc_register" "") (const_int 0)])
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
562 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
563 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
564 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
565 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
566 it\\t%D3\;fcpyd%D3\\t%P0, %P2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
567 it\\t%d3\;fcpyd%d3\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
568 ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
569 it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
570 it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
571 ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
572 it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
573 it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
574 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
575 [(set_attr "conds" "use")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
576 (set_attr "length" "6,6,10,6,6,10,6,6,10")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
577 (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
578 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
579
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
580
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
581 ;; Sign manipulation functions
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
582
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
583 (define_insn "*abssf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
584 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
585 (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
586 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
587 "fabss%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
588 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
589 (set_attr "type" "ffariths")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
590 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
591
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
592 (define_insn "*absdf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
593 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
594 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
595 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
596 "fabsd%?\\t%P0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
597 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
598 (set_attr "type" "ffarithd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
599 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
600
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
601 (define_insn "*negsf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
602 [(set (match_operand:SF 0 "s_register_operand" "=t,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
603 (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
604 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
605 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
606 fnegs%?\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
607 eor%?\\t%0, %1, #-2147483648"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
608 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
609 (set_attr "type" "ffariths")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
610 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
611
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
612 (define_insn_and_split "*negdf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
613 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
614 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
615 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
616 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
617 fnegd%?\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
618 #
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
619 #"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
620 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
621 && arm_general_register_operand (operands[0], DFmode)"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
622 [(set (match_dup 0) (match_dup 1))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
623 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
624 if (REGNO (operands[0]) == REGNO (operands[1]))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
625 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
626 operands[0] = gen_highpart (SImode, operands[0]);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
627 operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
628 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
629 else
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
630 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
631 rtx in_hi, in_lo, out_hi, out_lo;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
632
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
633 in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
634 GEN_INT (0x80000000));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
635 in_lo = gen_lowpart (SImode, operands[1]);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
636 out_hi = gen_highpart (SImode, operands[0]);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
637 out_lo = gen_lowpart (SImode, operands[0]);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
638
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
639 if (REGNO (in_lo) == REGNO (out_hi))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
640 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
641 emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
642 operands[0] = out_hi;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
643 operands[1] = in_hi;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
644 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
645 else
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
646 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
647 emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
648 operands[0] = out_lo;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
649 operands[1] = in_lo;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
650 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
651 }
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
652 "
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
653 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
654 (set_attr "length" "4,4,8")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
655 (set_attr "type" "ffarithd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
656 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
657
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
658
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
659 ;; Arithmetic insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
660
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
661 (define_insn "*addsf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
662 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
663 (plus:SF (match_operand:SF 1 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
664 (match_operand:SF 2 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
665 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
666 "fadds%?\\t%0, %1, %2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
667 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
668 (set_attr "type" "fadds")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
669 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
670
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
671 (define_insn "*adddf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
672 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
673 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
674 (match_operand:DF 2 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
675 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
676 "faddd%?\\t%P0, %P1, %P2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
677 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
678 (set_attr "type" "faddd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
679 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
680
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
681
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
682 (define_insn "*subsf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
683 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
684 (minus:SF (match_operand:SF 1 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
685 (match_operand:SF 2 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
686 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
687 "fsubs%?\\t%0, %1, %2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
688 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
689 (set_attr "type" "fadds")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
690 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
691
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
692 (define_insn "*subdf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
693 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
694 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
695 (match_operand:DF 2 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
696 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
697 "fsubd%?\\t%P0, %P1, %P2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
698 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
699 (set_attr "type" "faddd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
700 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
701
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
702
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
703 ;; Division insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
704
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
705 (define_insn "*divsf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
706 [(set (match_operand:SF 0 "s_register_operand" "+t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
707 (div:SF (match_operand:SF 1 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
708 (match_operand:SF 2 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
709 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
710 "fdivs%?\\t%0, %1, %2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
711 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
712 (set_attr "type" "fdivs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
713 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
714
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
715 (define_insn "*divdf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
716 [(set (match_operand:DF 0 "s_register_operand" "+w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
717 (div:DF (match_operand:DF 1 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
718 (match_operand:DF 2 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
719 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
720 "fdivd%?\\t%P0, %P1, %P2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
721 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
722 (set_attr "type" "fdivd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
723 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
724
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
725
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
726 ;; Multiplication insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
727
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
728 (define_insn "*mulsf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
729 [(set (match_operand:SF 0 "s_register_operand" "+t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
730 (mult:SF (match_operand:SF 1 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
731 (match_operand:SF 2 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
732 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
733 "fmuls%?\\t%0, %1, %2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
734 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
735 (set_attr "type" "fmuls")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
736 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
737
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
738 (define_insn "*muldf3_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
739 [(set (match_operand:DF 0 "s_register_operand" "+w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
740 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
741 (match_operand:DF 2 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
742 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
743 "fmuld%?\\t%P0, %P1, %P2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
744 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
745 (set_attr "type" "fmuld")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
746 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
747
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
748
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
749 (define_insn "*mulsf3negsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
750 [(set (match_operand:SF 0 "s_register_operand" "+t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
751 (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
752 (match_operand:SF 2 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
753 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
754 "fnmuls%?\\t%0, %1, %2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
755 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
756 (set_attr "type" "fmuls")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
757 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
758
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
759 (define_insn "*muldf3negdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
760 [(set (match_operand:DF 0 "s_register_operand" "+w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
761 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
762 (match_operand:DF 2 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
763 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
764 "fnmuld%?\\t%P0, %P1, %P2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
765 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
766 (set_attr "type" "fmuld")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
767 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
768
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
769
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
770 ;; Multiply-accumulate insns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
771
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
772 ;; 0 = 1 * 2 + 0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
773 (define_insn "*mulsf3addsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
774 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
775 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
776 (match_operand:SF 3 "s_register_operand" "t"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
777 (match_operand:SF 1 "s_register_operand" "0")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
778 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
779 "fmacs%?\\t%0, %2, %3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
780 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
781 (set_attr "type" "fmacs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
782 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
783
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
784 (define_insn "*muldf3adddf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
785 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
786 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
787 (match_operand:DF 3 "s_register_operand" "w"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
788 (match_operand:DF 1 "s_register_operand" "0")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
789 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
790 "fmacd%?\\t%P0, %P2, %P3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
791 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
792 (set_attr "type" "fmacd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
793 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
794
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
795 ;; 0 = 1 * 2 - 0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
796 (define_insn "*mulsf3subsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
797 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
798 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
799 (match_operand:SF 3 "s_register_operand" "t"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
800 (match_operand:SF 1 "s_register_operand" "0")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
801 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
802 "fmscs%?\\t%0, %2, %3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
803 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
804 (set_attr "type" "fmacs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
805 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
806
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
807 (define_insn "*muldf3subdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
808 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
809 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
810 (match_operand:DF 3 "s_register_operand" "w"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
811 (match_operand:DF 1 "s_register_operand" "0")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
812 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
813 "fmscd%?\\t%P0, %P2, %P3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
814 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
815 (set_attr "type" "fmacd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
816 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
817
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
818 ;; 0 = -(1 * 2) + 0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
819 (define_insn "*mulsf3negsfaddsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
820 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
821 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
822 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
823 (match_operand:SF 3 "s_register_operand" "t"))))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
824 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
825 "fnmacs%?\\t%0, %2, %3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
826 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
827 (set_attr "type" "fmacs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
828 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
829
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
830 (define_insn "*fmuldf3negdfadddf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
831 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
832 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
833 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
834 (match_operand:DF 3 "s_register_operand" "w"))))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
835 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
836 "fnmacd%?\\t%P0, %P2, %P3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
837 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
838 (set_attr "type" "fmacd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
839 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
840
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
841
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
842 ;; 0 = -(1 * 2) - 0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
843 (define_insn "*mulsf3negsfsubsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
844 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
845 (minus:SF (mult:SF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
846 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
847 (match_operand:SF 3 "s_register_operand" "t"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
848 (match_operand:SF 1 "s_register_operand" "0")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
849 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
850 "fnmscs%?\\t%0, %2, %3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
851 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
852 (set_attr "type" "fmacs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
853 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
854
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
855 (define_insn "*muldf3negdfsubdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
856 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
857 (minus:DF (mult:DF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
858 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
859 (match_operand:DF 3 "s_register_operand" "w"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
860 (match_operand:DF 1 "s_register_operand" "0")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
861 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
862 "fnmscd%?\\t%P0, %P2, %P3"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
863 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
864 (set_attr "type" "fmacd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
865 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
866
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
867
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
868 ;; Conversion routines
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
869
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
870 (define_insn "*extendsfdf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
871 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
872 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
873 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
874 "fcvtds%?\\t%P0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
875 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
876 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
877 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
878
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
879 (define_insn "*truncdfsf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
880 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
881 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
882 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
883 "fcvtsd%?\\t%0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
884 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
885 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
886 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
887
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
888 (define_insn "extendhfsf2"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
889 [(set (match_operand:SF 0 "s_register_operand" "=t")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
890 (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
891 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
892 "vcvtb%?.f32.f16\\t%0, %1"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
893 [(set_attr "predicable" "yes")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
894 (set_attr "type" "f_cvt")]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
895 )
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
896
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
897 (define_insn "truncsfhf2"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
898 [(set (match_operand:HF 0 "s_register_operand" "=t")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
899 (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
900 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
901 "vcvtb%?.f16.f32\\t%0, %1"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
902 [(set_attr "predicable" "yes")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
903 (set_attr "type" "f_cvt")]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
904 )
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
905
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
906 (define_insn "*truncsisf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
907 [(set (match_operand:SI 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
908 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
909 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
910 "ftosizs%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
911 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
912 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
913 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
914
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
915 (define_insn "*truncsidf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
916 [(set (match_operand:SI 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
917 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
918 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
919 "ftosizd%?\\t%0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
920 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
921 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
922 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
923
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
924
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
925 (define_insn "fixuns_truncsfsi2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
926 [(set (match_operand:SI 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
927 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
928 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
929 "ftouizs%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
930 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
931 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
932 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
933
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
934 (define_insn "fixuns_truncdfsi2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
935 [(set (match_operand:SI 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
936 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
937 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
938 "ftouizd%?\\t%0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
939 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
940 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
941 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
942
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
943
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
944 (define_insn "*floatsisf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
945 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
946 (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
947 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
948 "fsitos%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
949 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
950 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
951 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
952
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
953 (define_insn "*floatsidf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
954 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
955 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
956 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
957 "fsitod%?\\t%P0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
958 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
959 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
960 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
961
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
962
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
963 (define_insn "floatunssisf2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
964 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
965 (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
966 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
967 "fuitos%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
968 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
969 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
970 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
971
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
972 (define_insn "floatunssidf2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
973 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
974 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
975 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
976 "fuitod%?\\t%P0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
977 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
978 (set_attr "type" "f_cvt")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
979 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
980
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
981
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
982 ;; Sqrt insns.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
983
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
984 (define_insn "*sqrtsf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
985 [(set (match_operand:SF 0 "s_register_operand" "=t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
986 (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
987 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
988 "fsqrts%?\\t%0, %1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
989 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
990 (set_attr "type" "fdivs")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
991 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
992
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
993 (define_insn "*sqrtdf2_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
994 [(set (match_operand:DF 0 "s_register_operand" "=w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
995 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
996 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
997 "fsqrtd%?\\t%P0, %P1"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
998 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
999 (set_attr "type" "fdivd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1000 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1001
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1002
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1003 ;; Patterns to split/copy vfp condition flags.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1004
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1005 (define_insn "*movcc_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1006 [(set (reg CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1007 (reg VFPCC_REGNUM))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1008 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1009 "fmstat%?"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1010 [(set_attr "conds" "set")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1011 (set_attr "type" "f_flag")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1012 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1013
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1014 (define_insn_and_split "*cmpsf_split_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1015 [(set (reg:CCFP CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1016 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1017 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1018 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1019 "#"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1020 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1021 [(set (reg:CCFP VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1022 (compare:CCFP (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1023 (match_dup 1)))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1024 (set (reg:CCFP CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1025 (reg:CCFP VFPCC_REGNUM))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1026 ""
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1027 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1028
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1029 (define_insn_and_split "*cmpsf_trap_split_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1030 [(set (reg:CCFPE CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1031 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1032 (match_operand:SF 1 "vfp_compare_operand" "tG")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1033 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1034 "#"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1035 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1036 [(set (reg:CCFPE VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1037 (compare:CCFPE (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1038 (match_dup 1)))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1039 (set (reg:CCFPE CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1040 (reg:CCFPE VFPCC_REGNUM))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1041 ""
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1042 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1043
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1044 (define_insn_and_split "*cmpdf_split_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1045 [(set (reg:CCFP CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1046 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1047 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1048 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1049 "#"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1050 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1051 [(set (reg:CCFP VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1052 (compare:CCFP (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1053 (match_dup 1)))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1054 (set (reg:CCFP CC_REGNUM)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1055 (reg:CCFP VFPCC_REGNUM))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1056 ""
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1057 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1058
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1059 (define_insn_and_split "*cmpdf_trap_split_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1060 [(set (reg:CCFPE CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1061 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1062 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1063 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1064 "#"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1065 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1066 [(set (reg:CCFPE VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1067 (compare:CCFPE (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1068 (match_dup 1)))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1069 (set (reg:CCFPE CC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1070 (reg:CCFPE VFPCC_REGNUM))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1071 ""
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1072 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1073
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1074
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1075 ;; Comparison patterns
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1076
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1077 (define_insn "*cmpsf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1078 [(set (reg:CCFP VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1079 (compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1080 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1081 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1082 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1083 fcmps%?\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1084 fcmpzs%?\\t%0"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1085 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1086 (set_attr "type" "fcmps")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1087 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1088
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1089 (define_insn "*cmpsf_trap_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1090 [(set (reg:CCFPE VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1091 (compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1092 (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1093 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1094 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1095 fcmpes%?\\t%0, %1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1096 fcmpezs%?\\t%0"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1097 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1098 (set_attr "type" "fcmpd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1099 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1100
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1101 (define_insn "*cmpdf_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1102 [(set (reg:CCFP VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1103 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1104 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1105 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1106 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1107 fcmpd%?\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1108 fcmpzd%?\\t%P0"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1109 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1110 (set_attr "type" "fcmpd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1111 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1112
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1113 (define_insn "*cmpdf_trap_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1114 [(set (reg:CCFPE VFPCC_REGNUM)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1115 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1116 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1117 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1118 "@
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1119 fcmped%?\\t%P0, %P1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1120 fcmpezd%?\\t%P0"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1121 [(set_attr "predicable" "yes")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1122 (set_attr "type" "fcmpd")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1123 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1124
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1125
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1126 ;; Store multiple insn used in function prologue.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1127
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1128 (define_insn "*push_multi_vfp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1129 [(match_parallel 2 "multi_register_push"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1130 [(set (match_operand:BLK 0 "memory_operand" "=m")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1131 (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1132 UNSPEC_PUSH_MULT))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1133 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1134 "* return vfp_output_fstmd (operands);"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1135 [(set_attr "type" "f_stored")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1136 )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1137
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1138
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1139 ;; Unimplemented insns:
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1140 ;; fldm*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1141 ;; fstm*
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1142 ;; fmdhr et al (VFPv1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1143 ;; Support for xD (single precision only) variants.
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
1144 ;; fmrrs, fmsrr