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comparison gcc/config/mips/mips-ps-3d.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
comparison
equal deleted inserted replaced
52:c156f1bd5cd9 55:77e2b8dfacca
56 /* We can only support MOVN.PS and MOVZ.PS. 56 /* We can only support MOVN.PS and MOVZ.PS.
57 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and 57 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
58 MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move 58 MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move
59 each item independently. */ 59 each item independently. */
60 60
61 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT) 61 if (GET_MODE_CLASS (GET_MODE (XEXP (operands[1], 0))) != MODE_INT)
62 FAIL; 62 FAIL;
63 63
64 mips_expand_conditional_move (operands); 64 mips_expand_conditional_move (operands);
65 DONE; 65 DONE;
66 }) 66 })
437 ;---------------------------------------------------------------------------- 437 ;----------------------------------------------------------------------------
438 438
439 ; Branch on Any of Four Floating Point Condition Codes True 439 ; Branch on Any of Four Floating Point Condition Codes True
440 (define_insn "bc1any4t" 440 (define_insn "bc1any4t"
441 [(set (pc) 441 [(set (pc)
442 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 442 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
443 (const_int 0)) 443 (const_int 0))
444 (label_ref (match_operand 1 "" "")) 444 (label_ref (match_operand 0 "" ""))
445 (pc)))] 445 (pc)))]
446 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 446 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
447 "%*bc1any4t\t%0,%1%/" 447 "%*bc1any4t\t%1,%0%/"
448 [(set_attr "type" "branch") 448 [(set_attr "type" "branch")])
449 (set_attr "mode" "none")])
450 449
451 ; Branch on Any of Four Floating Point Condition Codes False 450 ; Branch on Any of Four Floating Point Condition Codes False
452 (define_insn "bc1any4f" 451 (define_insn "bc1any4f"
453 [(set (pc) 452 [(set (pc)
454 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 453 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
455 (const_int -1)) 454 (const_int -1))
456 (label_ref (match_operand 1 "" "")) 455 (label_ref (match_operand 0 "" ""))
457 (pc)))] 456 (pc)))]
458 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 457 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
459 "%*bc1any4f\t%0,%1%/" 458 "%*bc1any4f\t%1,%0%/"
460 [(set_attr "type" "branch") 459 [(set_attr "type" "branch")])
461 (set_attr "mode" "none")])
462 460
463 ; Branch on Any of Two Floating Point Condition Codes True 461 ; Branch on Any of Two Floating Point Condition Codes True
464 (define_insn "bc1any2t" 462 (define_insn "bc1any2t"
465 [(set (pc) 463 [(set (pc)
466 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 464 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
467 (const_int 0)) 465 (const_int 0))
468 (label_ref (match_operand 1 "" "")) 466 (label_ref (match_operand 0 "" ""))
469 (pc)))] 467 (pc)))]
470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 468 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
471 "%*bc1any2t\t%0,%1%/" 469 "%*bc1any2t\t%1,%0%/"
472 [(set_attr "type" "branch") 470 [(set_attr "type" "branch")])
473 (set_attr "mode" "none")])
474 471
475 ; Branch on Any of Two Floating Point Condition Codes False 472 ; Branch on Any of Two Floating Point Condition Codes False
476 (define_insn "bc1any2f" 473 (define_insn "bc1any2f"
477 [(set (pc) 474 [(set (pc)
478 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 475 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
479 (const_int -1)) 476 (const_int -1))
480 (label_ref (match_operand 1 "" "")) 477 (label_ref (match_operand 0 "" ""))
481 (pc)))] 478 (pc)))]
482 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 479 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
483 "%*bc1any2f\t%0,%1%/" 480 "%*bc1any2f\t%1,%0%/"
484 [(set_attr "type" "branch") 481 [(set_attr "type" "branch")])
485 (set_attr "mode" "none")])
486 482
487 ; Used to access one register in a CCV2 pair. Operand 0 is the register 483 ; Used to access one register in a CCV2 pair. Operand 0 is the register
488 ; pair and operand 1 is the index of the register we want (a CONST_INT). 484 ; pair and operand 1 is the index of the register we want (a CONST_INT).
489 (define_expand "single_cc" 485 (define_expand "single_cc"
490 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC) 486 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
495 ; Operand 2 is the register pair and operand 3 is the index of the 491 ; Operand 2 is the register pair and operand 3 is the index of the
496 ; register we want. 492 ; register we want.
497 (define_insn "*branch_upper_lower" 493 (define_insn "*branch_upper_lower"
498 [(set (pc) 494 [(set (pc)
499 (if_then_else 495 (if_then_else
500 (match_operator 0 "equality_operator" 496 (match_operator 1 "equality_operator"
501 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 497 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
502 (match_operand 3 "const_int_operand")] 498 (match_operand 3 "const_int_operand")]
503 UNSPEC_SINGLE_CC) 499 UNSPEC_SINGLE_CC)
504 (const_int 0)]) 500 (const_int 0)])
505 (label_ref (match_operand 1 "" "")) 501 (label_ref (match_operand 0 "" ""))
506 (pc)))] 502 (pc)))]
507 "TARGET_HARD_FLOAT" 503 "TARGET_HARD_FLOAT"
508 { 504 {
509 operands[2] 505 operands[2]
510 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 506 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
511 return mips_output_conditional_branch (insn, operands, 507 return mips_output_conditional_branch (insn, operands,
512 MIPS_BRANCH ("b%F0", "%2,%1"), 508 MIPS_BRANCH ("b%F1", "%2,%0"),
513 MIPS_BRANCH ("b%W0", "%2,%1")); 509 MIPS_BRANCH ("b%W1", "%2,%0"));
514 } 510 }
515 [(set_attr "type" "branch") 511 [(set_attr "type" "branch")])
516 (set_attr "mode" "none")])
517 512
518 ; As above, but with the sense of the condition reversed. 513 ; As above, but with the sense of the condition reversed.
519 (define_insn "*branch_upper_lower_inverted" 514 (define_insn "*branch_upper_lower_inverted"
520 [(set (pc) 515 [(set (pc)
521 (if_then_else 516 (if_then_else
522 (match_operator 0 "equality_operator" 517 (match_operator 1 "equality_operator"
523 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 518 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
524 (match_operand 3 "const_int_operand")] 519 (match_operand 3 "const_int_operand")]
525 UNSPEC_SINGLE_CC) 520 UNSPEC_SINGLE_CC)
526 (const_int 0)]) 521 (const_int 0)])
527 (pc) 522 (pc)
528 (label_ref (match_operand 1 "" ""))))] 523 (label_ref (match_operand 0 "" ""))))]
529 "TARGET_HARD_FLOAT" 524 "TARGET_HARD_FLOAT"
530 { 525 {
531 operands[2] 526 operands[2]
532 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 527 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
533 return mips_output_conditional_branch (insn, operands, 528 return mips_output_conditional_branch (insn, operands,
534 MIPS_BRANCH ("b%W0", "%2,%1"), 529 MIPS_BRANCH ("b%W1", "%2,%0"),
535 MIPS_BRANCH ("b%F0", "%2,%1")); 530 MIPS_BRANCH ("b%F1", "%2,%0"));
536 } 531 }
537 [(set_attr "type" "branch") 532 [(set_attr "type" "branch")])
538 (set_attr "mode" "none")])
539 533
540 ;---------------------------------------------------------------------------- 534 ;----------------------------------------------------------------------------
541 ; Floating Point Reduced Precision Reciprocal Square Root Instructions. 535 ; Floating Point Reduced Precision Reciprocal Square Root Instructions.
542 ;---------------------------------------------------------------------------- 536 ;----------------------------------------------------------------------------
543 537