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comparison gcc/config/rs6000/spe.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children
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52:c156f1bd5cd9 55:77e2b8dfacca
1 ;; e500 SPE description 1 ;; e500 SPE description
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008 2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) 4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
97 "efsdiv %0,%1,%2" 97 "efsdiv %0,%1,%2"
98 [(set_attr "type" "vecfdiv")]) 98 [(set_attr "type" "vecfdiv")])
99 99
100 ;; Floating point conversion instructions. 100 ;; Floating point conversion instructions.
101 101
102 (define_insn "fixuns_truncdfsi2" 102 (define_insn "spe_fixuns_truncdfsi2"
103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
104 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] 104 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
105 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" 105 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
106 "efdctuiz %0,%1" 106 "efdctuiz %0,%1"
107 [(set_attr "type" "fp")]) 107 [(set_attr "type" "fp")])
162 "efdcfsi %0,%1" 162 "efdcfsi %0,%1"
163 [(set_attr "type" "fp")]) 163 [(set_attr "type" "fp")])
164 164
165 ;; SPE SIMD instructions 165 ;; SPE SIMD instructions
166 166
167 (define_insn "spe_evabs" 167 (define_insn "absv2si2"
168 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 168 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
169 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 169 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
170 "TARGET_SPE" 170 "TARGET_SPE"
171 "evabs %0,%1" 171 "evabs %0,%1"
172 [(set_attr "type" "vecsimple") 172 [(set_attr "type" "vecsimple")
179 "TARGET_SPE" 179 "TARGET_SPE"
180 "evandc %0,%1,%2" 180 "evandc %0,%1,%2"
181 [(set_attr "type" "vecsimple") 181 [(set_attr "type" "vecsimple")
182 (set_attr "length" "4")]) 182 (set_attr "length" "4")])
183 183
184 (define_insn "spe_evand" 184 (define_insn "andv2si3"
185 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 185 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
186 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 186 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
187 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 187 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
188 "TARGET_SPE" 188 "TARGET_SPE"
189 "evand %0,%1,%2" 189 "evand %0,%1,%2"
1896 "TARGET_SPE" 1896 "TARGET_SPE"
1897 "evmwumi %0,%1,%2" 1897 "evmwumi %0,%1,%2"
1898 [(set_attr "type" "veccomplex") 1898 [(set_attr "type" "veccomplex")
1899 (set_attr "length" "4")]) 1899 (set_attr "length" "4")])
1900 1900
1901 (define_insn "spe_evaddw" 1901 (define_insn "addv2si3"
1902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1903 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1903 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1904 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1904 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1905 "TARGET_SPE" 1905 "TARGET_SPE"
1906 "evaddw %0,%1,%2" 1906 "evaddw %0,%1,%2"
1965 "TARGET_SPE" 1965 "TARGET_SPE"
1966 "evsubifw %0,%2,%1" 1966 "evsubifw %0,%2,%1"
1967 [(set_attr "type" "veccomplex") 1967 [(set_attr "type" "veccomplex")
1968 (set_attr "length" "4")]) 1968 (set_attr "length" "4")])
1969 1969
1970 (define_insn "spe_evsubfw" 1970 (define_insn "subv2si3"
1971 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1971 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1972 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1972 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1973 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1973 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1974 "TARGET_SPE" 1974 "TARGET_SPE"
1975 "evsubfw %0,%2,%1" 1975 "evsubfw %0,%2,%1"
2026 "TARGET_SPE" 2026 "TARGET_SPE"
2027 "evmra %0,%1" 2027 "evmra %0,%1"
2028 [(set_attr "type" "veccomplex") 2028 [(set_attr "type" "veccomplex")
2029 (set_attr "length" "4")]) 2029 (set_attr "length" "4")])
2030 2030
2031 (define_insn "spe_evdivws" 2031 (define_insn "divv2si3"
2032 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2032 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2033 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 2033 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2034 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) 2034 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2035 (clobber (reg:SI SPEFSCR_REGNO))] 2035 (clobber (reg:SI SPEFSCR_REGNO))]
2036 "TARGET_SPE" 2036 "TARGET_SPE"
3154 ;; Out-of-line prologues and epilogues. 3154 ;; Out-of-line prologues and epilogues.
3155 (define_insn "*save_gpregs_spe" 3155 (define_insn "*save_gpregs_spe"
3156 [(match_parallel 0 "any_parallel_operand" 3156 [(match_parallel 0 "any_parallel_operand"
3157 [(clobber (reg:P 65)) 3157 [(clobber (reg:P 65))
3158 (use (match_operand:P 1 "symbol_ref_operand" "s")) 3158 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3159 (use (match_operand:P 2 "gpc_reg_operand" "r")) 3159 (use (reg:P 11))
3160 (set (match_operand:V2SI 3 "memory_operand" "=m") 3160 (set (match_operand:V2SI 2 "memory_operand" "=m")
3161 (match_operand:V2SI 4 "gpc_reg_operand" "r"))])] 3161 (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
3162 "TARGET_SPE_ABI" 3162 "TARGET_SPE_ABI"
3163 "bl %z1" 3163 "bl %z1"
3164 [(set_attr "type" "branch") 3164 [(set_attr "type" "branch")
3165 (set_attr "length" "4")]) 3165 (set_attr "length" "4")])
3166 3166
3167 (define_insn "*restore_gpregs_spe" 3167 (define_insn "*restore_gpregs_spe"
3168 [(match_parallel 0 "any_parallel_operand" 3168 [(match_parallel 0 "any_parallel_operand"
3169 [(clobber (reg:P 65)) 3169 [(clobber (reg:P 65))
3170 (use (match_operand:P 1 "symbol_ref_operand" "s")) 3170 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3171 (use (match_operand:P 2 "gpc_reg_operand" "r")) 3171 (use (reg:P 11))
3172 (set (match_operand:V2SI 3 "gpc_reg_operand" "=r") 3172 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3173 (match_operand:V2SI 4 "memory_operand" "m"))])] 3173 (match_operand:V2SI 3 "memory_operand" "m"))])]
3174 "TARGET_SPE_ABI" 3174 "TARGET_SPE_ABI"
3175 "bl %z1" 3175 "bl %z1"
3176 [(set_attr "type" "branch") 3176 [(set_attr "type" "branch")
3177 (set_attr "length" "4")]) 3177 (set_attr "length" "4")])
3178 3178
3179 (define_insn "*return_and_restore_gpregs_spe" 3179 (define_insn "*return_and_restore_gpregs_spe"
3180 [(match_parallel 0 "any_parallel_operand" 3180 [(match_parallel 0 "any_parallel_operand"
3181 [(return) 3181 [(return)
3182 (clobber (reg:P 65)) 3182 (clobber (reg:P 65))
3183 (use (match_operand:P 1 "symbol_ref_operand" "s")) 3183 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3184 (use (match_operand:P 2 "gpc_reg_operand" "r")) 3184 (use (reg:P 11))
3185 (set (match_operand:V2SI 3 "gpc_reg_operand" "=r") 3185 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3186 (match_operand:V2SI 4 "memory_operand" "m"))])] 3186 (match_operand:V2SI 3 "memory_operand" "m"))])]
3187 "TARGET_SPE_ABI" 3187 "TARGET_SPE_ABI"
3188 "b %z1" 3188 "b %z1"
3189 [(set_attr "type" "branch") 3189 [(set_attr "type" "branch")
3190 (set_attr "length" "4")]) 3190 (set_attr "length" "4")])