Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/spe.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children |
| rev | line source |
|---|---|
| 0 | 1 ;; e500 SPE description |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
| 0 | 3 ;; Free Software Foundation, Inc. |
| 4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) | |
| 5 | |
| 6 ;; This file is part of GCC. | |
| 7 | |
| 8 ;; GCC is free software; you can redistribute it and/or modify it | |
| 9 ;; under the terms of the GNU General Public License as published | |
| 10 ;; by the Free Software Foundation; either version 3, or (at your | |
| 11 ;; option) any later version. | |
| 12 | |
| 13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 ;; License for more details. | |
| 17 | |
| 18 ;; You should have received a copy of the GNU General Public License | |
| 19 ;; along with GCC; see the file COPYING3. If not see | |
| 20 ;; <http://www.gnu.org/licenses/>. | |
| 21 | |
| 22 (define_constants | |
| 23 [(CMPDFEQ_GPR 1006) | |
| 24 (TSTDFEQ_GPR 1007) | |
| 25 (CMPDFGT_GPR 1008) | |
| 26 (TSTDFGT_GPR 1009) | |
| 27 (CMPDFLT_GPR 1010) | |
| 28 (TSTDFLT_GPR 1011) | |
| 29 (CMPTFEQ_GPR 1012) | |
| 30 (TSTTFEQ_GPR 1013) | |
| 31 (CMPTFGT_GPR 1014) | |
| 32 (TSTTFGT_GPR 1015) | |
| 33 (CMPTFLT_GPR 1016) | |
| 34 (TSTTFLT_GPR 1017) | |
| 35 (E500_CR_IOR_COMPARE 1018) | |
| 36 ]) | |
| 37 | |
| 38 ;; Modes using a 64-bit register. | |
| 39 (define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI]) | |
| 40 | |
| 41 ;; Likewise, but allow TFmode (two registers) as well. | |
| 42 (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF]) | |
| 43 | |
| 44 ;; DImode and TImode. | |
| 45 (define_mode_iterator DITI [DI TI]) | |
| 46 | |
| 47 (define_insn "*negsf2_gpr" | |
| 48 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 49 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
| 50 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 51 "efsneg %0,%1" | |
| 52 [(set_attr "type" "fpsimple")]) | |
| 53 | |
| 54 (define_insn "*abssf2_gpr" | |
| 55 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 56 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
| 57 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 58 "efsabs %0,%1" | |
| 59 [(set_attr "type" "fpsimple")]) | |
| 60 | |
| 61 (define_insn "*nabssf2_gpr" | |
| 62 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 63 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] | |
| 64 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 65 "efsnabs %0,%1" | |
| 66 [(set_attr "type" "fpsimple")]) | |
| 67 | |
| 68 (define_insn "*addsf3_gpr" | |
| 69 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 70 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
| 71 (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
| 72 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 73 "efsadd %0,%1,%2" | |
| 74 [(set_attr "type" "fp")]) | |
| 75 | |
| 76 (define_insn "*subsf3_gpr" | |
| 77 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 78 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 79 (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
| 80 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 81 "efssub %0,%1,%2" | |
| 82 [(set_attr "type" "fp")]) | |
| 83 | |
| 84 (define_insn "*mulsf3_gpr" | |
| 85 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 86 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
| 87 (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
| 88 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 89 "efsmul %0,%1,%2" | |
| 90 [(set_attr "type" "fp")]) | |
| 91 | |
| 92 (define_insn "*divsf3_gpr" | |
| 93 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 94 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 95 (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
| 96 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 97 "efsdiv %0,%1,%2" | |
| 98 [(set_attr "type" "vecfdiv")]) | |
| 99 | |
| 100 ;; Floating point conversion instructions. | |
| 101 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
102 (define_insn "spe_fixuns_truncdfsi2" |
| 0 | 103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
| 104 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
| 105 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 106 "efdctuiz %0,%1" | |
| 107 [(set_attr "type" "fp")]) | |
| 108 | |
| 109 (define_insn "spe_extendsfdf2" | |
| 110 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 111 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
| 112 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 113 "efdcfs %0,%1" | |
| 114 [(set_attr "type" "fp")]) | |
| 115 | |
| 116 (define_insn "spe_fixuns_truncsfsi2" | |
| 117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
| 118 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
| 119 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 120 "efsctuiz %0,%1" | |
| 121 [(set_attr "type" "fp")]) | |
| 122 | |
| 123 (define_insn "spe_fix_truncsfsi2" | |
| 124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
| 125 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
| 126 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 127 "efsctsiz %0,%1" | |
| 128 [(set_attr "type" "fp")]) | |
| 129 | |
| 130 (define_insn "spe_fix_truncdfsi2" | |
| 131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
| 132 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
| 133 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 134 "efdctsiz %0,%1" | |
| 135 [(set_attr "type" "fp")]) | |
| 136 | |
| 137 (define_insn "spe_floatunssisf2" | |
| 138 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 139 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
| 140 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 141 "efscfui %0,%1" | |
| 142 [(set_attr "type" "fp")]) | |
| 143 | |
| 144 (define_insn "spe_floatunssidf2" | |
| 145 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 146 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
| 147 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 148 "efdcfui %0,%1" | |
| 149 [(set_attr "type" "fp")]) | |
| 150 | |
| 151 (define_insn "spe_floatsisf2" | |
| 152 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 153 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
| 154 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 155 "efscfsi %0,%1" | |
| 156 [(set_attr "type" "fp")]) | |
| 157 | |
| 158 (define_insn "spe_floatsidf2" | |
| 159 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 160 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
| 161 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 162 "efdcfsi %0,%1" | |
| 163 [(set_attr "type" "fp")]) | |
| 164 | |
| 165 ;; SPE SIMD instructions | |
| 166 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
167 (define_insn "absv2si2" |
| 0 | 168 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
| 169 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
| 170 "TARGET_SPE" | |
| 171 "evabs %0,%1" | |
| 172 [(set_attr "type" "vecsimple") | |
| 173 (set_attr "length" "4")]) | |
| 174 | |
| 175 (define_insn "spe_evandc" | |
| 176 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 177 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 178 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
| 179 "TARGET_SPE" | |
| 180 "evandc %0,%1,%2" | |
| 181 [(set_attr "type" "vecsimple") | |
| 182 (set_attr "length" "4")]) | |
| 183 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
184 (define_insn "andv2si3" |
| 0 | 185 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
| 186 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 187 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
| 188 "TARGET_SPE" | |
| 189 "evand %0,%1,%2" | |
| 190 [(set_attr "type" "vecsimple") | |
| 191 (set_attr "length" "4")]) | |
| 192 | |
| 193 ;; Vector compare instructions | |
| 194 | |
| 195 (define_insn "spe_evcmpeq" | |
| 196 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 197 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 198 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] | |
| 199 "TARGET_SPE" | |
| 200 "evcmpeq %0,%1,%2" | |
| 201 [(set_attr "type" "veccmp") | |
| 202 (set_attr "length" "4")]) | |
| 203 | |
| 204 (define_insn "spe_evcmpgts" | |
| 205 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 206 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 207 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] | |
| 208 "TARGET_SPE" | |
| 209 "evcmpgts %0,%1,%2" | |
| 210 [(set_attr "type" "veccmp") | |
| 211 (set_attr "length" "4")]) | |
| 212 | |
| 213 (define_insn "spe_evcmpgtu" | |
| 214 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 215 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 216 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] | |
| 217 "TARGET_SPE" | |
| 218 "evcmpgtu %0,%1,%2" | |
| 219 [(set_attr "type" "veccmp") | |
| 220 (set_attr "length" "4")]) | |
| 221 | |
| 222 (define_insn "spe_evcmplts" | |
| 223 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 224 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 225 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] | |
| 226 "TARGET_SPE" | |
| 227 "evcmplts %0,%1,%2" | |
| 228 [(set_attr "type" "veccmp") | |
| 229 (set_attr "length" "4")]) | |
| 230 | |
| 231 (define_insn "spe_evcmpltu" | |
| 232 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 233 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 234 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] | |
| 235 "TARGET_SPE" | |
| 236 "evcmpltu %0,%1,%2" | |
| 237 [(set_attr "type" "veccmp") | |
| 238 (set_attr "length" "4")]) | |
| 239 | |
| 240 ;; Floating point vector compare instructions | |
| 241 | |
| 242 (define_insn "spe_evfscmpeq" | |
| 243 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 244 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 245 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) | |
| 246 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 247 "TARGET_SPE" | |
| 248 "evfscmpeq %0,%1,%2" | |
| 249 [(set_attr "type" "veccmp") | |
| 250 (set_attr "length" "4")]) | |
| 251 | |
| 252 (define_insn "spe_evfscmpgt" | |
| 253 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 254 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 255 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) | |
| 256 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 257 "TARGET_SPE" | |
| 258 "evfscmpgt %0,%1,%2" | |
| 259 [(set_attr "type" "veccmp") | |
| 260 (set_attr "length" "4")]) | |
| 261 | |
| 262 (define_insn "spe_evfscmplt" | |
| 263 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 264 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 265 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) | |
| 266 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 267 "TARGET_SPE" | |
| 268 "evfscmplt %0,%1,%2" | |
| 269 [(set_attr "type" "veccmp") | |
| 270 (set_attr "length" "4")]) | |
| 271 | |
| 272 (define_insn "spe_evfststeq" | |
| 273 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 274 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 275 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] | |
| 276 "TARGET_SPE" | |
| 277 "evfststeq %0,%1,%2" | |
| 278 [(set_attr "type" "veccmp") | |
| 279 (set_attr "length" "4")]) | |
| 280 | |
| 281 (define_insn "spe_evfststgt" | |
| 282 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 283 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 284 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] | |
| 285 "TARGET_SPE" | |
| 286 "evfststgt %0,%1,%2" | |
| 287 [(set_attr "type" "veccmp") | |
| 288 (set_attr "length" "4")]) | |
| 289 | |
| 290 (define_insn "spe_evfststlt" | |
| 291 [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
| 292 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 293 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] | |
| 294 "TARGET_SPE" | |
| 295 "evfststlt %0,%1,%2" | |
| 296 [(set_attr "type" "veccmp") | |
| 297 (set_attr "length" "4")]) | |
| 298 | |
| 299 ;; End of vector compare instructions | |
| 300 | |
| 301 (define_insn "spe_evcntlsw" | |
| 302 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 303 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] | |
| 304 "TARGET_SPE" | |
| 305 "evcntlsw %0,%1" | |
| 306 [(set_attr "type" "vecsimple") | |
| 307 (set_attr "length" "4")]) | |
| 308 | |
| 309 (define_insn "spe_evcntlzw" | |
| 310 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 311 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] | |
| 312 "TARGET_SPE" | |
| 313 "evcntlzw %0,%1" | |
| 314 [(set_attr "type" "vecsimple") | |
| 315 (set_attr "length" "4")]) | |
| 316 | |
| 317 (define_insn "spe_eveqv" | |
| 318 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 319 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 320 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
| 321 "TARGET_SPE" | |
| 322 "eveqv %0,%1,%2" | |
| 323 [(set_attr "type" "vecsimple") | |
| 324 (set_attr "length" "4")]) | |
| 325 | |
| 326 (define_insn "spe_evextsb" | |
| 327 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 328 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] | |
| 329 "TARGET_SPE" | |
| 330 "evextsb %0,%1" | |
| 331 [(set_attr "type" "vecsimple") | |
| 332 (set_attr "length" "4")]) | |
| 333 | |
| 334 (define_insn "spe_evextsh" | |
| 335 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 336 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] | |
| 337 "TARGET_SPE" | |
| 338 "evextsh %0,%1" | |
| 339 [(set_attr "type" "vecsimple") | |
| 340 (set_attr "length" "4")]) | |
| 341 | |
| 342 (define_insn "spe_evlhhesplat" | |
| 343 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 344 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 345 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 346 (unspec [(const_int 0)] 509)] | |
| 347 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 348 "evlhhesplat %0,%2*2(%1)" | |
| 349 [(set_attr "type" "vecload") | |
| 350 (set_attr "length" "4")]) | |
| 351 | |
| 352 (define_insn "spe_evlhhesplatx" | |
| 353 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 354 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 355 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 356 (unspec [(const_int 0)] 510)] | |
| 357 "TARGET_SPE" | |
| 358 "evlhhesplatx %0,%1,%2" | |
| 359 [(set_attr "type" "vecload") | |
| 360 (set_attr "length" "4")]) | |
| 361 | |
| 362 (define_insn "spe_evlhhossplat" | |
| 363 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 364 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 365 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 366 (unspec [(const_int 0)] 511)] | |
| 367 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 368 "evlhhossplat %0,%2*2(%1)" | |
| 369 [(set_attr "type" "vecload") | |
| 370 (set_attr "length" "4")]) | |
| 371 | |
| 372 (define_insn "spe_evlhhossplatx" | |
| 373 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 374 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 375 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 376 (unspec [(const_int 0)] 512)] | |
| 377 "TARGET_SPE" | |
| 378 "evlhhossplatx %0,%1,%2" | |
| 379 [(set_attr "type" "vecload") | |
| 380 (set_attr "length" "4")]) | |
| 381 | |
| 382 (define_insn "spe_evlhhousplat" | |
| 383 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 384 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 385 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 386 (unspec [(const_int 0)] 513)] | |
| 387 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 388 "evlhhousplat %0,%2*2(%1)" | |
| 389 [(set_attr "type" "vecload") | |
| 390 (set_attr "length" "4")]) | |
| 391 | |
| 392 (define_insn "spe_evlhhousplatx" | |
| 393 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 394 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 395 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 396 (unspec [(const_int 0)] 514)] | |
| 397 "TARGET_SPE" | |
| 398 "evlhhousplatx %0,%1,%2" | |
| 399 [(set_attr "type" "vecload") | |
| 400 (set_attr "length" "4")]) | |
| 401 | |
| 402 (define_insn "spe_evlwhsplat" | |
| 403 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 404 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 405 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 406 (unspec [(const_int 0)] 515)] | |
| 407 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 408 "evlwhsplat %0,%2*4(%1)" | |
| 409 [(set_attr "type" "vecload") | |
| 410 (set_attr "length" "4")]) | |
| 411 | |
| 412 (define_insn "spe_evlwhsplatx" | |
| 413 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 414 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 415 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 416 (unspec [(const_int 0)] 516)] | |
| 417 "TARGET_SPE" | |
| 418 "evlwhsplatx %0,%1,%2" | |
| 419 [(set_attr "type" "vecload") | |
| 420 (set_attr "length" "4")]) | |
| 421 | |
| 422 (define_insn "spe_evlwwsplat" | |
| 423 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 424 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 425 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 426 (unspec [(const_int 0)] 517)] | |
| 427 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 428 "evlwwsplat %0,%2*4(%1)" | |
| 429 [(set_attr "type" "vecload") | |
| 430 (set_attr "length" "4")]) | |
| 431 | |
| 432 (define_insn "spe_evlwwsplatx" | |
| 433 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 434 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 435 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 436 (unspec [(const_int 0)] 518)] | |
| 437 "TARGET_SPE" | |
| 438 "evlwwsplatx %0,%1,%2" | |
| 439 [(set_attr "type" "vecload") | |
| 440 (set_attr "length" "4")]) | |
| 441 | |
| 442 (define_insn "spe_evmergehi" | |
| 443 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 444 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 445 (vec_select:V2SI | |
| 446 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 447 (parallel [(const_int 1) | |
| 448 (const_int 0)])) | |
| 449 (const_int 2)))] | |
| 450 "TARGET_SPE" | |
| 451 "evmergehi %0,%1,%2" | |
| 452 [(set_attr "type" "vecsimple") | |
| 453 (set_attr "length" "4")]) | |
| 454 | |
| 455 (define_insn "spe_evmergehilo" | |
| 456 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 457 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 458 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 459 (const_int 2)))] | |
| 460 "TARGET_SPE" | |
| 461 "evmergehilo %0,%1,%2" | |
| 462 [(set_attr "type" "vecsimple") | |
| 463 (set_attr "length" "4")]) | |
| 464 | |
| 465 (define_insn "spe_evmergelo" | |
| 466 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 467 (vec_merge:V2SI (vec_select:V2SI | |
| 468 (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 469 (parallel [(const_int 1) | |
| 470 (const_int 0)])) | |
| 471 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 472 (const_int 2)))] | |
| 473 "TARGET_SPE" | |
| 474 "evmergelo %0,%1,%2" | |
| 475 [(set_attr "type" "vecsimple") | |
| 476 (set_attr "length" "4")]) | |
| 477 | |
| 478 (define_insn "spe_evmergelohi" | |
| 479 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 480 (vec_merge:V2SI (vec_select:V2SI | |
| 481 (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 482 (parallel [(const_int 1) | |
| 483 (const_int 0)])) | |
| 484 (vec_select:V2SI | |
| 485 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 486 (parallel [(const_int 1) | |
| 487 (const_int 0)])) | |
| 488 (const_int 2)))] | |
| 489 "TARGET_SPE" | |
| 490 "evmergelohi %0,%1,%2" | |
| 491 [(set_attr "type" "vecsimple") | |
| 492 (set_attr "length" "4")]) | |
| 493 | |
| 494 (define_insn "spe_evnand" | |
| 495 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 496 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 497 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
| 498 "TARGET_SPE" | |
| 499 "evnand %0,%1,%2" | |
| 500 [(set_attr "type" "vecsimple") | |
| 501 (set_attr "length" "4")]) | |
| 502 | |
| 503 (define_insn "negv2si2" | |
| 504 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 505 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
| 506 "TARGET_SPE" | |
| 507 "evneg %0,%1" | |
| 508 [(set_attr "type" "vecsimple") | |
| 509 (set_attr "length" "4")]) | |
| 510 | |
| 511 (define_insn "spe_evnor" | |
| 512 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 513 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 514 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
| 515 "TARGET_SPE" | |
| 516 "evnor %0,%1,%2" | |
| 517 [(set_attr "type" "vecsimple") | |
| 518 (set_attr "length" "4")]) | |
| 519 | |
| 520 (define_insn "spe_evorc" | |
| 521 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 522 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 523 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
| 524 "TARGET_SPE" | |
| 525 "evorc %0,%1,%2" | |
| 526 [(set_attr "type" "vecsimple") | |
| 527 (set_attr "length" "4")]) | |
| 528 | |
| 529 (define_insn "spe_evor" | |
| 530 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 531 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 532 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
| 533 "TARGET_SPE" | |
| 534 "evor %0,%1,%2" | |
| 535 [(set_attr "type" "vecsimple") | |
| 536 (set_attr "length" "4")]) | |
| 537 | |
| 538 (define_insn "spe_evrlwi" | |
| 539 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 540 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 541 (match_operand:QI 2 "immediate_operand" "i")] 519))] | |
| 542 "TARGET_SPE" | |
| 543 "evrlwi %0,%1,%2" | |
| 544 [(set_attr "type" "vecsimple") | |
| 545 (set_attr "length" "4")]) | |
| 546 | |
| 547 (define_insn "spe_evrlw" | |
| 548 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 549 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 550 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] | |
| 551 "TARGET_SPE" | |
| 552 "evrlw %0,%1,%2" | |
| 553 [(set_attr "type" "veccomplex") | |
| 554 (set_attr "length" "4")]) | |
| 555 | |
| 556 (define_insn "spe_evrndw" | |
| 557 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 558 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] | |
| 559 "TARGET_SPE" | |
| 560 "evrndw %0,%1" | |
| 561 [(set_attr "type" "vecsimple") | |
| 562 (set_attr "length" "4")]) | |
| 563 | |
| 564 (define_insn "spe_evsel" | |
| 565 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 566 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 567 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 568 (match_operand:CC 3 "cc_reg_operand" "y")] 522))] | |
| 569 "TARGET_SPE" | |
| 570 "evsel %0,%1,%2,%3" | |
| 571 [(set_attr "type" "veccmp") | |
| 572 (set_attr "length" "4")]) | |
| 573 | |
| 574 (define_insn "spe_evsel_fs" | |
| 575 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 576 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 577 (match_operand:V2SF 2 "gpc_reg_operand" "r") | |
| 578 (match_operand:CC 3 "cc_reg_operand" "y")] 725))] | |
| 579 "TARGET_SPE" | |
| 580 "evsel %0,%1,%2,%3" | |
| 581 [(set_attr "type" "veccmp") | |
| 582 (set_attr "length" "4")]) | |
| 583 | |
| 584 (define_insn "spe_evslwi" | |
| 585 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 586 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 587 (match_operand:QI 2 "immediate_operand" "i")] | |
| 588 523))] | |
| 589 "TARGET_SPE" | |
| 590 "evslwi %0,%1,%2" | |
| 591 [(set_attr "type" "vecsimple") | |
| 592 (set_attr "length" "4")]) | |
| 593 | |
| 594 (define_insn "spe_evslw" | |
| 595 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 596 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 597 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] | |
| 598 "TARGET_SPE" | |
| 599 "evslw %0,%1,%2" | |
| 600 [(set_attr "type" "vecsimple") | |
| 601 (set_attr "length" "4")]) | |
| 602 | |
| 603 (define_insn "spe_evsrwis" | |
| 604 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 605 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 606 (match_operand:QI 2 "immediate_operand" "i")] | |
| 607 525))] | |
| 608 "TARGET_SPE" | |
| 609 "evsrwis %0,%1,%2" | |
| 610 [(set_attr "type" "vecsimple") | |
| 611 (set_attr "length" "4")]) | |
| 612 | |
| 613 (define_insn "spe_evsrwiu" | |
| 614 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 615 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 616 (match_operand:QI 2 "immediate_operand" "i")] | |
| 617 526))] | |
| 618 "TARGET_SPE" | |
| 619 "evsrwiu %0,%1,%2" | |
| 620 [(set_attr "type" "vecsimple") | |
| 621 (set_attr "length" "4")]) | |
| 622 | |
| 623 (define_insn "spe_evsrws" | |
| 624 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 625 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 626 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] | |
| 627 "TARGET_SPE" | |
| 628 "evsrws %0,%1,%2" | |
| 629 [(set_attr "type" "vecsimple") | |
| 630 (set_attr "length" "4")]) | |
| 631 | |
| 632 (define_insn "spe_evsrwu" | |
| 633 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 634 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 635 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] | |
| 636 "TARGET_SPE" | |
| 637 "evsrwu %0,%1,%2" | |
| 638 [(set_attr "type" "vecsimple") | |
| 639 (set_attr "length" "4")]) | |
| 640 | |
| 641 ;; vector xors | |
| 642 | |
| 643 (define_insn "xorv2si3" | |
| 644 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 645 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 646 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
| 647 "TARGET_SPE" | |
| 648 "evxor %0,%1,%2" | |
| 649 [(set_attr "type" "vecsimple") | |
| 650 (set_attr "length" "4")]) | |
| 651 | |
| 652 (define_insn "xorv4hi3" | |
| 653 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") | |
| 654 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r") | |
| 655 (match_operand:V4HI 2 "gpc_reg_operand" "r")))] | |
| 656 "TARGET_SPE" | |
| 657 "evxor %0,%1,%2" | |
| 658 [(set_attr "type" "vecsimple") | |
| 659 (set_attr "length" "4")]) | |
| 660 | |
| 661 (define_insn "xorv1di3" | |
| 662 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") | |
| 663 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r") | |
| 664 (match_operand:V1DI 2 "gpc_reg_operand" "r")))] | |
| 665 "TARGET_SPE" | |
| 666 "evxor %0,%1,%2" | |
| 667 [(set_attr "type" "vecsimple") | |
| 668 (set_attr "length" "4")]) | |
| 669 | |
| 670 ;; end of vector xors | |
| 671 | |
| 672 (define_insn "spe_evfsabs" | |
| 673 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 674 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
| 675 "TARGET_SPE" | |
| 676 "evfsabs %0,%1" | |
| 677 [(set_attr "type" "vecsimple") | |
| 678 (set_attr "length" "4")]) | |
| 679 | |
| 680 (define_insn "spe_evfsadd" | |
| 681 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 682 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 683 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
| 684 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 685 "TARGET_SPE" | |
| 686 "evfsadd %0,%1,%2" | |
| 687 [(set_attr "type" "vecfloat") | |
| 688 (set_attr "length" "4")]) | |
| 689 | |
| 690 (define_insn "spe_evfscfsf" | |
| 691 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 692 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] | |
| 693 "TARGET_SPE" | |
| 694 "evfscfsf %0,%1" | |
| 695 [(set_attr "type" "vecfloat") | |
| 696 (set_attr "length" "4")]) | |
| 697 | |
| 698 (define_insn "spe_evfscfsi" | |
| 699 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 700 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
| 701 "TARGET_SPE" | |
| 702 "evfscfsi %0,%1" | |
| 703 [(set_attr "type" "vecfloat") | |
| 704 (set_attr "length" "4")]) | |
| 705 | |
| 706 (define_insn "spe_evfscfuf" | |
| 707 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 708 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] | |
| 709 "TARGET_SPE" | |
| 710 "evfscfuf %0,%1" | |
| 711 [(set_attr "type" "vecfloat") | |
| 712 (set_attr "length" "4")]) | |
| 713 | |
| 714 (define_insn "spe_evfscfui" | |
| 715 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 716 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] | |
| 717 "TARGET_SPE" | |
| 718 "evfscfui %0,%1" | |
| 719 [(set_attr "type" "vecfloat") | |
| 720 (set_attr "length" "4")]) | |
| 721 | |
| 722 (define_insn "spe_evfsctsf" | |
| 723 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 724 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] | |
| 725 "TARGET_SPE" | |
| 726 "evfsctsf %0,%1" | |
| 727 [(set_attr "type" "vecfloat") | |
| 728 (set_attr "length" "4")]) | |
| 729 | |
| 730 (define_insn "spe_evfsctsi" | |
| 731 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 732 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] | |
| 733 "TARGET_SPE" | |
| 734 "evfsctsi %0,%1" | |
| 735 [(set_attr "type" "vecfloat") | |
| 736 (set_attr "length" "4")]) | |
| 737 | |
| 738 (define_insn "spe_evfsctsiz" | |
| 739 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 740 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] | |
| 741 "TARGET_SPE" | |
| 742 "evfsctsiz %0,%1" | |
| 743 [(set_attr "type" "vecfloat") | |
| 744 (set_attr "length" "4")]) | |
| 745 | |
| 746 (define_insn "spe_evfsctuf" | |
| 747 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 748 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] | |
| 749 "TARGET_SPE" | |
| 750 "evfsctuf %0,%1" | |
| 751 [(set_attr "type" "vecfloat") | |
| 752 (set_attr "length" "4")]) | |
| 753 | |
| 754 (define_insn "spe_evfsctui" | |
| 755 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 756 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] | |
| 757 "TARGET_SPE" | |
| 758 "evfsctui %0,%1" | |
| 759 [(set_attr "type" "vecfloat") | |
| 760 (set_attr "length" "4")]) | |
| 761 | |
| 762 (define_insn "spe_evfsctuiz" | |
| 763 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 764 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] | |
| 765 "TARGET_SPE" | |
| 766 "evfsctuiz %0,%1" | |
| 767 [(set_attr "type" "vecfloat") | |
| 768 (set_attr "length" "4")]) | |
| 769 | |
| 770 (define_insn "spe_evfsdiv" | |
| 771 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 772 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 773 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
| 774 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 775 "TARGET_SPE" | |
| 776 "evfsdiv %0,%1,%2" | |
| 777 [(set_attr "type" "vecfdiv") | |
| 778 (set_attr "length" "4")]) | |
| 779 | |
| 780 (define_insn "spe_evfsmul" | |
| 781 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 782 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 783 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
| 784 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 785 "TARGET_SPE" | |
| 786 "evfsmul %0,%1,%2" | |
| 787 [(set_attr "type" "vecfloat") | |
| 788 (set_attr "length" "4")]) | |
| 789 | |
| 790 (define_insn "spe_evfsnabs" | |
| 791 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 792 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] | |
| 793 "TARGET_SPE" | |
| 794 "evfsnabs %0,%1" | |
| 795 [(set_attr "type" "vecsimple") | |
| 796 (set_attr "length" "4")]) | |
| 797 | |
| 798 (define_insn "spe_evfsneg" | |
| 799 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 800 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
| 801 "TARGET_SPE" | |
| 802 "evfsneg %0,%1" | |
| 803 [(set_attr "type" "vecsimple") | |
| 804 (set_attr "length" "4")]) | |
| 805 | |
| 806 (define_insn "spe_evfssub" | |
| 807 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
| 808 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
| 809 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
| 810 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 811 "TARGET_SPE" | |
| 812 "evfssub %0,%1,%2" | |
| 813 [(set_attr "type" "vecfloat") | |
| 814 (set_attr "length" "4")]) | |
| 815 | |
| 816 ;; SPE SIMD load instructions. | |
| 817 | |
| 818 ;; Only the hardware engineer who designed the SPE understands the | |
| 819 ;; plethora of load and store instructions ;-). We have no way of | |
| 820 ;; differentiating between them with RTL so use an unspec of const_int 0 | |
| 821 ;; to avoid identical RTL. | |
| 822 | |
| 823 (define_insn "spe_evldd" | |
| 824 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 825 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 826 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 827 (unspec [(const_int 0)] 544)] | |
| 828 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 829 "evldd %0,%2*8(%1)" | |
| 830 [(set_attr "type" "vecload") | |
| 831 (set_attr "length" "4")]) | |
| 832 | |
| 833 (define_insn "spe_evlddx" | |
| 834 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 835 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 836 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 837 (unspec [(const_int 0)] 545)] | |
| 838 "TARGET_SPE" | |
| 839 "evlddx %0,%1,%2" | |
| 840 [(set_attr "type" "vecload") | |
| 841 (set_attr "length" "4")]) | |
| 842 | |
| 843 (define_insn "spe_evldh" | |
| 844 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 845 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 846 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 847 (unspec [(const_int 0)] 546)] | |
| 848 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 849 "evldh %0,%2*8(%1)" | |
| 850 [(set_attr "type" "vecload") | |
| 851 (set_attr "length" "4")]) | |
| 852 | |
| 853 (define_insn "spe_evldhx" | |
| 854 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 855 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 856 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 857 (unspec [(const_int 0)] 547)] | |
| 858 "TARGET_SPE" | |
| 859 "evldhx %0,%1,%2" | |
| 860 [(set_attr "type" "vecload") | |
| 861 (set_attr "length" "4")]) | |
| 862 | |
| 863 (define_insn "spe_evldw" | |
| 864 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 865 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 866 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 867 (unspec [(const_int 0)] 548)] | |
| 868 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 869 "evldw %0,%2*8(%1)" | |
| 870 [(set_attr "type" "vecload") | |
| 871 (set_attr "length" "4")]) | |
| 872 | |
| 873 (define_insn "spe_evldwx" | |
| 874 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 875 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 876 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 877 (unspec [(const_int 0)] 549)] | |
| 878 "TARGET_SPE" | |
| 879 "evldwx %0,%1,%2" | |
| 880 [(set_attr "type" "vecload") | |
| 881 (set_attr "length" "4")]) | |
| 882 | |
| 883 (define_insn "spe_evlwhe" | |
| 884 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 885 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 886 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 887 (unspec [(const_int 0)] 550)] | |
| 888 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 889 "evlwhe %0,%2*4(%1)" | |
| 890 [(set_attr "type" "vecload") | |
| 891 (set_attr "length" "4")]) | |
| 892 | |
| 893 (define_insn "spe_evlwhex" | |
| 894 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 895 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 896 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 897 (unspec [(const_int 0)] 551)] | |
| 898 "TARGET_SPE" | |
| 899 "evlwhex %0,%1,%2" | |
| 900 [(set_attr "type" "vecload") | |
| 901 (set_attr "length" "4")]) | |
| 902 | |
| 903 (define_insn "spe_evlwhos" | |
| 904 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 905 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 906 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 907 (unspec [(const_int 0)] 552)] | |
| 908 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 909 "evlwhos %0,%2*4(%1)" | |
| 910 [(set_attr "type" "vecload") | |
| 911 (set_attr "length" "4")]) | |
| 912 | |
| 913 (define_insn "spe_evlwhosx" | |
| 914 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 915 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 916 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 917 (unspec [(const_int 0)] 553)] | |
| 918 "TARGET_SPE" | |
| 919 "evlwhosx %0,%1,%2" | |
| 920 [(set_attr "type" "vecload") | |
| 921 (set_attr "length" "4")]) | |
| 922 | |
| 923 (define_insn "spe_evlwhou" | |
| 924 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 925 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 926 (match_operand:QI 2 "immediate_operand" "i")))) | |
| 927 (unspec [(const_int 0)] 554)] | |
| 928 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
| 929 "evlwhou %0,%2*4(%1)" | |
| 930 [(set_attr "type" "vecload") | |
| 931 (set_attr "length" "4")]) | |
| 932 | |
| 933 (define_insn "spe_evlwhoux" | |
| 934 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 935 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
| 936 (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
| 937 (unspec [(const_int 0)] 555)] | |
| 938 "TARGET_SPE" | |
| 939 "evlwhoux %0,%1,%2" | |
| 940 [(set_attr "type" "vecload") | |
| 941 (set_attr "length" "4")]) | |
| 942 | |
| 943 (define_insn "spe_brinc" | |
| 944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
| 945 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") | |
| 946 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] | |
| 947 "TARGET_SPE" | |
| 948 "brinc %0,%1,%2" | |
| 949 [(set_attr "type" "brinc") | |
| 950 (set_attr "length" "4")]) | |
| 951 | |
| 952 (define_insn "spe_evmhegsmfaa" | |
| 953 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 954 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 955 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 956 (reg:V2SI SPE_ACC_REGNO)] 557)) | |
| 957 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 958 "TARGET_SPE" | |
| 959 "evmhegsmfaa %0,%1,%2" | |
| 960 [(set_attr "type" "veccomplex") | |
| 961 (set_attr "length" "4")]) | |
| 962 | |
| 963 (define_insn "spe_evmhegsmfan" | |
| 964 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 965 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 966 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 967 (reg:V2SI SPE_ACC_REGNO)] 558)) | |
| 968 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 969 "TARGET_SPE" | |
| 970 "evmhegsmfan %0,%1,%2" | |
| 971 [(set_attr "type" "veccomplex") | |
| 972 (set_attr "length" "4")]) | |
| 973 | |
| 974 (define_insn "spe_evmhegsmiaa" | |
| 975 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 976 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 977 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 978 (reg:V2SI SPE_ACC_REGNO)] 559)) | |
| 979 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 980 "TARGET_SPE" | |
| 981 "evmhegsmiaa %0,%1,%2" | |
| 982 [(set_attr "type" "veccomplex") | |
| 983 (set_attr "length" "4")]) | |
| 984 | |
| 985 (define_insn "spe_evmhegsmian" | |
| 986 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 987 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 988 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 989 (reg:V2SI SPE_ACC_REGNO)] 560)) | |
| 990 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 991 "TARGET_SPE" | |
| 992 "evmhegsmian %0,%1,%2" | |
| 993 [(set_attr "type" "veccomplex") | |
| 994 (set_attr "length" "4")]) | |
| 995 | |
| 996 (define_insn "spe_evmhegumiaa" | |
| 997 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 998 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 999 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1000 (reg:V2SI SPE_ACC_REGNO)] 561)) | |
| 1001 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1002 "TARGET_SPE" | |
| 1003 "evmhegumiaa %0,%1,%2" | |
| 1004 [(set_attr "type" "veccomplex") | |
| 1005 (set_attr "length" "4")]) | |
| 1006 | |
| 1007 (define_insn "spe_evmhegumian" | |
| 1008 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1009 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1010 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1011 (reg:V2SI SPE_ACC_REGNO)] 562)) | |
| 1012 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1013 "TARGET_SPE" | |
| 1014 "evmhegumian %0,%1,%2" | |
| 1015 [(set_attr "type" "veccomplex") | |
| 1016 (set_attr "length" "4")]) | |
| 1017 | |
| 1018 (define_insn "spe_evmhesmfaaw" | |
| 1019 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1020 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1021 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1022 (reg:V2SI SPE_ACC_REGNO)] 563)) | |
| 1023 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1024 "TARGET_SPE" | |
| 1025 "evmhesmfaaw %0,%1,%2" | |
| 1026 [(set_attr "type" "veccomplex") | |
| 1027 (set_attr "length" "4")]) | |
| 1028 | |
| 1029 (define_insn "spe_evmhesmfanw" | |
| 1030 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1031 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1032 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1033 (reg:V2SI SPE_ACC_REGNO)] 564)) | |
| 1034 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1035 "TARGET_SPE" | |
| 1036 "evmhesmfanw %0,%1,%2" | |
| 1037 [(set_attr "type" "veccomplex") | |
| 1038 (set_attr "length" "4")]) | |
| 1039 | |
| 1040 (define_insn "spe_evmhesmfa" | |
| 1041 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1042 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1043 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) | |
| 1044 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1045 "TARGET_SPE" | |
| 1046 "evmhesmfa %0,%1,%2" | |
| 1047 [(set_attr "type" "veccomplex") | |
| 1048 (set_attr "length" "4")]) | |
| 1049 | |
| 1050 (define_insn "spe_evmhesmf" | |
| 1051 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1052 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1053 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] | |
| 1054 "TARGET_SPE" | |
| 1055 "evmhesmf %0,%1,%2" | |
| 1056 [(set_attr "type" "veccomplex") | |
| 1057 (set_attr "length" "4")]) | |
| 1058 | |
| 1059 (define_insn "spe_evmhesmiaaw" | |
| 1060 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1061 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1062 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1063 (reg:V2SI SPE_ACC_REGNO)] 567)) | |
| 1064 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1065 "TARGET_SPE" | |
| 1066 "evmhesmiaaw %0,%1,%2" | |
| 1067 [(set_attr "type" "veccomplex") | |
| 1068 (set_attr "length" "4")]) | |
| 1069 | |
| 1070 (define_insn "spe_evmhesmianw" | |
| 1071 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1072 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1073 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1074 (reg:V2SI SPE_ACC_REGNO)] 568)) | |
| 1075 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1076 "TARGET_SPE" | |
| 1077 "evmhesmianw %0,%1,%2" | |
| 1078 [(set_attr "type" "veccomplex") | |
| 1079 (set_attr "length" "4")]) | |
| 1080 | |
| 1081 (define_insn "spe_evmhesmia" | |
| 1082 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1083 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1084 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) | |
| 1085 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1086 "TARGET_SPE" | |
| 1087 "evmhesmia %0,%1,%2" | |
| 1088 [(set_attr "type" "veccomplex") | |
| 1089 (set_attr "length" "4")]) | |
| 1090 | |
| 1091 (define_insn "spe_evmhesmi" | |
| 1092 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1093 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1094 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] | |
| 1095 "TARGET_SPE" | |
| 1096 "evmhesmi %0,%1,%2" | |
| 1097 [(set_attr "type" "veccomplex") | |
| 1098 (set_attr "length" "4")]) | |
| 1099 | |
| 1100 (define_insn "spe_evmhessfaaw" | |
| 1101 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1102 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1103 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1104 (reg:V2SI SPE_ACC_REGNO)] 571)) | |
| 1105 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1106 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1107 "TARGET_SPE" | |
| 1108 "evmhessfaaw %0,%1,%2" | |
| 1109 [(set_attr "type" "veccomplex") | |
| 1110 (set_attr "length" "4")]) | |
| 1111 | |
| 1112 (define_insn "spe_evmhessfanw" | |
| 1113 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1114 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1115 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1116 (reg:V2SI SPE_ACC_REGNO)] 572)) | |
| 1117 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1118 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1119 "TARGET_SPE" | |
| 1120 "evmhessfanw %0,%1,%2" | |
| 1121 [(set_attr "type" "veccomplex") | |
| 1122 (set_attr "length" "4")]) | |
| 1123 | |
| 1124 (define_insn "spe_evmhessfa" | |
| 1125 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1126 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1127 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) | |
| 1128 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1129 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1130 "TARGET_SPE" | |
| 1131 "evmhessfa %0,%1,%2" | |
| 1132 [(set_attr "type" "veccomplex") | |
| 1133 (set_attr "length" "4")]) | |
| 1134 | |
| 1135 (define_insn "spe_evmhessf" | |
| 1136 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1137 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1138 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) | |
| 1139 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 1140 "TARGET_SPE" | |
| 1141 "evmhessf %0,%1,%2" | |
| 1142 [(set_attr "type" "veccomplex") | |
| 1143 (set_attr "length" "4")]) | |
| 1144 | |
| 1145 (define_insn "spe_evmhessiaaw" | |
| 1146 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1147 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1148 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1149 (reg:V2SI SPE_ACC_REGNO)] 575)) | |
| 1150 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1151 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1152 "TARGET_SPE" | |
| 1153 "evmhessiaaw %0,%1,%2" | |
| 1154 [(set_attr "type" "veccomplex") | |
| 1155 (set_attr "length" "4")]) | |
| 1156 | |
| 1157 (define_insn "spe_evmhessianw" | |
| 1158 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1159 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1160 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1161 (reg:V2SI SPE_ACC_REGNO)] 576)) | |
| 1162 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1163 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1164 "TARGET_SPE" | |
| 1165 "evmhessianw %0,%1,%2" | |
| 1166 [(set_attr "type" "veccomplex") | |
| 1167 (set_attr "length" "4")]) | |
| 1168 | |
| 1169 (define_insn "spe_evmheumiaaw" | |
| 1170 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1171 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1172 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1173 (reg:V2SI SPE_ACC_REGNO)] 577)) | |
| 1174 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1175 "TARGET_SPE" | |
| 1176 "evmheumiaaw %0,%1,%2" | |
| 1177 [(set_attr "type" "veccomplex") | |
| 1178 (set_attr "length" "4")]) | |
| 1179 | |
| 1180 (define_insn "spe_evmheumianw" | |
| 1181 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1182 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1183 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1184 (reg:V2SI SPE_ACC_REGNO)] 578)) | |
| 1185 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1186 "TARGET_SPE" | |
| 1187 "evmheumianw %0,%1,%2" | |
| 1188 [(set_attr "type" "veccomplex") | |
| 1189 (set_attr "length" "4")]) | |
| 1190 | |
| 1191 (define_insn "spe_evmheumia" | |
| 1192 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1193 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1194 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) | |
| 1195 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1196 "TARGET_SPE" | |
| 1197 "evmheumia %0,%1,%2" | |
| 1198 [(set_attr "type" "veccomplex") | |
| 1199 (set_attr "length" "4")]) | |
| 1200 | |
| 1201 (define_insn "spe_evmheumi" | |
| 1202 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1203 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1204 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] | |
| 1205 "TARGET_SPE" | |
| 1206 "evmheumi %0,%1,%2" | |
| 1207 [(set_attr "type" "veccomplex") | |
| 1208 (set_attr "length" "4")]) | |
| 1209 | |
| 1210 (define_insn "spe_evmheusiaaw" | |
| 1211 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1212 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1213 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1214 (reg:V2SI SPE_ACC_REGNO)] 581)) | |
| 1215 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1216 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1217 "TARGET_SPE" | |
| 1218 "evmheusiaaw %0,%1,%2" | |
| 1219 [(set_attr "type" "veccomplex") | |
| 1220 (set_attr "length" "4")]) | |
| 1221 | |
| 1222 (define_insn "spe_evmheusianw" | |
| 1223 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1224 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1225 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1226 (reg:V2SI SPE_ACC_REGNO)] 582)) | |
| 1227 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1228 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1229 "TARGET_SPE" | |
| 1230 "evmheusianw %0,%1,%2" | |
| 1231 [(set_attr "type" "veccomplex") | |
| 1232 (set_attr "length" "4")]) | |
| 1233 | |
| 1234 (define_insn "spe_evmhogsmfaa" | |
| 1235 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1236 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1237 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1238 (reg:V2SI SPE_ACC_REGNO)] 583)) | |
| 1239 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1240 "TARGET_SPE" | |
| 1241 "evmhogsmfaa %0,%1,%2" | |
| 1242 [(set_attr "type" "veccomplex") | |
| 1243 (set_attr "length" "4")]) | |
| 1244 | |
| 1245 (define_insn "spe_evmhogsmfan" | |
| 1246 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1247 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1248 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1249 (reg:V2SI SPE_ACC_REGNO)] 584)) | |
| 1250 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1251 "TARGET_SPE" | |
| 1252 "evmhogsmfan %0,%1,%2" | |
| 1253 [(set_attr "type" "veccomplex") | |
| 1254 (set_attr "length" "4")]) | |
| 1255 | |
| 1256 (define_insn "spe_evmhogsmiaa" | |
| 1257 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1258 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1259 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1260 (reg:V2SI SPE_ACC_REGNO)] 585)) | |
| 1261 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1262 "TARGET_SPE" | |
| 1263 "evmhogsmiaa %0,%1,%2" | |
| 1264 [(set_attr "type" "veccomplex") | |
| 1265 (set_attr "length" "4")]) | |
| 1266 | |
| 1267 (define_insn "spe_evmhogsmian" | |
| 1268 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1269 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1270 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1271 (reg:V2SI SPE_ACC_REGNO)] 586)) | |
| 1272 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1273 "TARGET_SPE" | |
| 1274 "evmhogsmian %0,%1,%2" | |
| 1275 [(set_attr "type" "veccomplex") | |
| 1276 (set_attr "length" "4")]) | |
| 1277 | |
| 1278 (define_insn "spe_evmhogumiaa" | |
| 1279 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1280 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1281 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1282 (reg:V2SI SPE_ACC_REGNO)] 587)) | |
| 1283 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1284 "TARGET_SPE" | |
| 1285 "evmhogumiaa %0,%1,%2" | |
| 1286 [(set_attr "type" "veccomplex") | |
| 1287 (set_attr "length" "4")]) | |
| 1288 | |
| 1289 (define_insn "spe_evmhogumian" | |
| 1290 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1291 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1292 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1293 (reg:V2SI SPE_ACC_REGNO)] 588)) | |
| 1294 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1295 "TARGET_SPE" | |
| 1296 "evmhogumian %0,%1,%2" | |
| 1297 [(set_attr "type" "veccomplex") | |
| 1298 (set_attr "length" "4")]) | |
| 1299 | |
| 1300 (define_insn "spe_evmhosmfaaw" | |
| 1301 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1302 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1303 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1304 (reg:V2SI SPE_ACC_REGNO)] 589)) | |
| 1305 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1306 "TARGET_SPE" | |
| 1307 "evmhosmfaaw %0,%1,%2" | |
| 1308 [(set_attr "type" "veccomplex") | |
| 1309 (set_attr "length" "4")]) | |
| 1310 | |
| 1311 (define_insn "spe_evmhosmfanw" | |
| 1312 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1313 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1314 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1315 (reg:V2SI SPE_ACC_REGNO)] 590)) | |
| 1316 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1317 "TARGET_SPE" | |
| 1318 "evmhosmfanw %0,%1,%2" | |
| 1319 [(set_attr "type" "veccomplex") | |
| 1320 (set_attr "length" "4")]) | |
| 1321 | |
| 1322 (define_insn "spe_evmhosmfa" | |
| 1323 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1324 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1325 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] | |
| 1326 "TARGET_SPE" | |
| 1327 "evmhosmfa %0,%1,%2" | |
| 1328 [(set_attr "type" "veccomplex") | |
| 1329 (set_attr "length" "4")]) | |
| 1330 | |
| 1331 (define_insn "spe_evmhosmf" | |
| 1332 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1333 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1334 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) | |
| 1335 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1336 "TARGET_SPE" | |
| 1337 "evmhosmf %0,%1,%2" | |
| 1338 [(set_attr "type" "veccomplex") | |
| 1339 (set_attr "length" "4")]) | |
| 1340 | |
| 1341 (define_insn "spe_evmhosmiaaw" | |
| 1342 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1343 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1344 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1345 (reg:V2SI SPE_ACC_REGNO)] 593)) | |
| 1346 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1347 "TARGET_SPE" | |
| 1348 "evmhosmiaaw %0,%1,%2" | |
| 1349 [(set_attr "type" "veccomplex") | |
| 1350 (set_attr "length" "4")]) | |
| 1351 | |
| 1352 (define_insn "spe_evmhosmianw" | |
| 1353 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1354 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1355 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1356 (reg:V2SI SPE_ACC_REGNO)] 594)) | |
| 1357 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1358 "TARGET_SPE" | |
| 1359 "evmhosmianw %0,%1,%2" | |
| 1360 [(set_attr "type" "veccomplex") | |
| 1361 (set_attr "length" "4")]) | |
| 1362 | |
| 1363 (define_insn "spe_evmhosmia" | |
| 1364 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1365 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1366 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) | |
| 1367 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1368 "TARGET_SPE" | |
| 1369 "evmhosmia %0,%1,%2" | |
| 1370 [(set_attr "type" "veccomplex") | |
| 1371 (set_attr "length" "4")]) | |
| 1372 | |
| 1373 (define_insn "spe_evmhosmi" | |
| 1374 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1375 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1376 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] | |
| 1377 "TARGET_SPE" | |
| 1378 "evmhosmi %0,%1,%2" | |
| 1379 [(set_attr "type" "veccomplex") | |
| 1380 (set_attr "length" "4")]) | |
| 1381 | |
| 1382 (define_insn "spe_evmhossfaaw" | |
| 1383 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1384 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1385 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1386 (reg:V2SI SPE_ACC_REGNO)] 597)) | |
| 1387 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1388 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1389 "TARGET_SPE" | |
| 1390 "evmhossfaaw %0,%1,%2" | |
| 1391 [(set_attr "type" "veccomplex") | |
| 1392 (set_attr "length" "4")]) | |
| 1393 | |
| 1394 (define_insn "spe_evmhossfanw" | |
| 1395 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1396 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1397 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1398 (reg:V2SI SPE_ACC_REGNO)] 598)) | |
| 1399 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1400 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1401 "TARGET_SPE" | |
| 1402 "evmhossfanw %0,%1,%2" | |
| 1403 [(set_attr "type" "veccomplex") | |
| 1404 (set_attr "length" "4")]) | |
| 1405 | |
| 1406 (define_insn "spe_evmhossfa" | |
| 1407 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1408 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1409 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1410 (reg:V2SI SPE_ACC_REGNO)] 599)) | |
| 1411 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1412 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1413 "TARGET_SPE" | |
| 1414 "evmhossfa %0,%1,%2" | |
| 1415 [(set_attr "type" "veccomplex") | |
| 1416 (set_attr "length" "4")]) | |
| 1417 | |
| 1418 (define_insn "spe_evmhossf" | |
| 1419 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1420 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1421 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) | |
| 1422 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 1423 "TARGET_SPE" | |
| 1424 "evmhossf %0,%1,%2" | |
| 1425 [(set_attr "type" "veccomplex") | |
| 1426 (set_attr "length" "4")]) | |
| 1427 | |
| 1428 (define_insn "spe_evmhossiaaw" | |
| 1429 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1430 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1431 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1432 (reg:V2SI SPE_ACC_REGNO)] 601)) | |
| 1433 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1434 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1435 "TARGET_SPE" | |
| 1436 "evmhossiaaw %0,%1,%2" | |
| 1437 [(set_attr "type" "veccomplex") | |
| 1438 (set_attr "length" "4")]) | |
| 1439 | |
| 1440 (define_insn "spe_evmhossianw" | |
| 1441 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1442 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1443 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1444 (reg:V2SI SPE_ACC_REGNO)] 602)) | |
| 1445 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1446 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1447 "TARGET_SPE" | |
| 1448 "evmhossianw %0,%1,%2" | |
| 1449 [(set_attr "type" "veccomplex") | |
| 1450 (set_attr "length" "4")]) | |
| 1451 | |
| 1452 (define_insn "spe_evmhoumiaaw" | |
| 1453 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1454 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1455 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1456 (reg:V2SI SPE_ACC_REGNO)] 603)) | |
| 1457 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1458 "TARGET_SPE" | |
| 1459 "evmhoumiaaw %0,%1,%2" | |
| 1460 [(set_attr "type" "veccomplex") | |
| 1461 (set_attr "length" "4")]) | |
| 1462 | |
| 1463 (define_insn "spe_evmhoumianw" | |
| 1464 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1465 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1466 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1467 (reg:V2SI SPE_ACC_REGNO)] 604)) | |
| 1468 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1469 "TARGET_SPE" | |
| 1470 "evmhoumianw %0,%1,%2" | |
| 1471 [(set_attr "type" "veccomplex") | |
| 1472 (set_attr "length" "4")]) | |
| 1473 | |
| 1474 (define_insn "spe_evmhoumia" | |
| 1475 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1476 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1477 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) | |
| 1478 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1479 "TARGET_SPE" | |
| 1480 "evmhoumia %0,%1,%2" | |
| 1481 [(set_attr "type" "veccomplex") | |
| 1482 (set_attr "length" "4")]) | |
| 1483 | |
| 1484 (define_insn "spe_evmhoumi" | |
| 1485 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1486 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1487 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] | |
| 1488 "TARGET_SPE" | |
| 1489 "evmhoumi %0,%1,%2" | |
| 1490 [(set_attr "type" "veccomplex") | |
| 1491 (set_attr "length" "4")]) | |
| 1492 | |
| 1493 (define_insn "spe_evmhousiaaw" | |
| 1494 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1495 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1496 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1497 (reg:V2SI SPE_ACC_REGNO)] 607)) | |
| 1498 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1499 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1500 "TARGET_SPE" | |
| 1501 "evmhousiaaw %0,%1,%2" | |
| 1502 [(set_attr "type" "veccomplex") | |
| 1503 (set_attr "length" "4")]) | |
| 1504 | |
| 1505 (define_insn "spe_evmhousianw" | |
| 1506 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1507 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1508 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1509 (reg:V2SI SPE_ACC_REGNO)] 608)) | |
| 1510 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1511 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1512 "TARGET_SPE" | |
| 1513 "evmhousianw %0,%1,%2" | |
| 1514 [(set_attr "type" "veccomplex") | |
| 1515 (set_attr "length" "4")]) | |
| 1516 | |
| 1517 (define_insn "spe_evmmlssfa" | |
| 1518 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1519 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1520 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] | |
| 1521 "TARGET_SPE" | |
| 1522 "evmmlssfa %0,%1,%2" | |
| 1523 [(set_attr "type" "veccomplex") | |
| 1524 (set_attr "length" "4")]) | |
| 1525 | |
| 1526 (define_insn "spe_evmmlssf" | |
| 1527 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1528 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1529 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] | |
| 1530 "TARGET_SPE" | |
| 1531 "evmmlssf %0,%1,%2" | |
| 1532 [(set_attr "type" "veccomplex") | |
| 1533 (set_attr "length" "4")]) | |
| 1534 | |
| 1535 (define_insn "spe_evmwhsmfa" | |
| 1536 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1537 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1538 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) | |
| 1539 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1540 "TARGET_SPE" | |
| 1541 "evmwhsmfa %0,%1,%2" | |
| 1542 [(set_attr "type" "veccomplex") | |
| 1543 (set_attr "length" "4")]) | |
| 1544 | |
| 1545 (define_insn "spe_evmwhsmf" | |
| 1546 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1547 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1548 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] | |
| 1549 "TARGET_SPE" | |
| 1550 "evmwhsmf %0,%1,%2" | |
| 1551 [(set_attr "type" "veccomplex") | |
| 1552 (set_attr "length" "4")]) | |
| 1553 | |
| 1554 (define_insn "spe_evmwhsmia" | |
| 1555 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1556 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1557 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) | |
| 1558 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1559 "TARGET_SPE" | |
| 1560 "evmwhsmia %0,%1,%2" | |
| 1561 [(set_attr "type" "veccomplex") | |
| 1562 (set_attr "length" "4")]) | |
| 1563 | |
| 1564 (define_insn "spe_evmwhsmi" | |
| 1565 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1566 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1567 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] | |
| 1568 "TARGET_SPE" | |
| 1569 "evmwhsmi %0,%1,%2" | |
| 1570 [(set_attr "type" "veccomplex") | |
| 1571 (set_attr "length" "4")]) | |
| 1572 | |
| 1573 (define_insn "spe_evmwhssfa" | |
| 1574 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1575 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1576 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) | |
| 1577 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1578 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1579 "TARGET_SPE" | |
| 1580 "evmwhssfa %0,%1,%2" | |
| 1581 [(set_attr "type" "veccomplex") | |
| 1582 (set_attr "length" "4")]) | |
| 1583 | |
| 1584 (define_insn "spe_evmwhusian" | |
| 1585 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1586 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1587 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] | |
| 1588 "TARGET_SPE" | |
| 1589 "evmwhusian %0,%1,%2" | |
| 1590 [(set_attr "type" "veccomplex") | |
| 1591 (set_attr "length" "4")]) | |
| 1592 | |
| 1593 (define_insn "spe_evmwhssf" | |
| 1594 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1595 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1596 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) | |
| 1597 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 1598 "TARGET_SPE" | |
| 1599 "evmwhssf %0,%1,%2" | |
| 1600 [(set_attr "type" "veccomplex") | |
| 1601 (set_attr "length" "4")]) | |
| 1602 | |
| 1603 (define_insn "spe_evmwhumia" | |
| 1604 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1605 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1606 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) | |
| 1607 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1608 "TARGET_SPE" | |
| 1609 "evmwhumia %0,%1,%2" | |
| 1610 [(set_attr "type" "veccomplex") | |
| 1611 (set_attr "length" "4")]) | |
| 1612 | |
| 1613 (define_insn "spe_evmwhumi" | |
| 1614 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1615 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1616 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] | |
| 1617 "TARGET_SPE" | |
| 1618 "evmwhumi %0,%1,%2" | |
| 1619 [(set_attr "type" "veccomplex") | |
| 1620 (set_attr "length" "4")]) | |
| 1621 | |
| 1622 (define_insn "spe_evmwlsmiaaw" | |
| 1623 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1624 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1625 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1626 (reg:V2SI SPE_ACC_REGNO)] 635)) | |
| 1627 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1628 "TARGET_SPE" | |
| 1629 "evmwlsmiaaw %0,%1,%2" | |
| 1630 [(set_attr "type" "veccomplex") | |
| 1631 (set_attr "length" "4")]) | |
| 1632 | |
| 1633 (define_insn "spe_evmwlsmianw" | |
| 1634 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1635 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1636 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1637 (reg:V2SI SPE_ACC_REGNO)] 636)) | |
| 1638 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1639 "TARGET_SPE" | |
| 1640 "evmwlsmianw %0,%1,%2" | |
| 1641 [(set_attr "type" "veccomplex") | |
| 1642 (set_attr "length" "4")]) | |
| 1643 | |
| 1644 (define_insn "spe_evmwlssiaaw" | |
| 1645 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1646 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1647 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1648 (reg:V2SI SPE_ACC_REGNO)] 641)) | |
| 1649 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1650 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1651 "TARGET_SPE" | |
| 1652 "evmwlssiaaw %0,%1,%2" | |
| 1653 [(set_attr "type" "veccomplex") | |
| 1654 (set_attr "length" "4")]) | |
| 1655 | |
| 1656 (define_insn "spe_evmwlssianw" | |
| 1657 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1658 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1659 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1660 (reg:V2SI SPE_ACC_REGNO)] 642)) | |
| 1661 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1662 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1663 "TARGET_SPE" | |
| 1664 "evmwlssianw %0,%1,%2" | |
| 1665 [(set_attr "type" "veccomplex") | |
| 1666 (set_attr "length" "4")]) | |
| 1667 | |
| 1668 (define_insn "spe_evmwlumiaaw" | |
| 1669 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1670 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1671 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1672 (reg:V2SI SPE_ACC_REGNO)] 643)) | |
| 1673 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1674 "TARGET_SPE" | |
| 1675 "evmwlumiaaw %0,%1,%2" | |
| 1676 [(set_attr "type" "veccomplex") | |
| 1677 (set_attr "length" "4")]) | |
| 1678 | |
| 1679 (define_insn "spe_evmwlumianw" | |
| 1680 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1681 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1682 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1683 (reg:V2SI SPE_ACC_REGNO)] 644)) | |
| 1684 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1685 "TARGET_SPE" | |
| 1686 "evmwlumianw %0,%1,%2" | |
| 1687 [(set_attr "type" "veccomplex") | |
| 1688 (set_attr "length" "4")]) | |
| 1689 | |
| 1690 (define_insn "spe_evmwlumia" | |
| 1691 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1692 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1693 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) | |
| 1694 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1695 "TARGET_SPE" | |
| 1696 "evmwlumia %0,%1,%2" | |
| 1697 [(set_attr "type" "veccomplex") | |
| 1698 (set_attr "length" "4")]) | |
| 1699 | |
| 1700 (define_insn "spe_evmwlumi" | |
| 1701 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1702 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1703 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] | |
| 1704 "TARGET_SPE" | |
| 1705 "evmwlumi %0,%1,%2" | |
| 1706 [(set_attr "type" "veccomplex") | |
| 1707 (set_attr "length" "4")]) | |
| 1708 | |
| 1709 (define_insn "spe_evmwlusiaaw" | |
| 1710 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1711 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1712 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1713 (reg:V2SI SPE_ACC_REGNO)] 647)) | |
| 1714 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1715 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1716 "TARGET_SPE" | |
| 1717 "evmwlusiaaw %0,%1,%2" | |
| 1718 [(set_attr "type" "veccomplex") | |
| 1719 (set_attr "length" "4")]) | |
| 1720 | |
| 1721 (define_insn "spe_evmwlusianw" | |
| 1722 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1723 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1724 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1725 (reg:V2SI SPE_ACC_REGNO)] 648)) | |
| 1726 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1727 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1728 "TARGET_SPE" | |
| 1729 "evmwlusianw %0,%1,%2" | |
| 1730 [(set_attr "type" "veccomplex") | |
| 1731 (set_attr "length" "4")]) | |
| 1732 | |
| 1733 (define_insn "spe_evmwsmfaa" | |
| 1734 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1735 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1736 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1737 (reg:V2SI SPE_ACC_REGNO)] 649)) | |
| 1738 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1739 "TARGET_SPE" | |
| 1740 "evmwsmfaa %0,%1,%2" | |
| 1741 [(set_attr "type" "veccomplex") | |
| 1742 (set_attr "length" "4")]) | |
| 1743 | |
| 1744 (define_insn "spe_evmwsmfan" | |
| 1745 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1746 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1747 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1748 (reg:V2SI SPE_ACC_REGNO)] 650)) | |
| 1749 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1750 "TARGET_SPE" | |
| 1751 "evmwsmfan %0,%1,%2" | |
| 1752 [(set_attr "type" "veccomplex") | |
| 1753 (set_attr "length" "4")]) | |
| 1754 | |
| 1755 (define_insn "spe_evmwsmfa" | |
| 1756 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1757 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1758 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) | |
| 1759 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1760 "TARGET_SPE" | |
| 1761 "evmwsmfa %0,%1,%2" | |
| 1762 [(set_attr "type" "veccomplex") | |
| 1763 (set_attr "length" "4")]) | |
| 1764 | |
| 1765 (define_insn "spe_evmwsmf" | |
| 1766 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1767 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1768 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] | |
| 1769 "TARGET_SPE" | |
| 1770 "evmwsmf %0,%1,%2" | |
| 1771 [(set_attr "type" "veccomplex") | |
| 1772 (set_attr "length" "4")]) | |
| 1773 | |
| 1774 (define_insn "spe_evmwsmiaa" | |
| 1775 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1776 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1777 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1778 (reg:V2SI SPE_ACC_REGNO)] 653)) | |
| 1779 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1780 "TARGET_SPE" | |
| 1781 "evmwsmiaa %0,%1,%2" | |
| 1782 [(set_attr "type" "veccomplex") | |
| 1783 (set_attr "length" "4")]) | |
| 1784 | |
| 1785 (define_insn "spe_evmwsmian" | |
| 1786 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1787 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1788 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1789 (reg:V2SI SPE_ACC_REGNO)] 654)) | |
| 1790 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1791 "TARGET_SPE" | |
| 1792 "evmwsmian %0,%1,%2" | |
| 1793 [(set_attr "type" "veccomplex") | |
| 1794 (set_attr "length" "4")]) | |
| 1795 | |
| 1796 (define_insn "spe_evmwsmia" | |
| 1797 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1798 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1799 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) | |
| 1800 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1801 "TARGET_SPE" | |
| 1802 "evmwsmia %0,%1,%2" | |
| 1803 [(set_attr "type" "veccomplex") | |
| 1804 (set_attr "length" "4")]) | |
| 1805 | |
| 1806 (define_insn "spe_evmwsmi" | |
| 1807 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1808 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1809 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] | |
| 1810 "TARGET_SPE" | |
| 1811 "evmwsmi %0,%1,%2" | |
| 1812 [(set_attr "type" "veccomplex") | |
| 1813 (set_attr "length" "4")]) | |
| 1814 | |
| 1815 (define_insn "spe_evmwssfaa" | |
| 1816 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1817 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1818 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1819 (reg:V2SI SPE_ACC_REGNO)] 657)) | |
| 1820 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1821 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1822 "TARGET_SPE" | |
| 1823 "evmwssfaa %0,%1,%2" | |
| 1824 [(set_attr "type" "veccomplex") | |
| 1825 (set_attr "length" "4")]) | |
| 1826 | |
| 1827 (define_insn "spe_evmwssfan" | |
| 1828 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1829 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1830 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1831 (reg:V2SI SPE_ACC_REGNO)] 658)) | |
| 1832 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1833 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1834 "TARGET_SPE" | |
| 1835 "evmwssfan %0,%1,%2" | |
| 1836 [(set_attr "type" "veccomplex") | |
| 1837 (set_attr "length" "4")]) | |
| 1838 | |
| 1839 (define_insn "spe_evmwssfa" | |
| 1840 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1841 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1842 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) | |
| 1843 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1844 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1845 "TARGET_SPE" | |
| 1846 "evmwssfa %0,%1,%2" | |
| 1847 [(set_attr "type" "veccomplex") | |
| 1848 (set_attr "length" "4")]) | |
| 1849 | |
| 1850 (define_insn "spe_evmwssf" | |
| 1851 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1852 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1853 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) | |
| 1854 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 1855 "TARGET_SPE" | |
| 1856 "evmwssf %0,%1,%2" | |
| 1857 [(set_attr "type" "veccomplex") | |
| 1858 (set_attr "length" "4")]) | |
| 1859 | |
| 1860 (define_insn "spe_evmwumiaa" | |
| 1861 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1862 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1863 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1864 (reg:V2SI SPE_ACC_REGNO)] 661)) | |
| 1865 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1866 "TARGET_SPE" | |
| 1867 "evmwumiaa %0,%1,%2" | |
| 1868 [(set_attr "type" "veccomplex") | |
| 1869 (set_attr "length" "4")]) | |
| 1870 | |
| 1871 (define_insn "spe_evmwumian" | |
| 1872 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1873 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1874 (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
| 1875 (reg:V2SI SPE_ACC_REGNO)] 662)) | |
| 1876 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1877 "TARGET_SPE" | |
| 1878 "evmwumian %0,%1,%2" | |
| 1879 [(set_attr "type" "veccomplex") | |
| 1880 (set_attr "length" "4")]) | |
| 1881 | |
| 1882 (define_insn "spe_evmwumia" | |
| 1883 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1884 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1885 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) | |
| 1886 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1887 "TARGET_SPE" | |
| 1888 "evmwumia %0,%1,%2" | |
| 1889 [(set_attr "type" "veccomplex") | |
| 1890 (set_attr "length" "4")]) | |
| 1891 | |
| 1892 (define_insn "spe_evmwumi" | |
| 1893 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1894 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1895 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] | |
| 1896 "TARGET_SPE" | |
| 1897 "evmwumi %0,%1,%2" | |
| 1898 [(set_attr "type" "veccomplex") | |
| 1899 (set_attr "length" "4")]) | |
| 1900 | |
|
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diff
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|
1901 (define_insn "addv2si3" |
| 0 | 1902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
| 1903 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1904 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
| 1905 "TARGET_SPE" | |
| 1906 "evaddw %0,%1,%2" | |
| 1907 [(set_attr "type" "vecsimple") | |
| 1908 (set_attr "length" "4")]) | |
| 1909 | |
| 1910 (define_insn "spe_evaddusiaaw" | |
| 1911 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1912 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1913 (reg:V2SI SPE_ACC_REGNO)] 673)) | |
| 1914 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1915 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1916 "TARGET_SPE" | |
| 1917 "evaddusiaaw %0,%1" | |
| 1918 [(set_attr "type" "veccomplex") | |
| 1919 (set_attr "length" "4")]) | |
| 1920 | |
| 1921 (define_insn "spe_evaddumiaaw" | |
| 1922 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1923 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1924 (reg:V2SI SPE_ACC_REGNO)] 674)) | |
| 1925 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1926 "TARGET_SPE" | |
| 1927 "evaddumiaaw %0,%1" | |
| 1928 [(set_attr "type" "veccomplex") | |
| 1929 (set_attr "length" "4")]) | |
| 1930 | |
| 1931 (define_insn "spe_evaddssiaaw" | |
| 1932 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1933 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1934 (reg:V2SI SPE_ACC_REGNO)] 675)) | |
| 1935 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1936 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1937 "TARGET_SPE" | |
| 1938 "evaddssiaaw %0,%1" | |
| 1939 [(set_attr "type" "veccomplex") | |
| 1940 (set_attr "length" "4")]) | |
| 1941 | |
| 1942 (define_insn "spe_evaddsmiaaw" | |
| 1943 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1944 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1945 (reg:V2SI SPE_ACC_REGNO)] 676)) | |
| 1946 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1947 "TARGET_SPE" | |
| 1948 "evaddsmiaaw %0,%1" | |
| 1949 [(set_attr "type" "veccomplex") | |
| 1950 (set_attr "length" "4")]) | |
| 1951 | |
| 1952 (define_insn "spe_evaddiw" | |
| 1953 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1954 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1955 (match_operand:QI 2 "immediate_operand" "i")] 677))] | |
| 1956 "TARGET_SPE" | |
| 1957 "evaddiw %0,%1,%2" | |
| 1958 [(set_attr "type" "vecsimple") | |
| 1959 (set_attr "length" "4")]) | |
| 1960 | |
| 1961 (define_insn "spe_evsubifw" | |
| 1962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1964 (match_operand:QI 2 "immediate_operand" "i")] 678))] | |
| 1965 "TARGET_SPE" | |
| 1966 "evsubifw %0,%2,%1" | |
| 1967 [(set_attr "type" "veccomplex") | |
| 1968 (set_attr "length" "4")]) | |
| 1969 | |
|
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parents:
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diff
changeset
|
1970 (define_insn "subv2si3" |
| 0 | 1971 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
| 1972 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1973 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
| 1974 "TARGET_SPE" | |
| 1975 "evsubfw %0,%2,%1" | |
| 1976 [(set_attr "type" "veccomplex") | |
| 1977 (set_attr "length" "4")]) | |
| 1978 | |
| 1979 (define_insn "spe_evsubfusiaaw" | |
| 1980 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1981 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1982 (reg:V2SI SPE_ACC_REGNO)] 679)) | |
| 1983 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 1984 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1985 "TARGET_SPE" | |
| 1986 "evsubfusiaaw %0,%1" | |
| 1987 [(set_attr "type" "veccomplex") | |
| 1988 (set_attr "length" "4")]) | |
| 1989 | |
| 1990 (define_insn "spe_evsubfumiaaw" | |
| 1991 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 1992 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 1993 (reg:V2SI SPE_ACC_REGNO)] 680)) | |
| 1994 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 1995 "TARGET_SPE" | |
| 1996 "evsubfumiaaw %0,%1" | |
| 1997 [(set_attr "type" "veccomplex") | |
| 1998 (set_attr "length" "4")]) | |
| 1999 | |
| 2000 (define_insn "spe_evsubfssiaaw" | |
| 2001 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2002 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2003 (reg:V2SI SPE_ACC_REGNO)] 681)) | |
| 2004 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2005 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2006 "TARGET_SPE" | |
| 2007 "evsubfssiaaw %0,%1" | |
| 2008 [(set_attr "type" "veccomplex") | |
| 2009 (set_attr "length" "4")]) | |
| 2010 | |
| 2011 (define_insn "spe_evsubfsmiaaw" | |
| 2012 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2013 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2014 (reg:V2SI SPE_ACC_REGNO)] 682)) | |
| 2015 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2016 "TARGET_SPE" | |
| 2017 "evsubfsmiaaw %0,%1" | |
| 2018 [(set_attr "type" "veccomplex") | |
| 2019 (set_attr "length" "4")]) | |
| 2020 | |
| 2021 (define_insn "spe_evmra" | |
| 2022 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2023 (match_operand:V2SI 1 "gpc_reg_operand" "r")) | |
| 2024 (set (reg:V2SI SPE_ACC_REGNO) | |
| 2025 (unspec:V2SI [(match_dup 1)] 726))] | |
| 2026 "TARGET_SPE" | |
| 2027 "evmra %0,%1" | |
| 2028 [(set_attr "type" "veccomplex") | |
| 2029 (set_attr "length" "4")]) | |
| 2030 | |
|
55
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parents:
0
diff
changeset
|
2031 (define_insn "divv2si3" |
| 0 | 2032 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
| 2033 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2034 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
| 2035 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 2036 "TARGET_SPE" | |
| 2037 "evdivws %0,%1,%2" | |
| 2038 [(set_attr "type" "vecdiv") | |
| 2039 (set_attr "length" "4")]) | |
| 2040 | |
| 2041 (define_insn "spe_evdivwu" | |
| 2042 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2043 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2044 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
| 2045 (clobber (reg:SI SPEFSCR_REGNO))] | |
| 2046 "TARGET_SPE" | |
| 2047 "evdivwu %0,%1,%2" | |
| 2048 [(set_attr "type" "vecdiv") | |
| 2049 (set_attr "length" "4")]) | |
| 2050 | |
| 2051 (define_insn "spe_evsplatfi" | |
| 2052 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2053 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] | |
| 2054 "TARGET_SPE" | |
| 2055 "evsplatfi %0,%1" | |
| 2056 [(set_attr "type" "vecperm") | |
| 2057 (set_attr "length" "4")]) | |
| 2058 | |
| 2059 (define_insn "spe_evsplati" | |
| 2060 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2061 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] | |
| 2062 "TARGET_SPE" | |
| 2063 "evsplati %0,%1" | |
| 2064 [(set_attr "type" "vecperm") | |
| 2065 (set_attr "length" "4")]) | |
| 2066 | |
| 2067 (define_insn "spe_evstdd" | |
| 2068 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2069 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2070 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2071 (unspec [(const_int 0)] 686)] | |
| 2072 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2073 "evstdd %2,%1*8(%0)" | |
| 2074 [(set_attr "type" "vecstore") | |
| 2075 (set_attr "length" "4")]) | |
| 2076 | |
| 2077 (define_insn "spe_evstddx" | |
| 2078 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2079 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2080 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2081 (unspec [(const_int 0)] 687)] | |
| 2082 "TARGET_SPE" | |
| 2083 "evstddx %2,%0,%1" | |
| 2084 [(set_attr "type" "vecstore") | |
| 2085 (set_attr "length" "4")]) | |
| 2086 | |
| 2087 (define_insn "spe_evstdh" | |
| 2088 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2089 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2090 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2091 (unspec [(const_int 0)] 688)] | |
| 2092 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2093 "evstdh %2,%1*8(%0)" | |
| 2094 [(set_attr "type" "vecstore") | |
| 2095 (set_attr "length" "4")]) | |
| 2096 | |
| 2097 (define_insn "spe_evstdhx" | |
| 2098 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2099 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2100 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2101 (unspec [(const_int 0)] 689)] | |
| 2102 "TARGET_SPE" | |
| 2103 "evstdhx %2,%0,%1" | |
| 2104 [(set_attr "type" "vecstore") | |
| 2105 (set_attr "length" "4")]) | |
| 2106 | |
| 2107 (define_insn "spe_evstdw" | |
| 2108 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2109 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2110 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2111 (unspec [(const_int 0)] 690)] | |
| 2112 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2113 "evstdw %2,%1*8(%0)" | |
| 2114 [(set_attr "type" "vecstore") | |
| 2115 (set_attr "length" "4")]) | |
| 2116 | |
| 2117 (define_insn "spe_evstdwx" | |
| 2118 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2119 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2120 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2121 (unspec [(const_int 0)] 691)] | |
| 2122 "TARGET_SPE" | |
| 2123 "evstdwx %2,%0,%1" | |
| 2124 [(set_attr "type" "vecstore") | |
| 2125 (set_attr "length" "4")]) | |
| 2126 | |
| 2127 (define_insn "spe_evstwhe" | |
| 2128 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2129 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2130 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2131 (unspec [(const_int 0)] 692)] | |
| 2132 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2133 "evstwhe %2,%1*4(%0)" | |
| 2134 [(set_attr "type" "vecstore") | |
| 2135 (set_attr "length" "4")]) | |
| 2136 | |
| 2137 (define_insn "spe_evstwhex" | |
| 2138 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2139 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2140 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2141 (unspec [(const_int 0)] 693)] | |
| 2142 "TARGET_SPE" | |
| 2143 "evstwhex %2,%0,%1" | |
| 2144 [(set_attr "type" "vecstore") | |
| 2145 (set_attr "length" "4")]) | |
| 2146 | |
| 2147 (define_insn "spe_evstwho" | |
| 2148 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2149 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2150 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2151 (unspec [(const_int 0)] 694)] | |
| 2152 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2153 "evstwho %2,%1*4(%0)" | |
| 2154 [(set_attr "type" "vecstore") | |
| 2155 (set_attr "length" "4")]) | |
| 2156 | |
| 2157 (define_insn "spe_evstwhox" | |
| 2158 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2159 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2160 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2161 (unspec [(const_int 0)] 695)] | |
| 2162 "TARGET_SPE" | |
| 2163 "evstwhox %2,%0,%1" | |
| 2164 [(set_attr "type" "vecstore") | |
| 2165 (set_attr "length" "4")]) | |
| 2166 | |
| 2167 (define_insn "spe_evstwwe" | |
| 2168 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2169 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2170 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2171 (unspec [(const_int 0)] 696)] | |
| 2172 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2173 "evstwwe %2,%1*4(%0)" | |
| 2174 [(set_attr "type" "vecstore") | |
| 2175 (set_attr "length" "4")]) | |
| 2176 | |
| 2177 (define_insn "spe_evstwwex" | |
| 2178 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2179 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2180 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2181 (unspec [(const_int 0)] 697)] | |
| 2182 "TARGET_SPE" | |
| 2183 "evstwwex %2,%0,%1" | |
| 2184 [(set_attr "type" "vecstore") | |
| 2185 (set_attr "length" "4")]) | |
| 2186 | |
| 2187 (define_insn "spe_evstwwo" | |
| 2188 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2189 (match_operand:QI 1 "immediate_operand" "i"))) | |
| 2190 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2191 (unspec [(const_int 0)] 698)] | |
| 2192 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" | |
| 2193 "evstwwo %2,%1*4(%0)" | |
| 2194 [(set_attr "type" "vecstore") | |
| 2195 (set_attr "length" "4")]) | |
| 2196 | |
| 2197 (define_insn "spe_evstwwox" | |
| 2198 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
| 2199 (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
| 2200 (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
| 2201 (unspec [(const_int 0)] 699)] | |
| 2202 "TARGET_SPE" | |
| 2203 "evstwwox %2,%0,%1" | |
| 2204 [(set_attr "type" "vecstore") | |
| 2205 (set_attr "length" "4")]) | |
| 2206 | |
| 2207 ;; Double-precision floating point instructions. | |
| 2208 | |
| 2209 ;; FIXME: Add o=r option. | |
| 2210 (define_insn "*frob_<SPE64:mode>_<DITI:mode>" | |
| 2211 [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r") | |
| 2212 (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))] | |
| 2213 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode) | |
| 2214 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)" | |
| 2215 "@ | |
| 2216 evmergelo %0,%1,%L1 | |
| 2217 evldd%X1 %0,%y1") | |
| 2218 | |
| 2219 (define_insn "*frob_tf_ti" | |
| 2220 [(set (match_operand:TF 0 "gpc_reg_operand" "=r") | |
| 2221 (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))] | |
| 2222 "TARGET_E500_DOUBLE" | |
| 2223 "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1" | |
| 2224 [(set_attr "length" "8")]) | |
| 2225 | |
| 2226 (define_insn "*frob_<mode>_di_2" | |
| 2227 [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0) | |
| 2228 (match_operand:DI 1 "input_operand" "r,m"))] | |
| 2229 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2230 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2231 "@ | |
| 2232 evmergelo %0,%1,%L1 | |
| 2233 evldd%X1 %0,%y1") | |
| 2234 | |
| 2235 (define_insn "*frob_tf_di_8_2" | |
| 2236 [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8) | |
| 2237 (match_operand:DI 1 "input_operand" "r,m"))] | |
| 2238 "TARGET_E500_DOUBLE" | |
| 2239 "@ | |
| 2240 evmergelo %L0,%1,%L1 | |
| 2241 evldd%X1 %L0,%y1") | |
| 2242 | |
| 2243 (define_insn "*frob_di_<mode>" | |
| 2244 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r") | |
| 2245 (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))] | |
| 2246 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2247 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2248 "evmergehi %0,%1,%1\;mr %L0,%1" | |
| 2249 [(set_attr "length" "8")]) | |
| 2250 | |
| 2251 (define_insn "*frob_ti_tf" | |
| 2252 [(set (match_operand:TI 0 "nonimmediate_operand" "=&r") | |
| 2253 (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))] | |
| 2254 "TARGET_E500_DOUBLE" | |
| 2255 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1" | |
| 2256 [(set_attr "length" "16")]) | |
| 2257 | |
| 2258 (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2" | |
| 2259 [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0) | |
| 2260 (match_operand:SPE64 1 "input_operand" "r,m"))] | |
| 2261 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode) | |
| 2262 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)" | |
| 2263 "* | |
| 2264 { | |
| 2265 switch (which_alternative) | |
| 2266 { | |
| 2267 default: | |
| 2268 gcc_unreachable (); | |
| 2269 case 0: | |
| 2270 return \"evmergehi %0,%1,%1\;mr %L0,%1\"; | |
| 2271 case 1: | |
| 2272 /* If the address is not offsettable we need to load the whole | |
| 2273 doubleword into a 64-bit register and then copy the high word | |
| 2274 to form the correct output layout. */ | |
| 2275 if (!offsettable_nonstrict_memref_p (operands[1])) | |
| 2276 return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\"; | |
| 2277 /* If the low-address word is used in the address, we must load | |
| 2278 it last. Otherwise, load it first. Note that we cannot have | |
| 2279 auto-increment in that case since the address register is | |
| 2280 known to be dead. */ | |
| 2281 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
| 2282 operands[1], 0)) | |
| 2283 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
| 2284 else | |
| 2285 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\"; | |
| 2286 } | |
| 2287 }" | |
| 2288 [(set_attr "length" "8,8")]) | |
| 2289 | |
| 2290 ; As the above, but TImode at offset 8. | |
| 2291 (define_insn "*frob_ti_<mode>_8_2" | |
| 2292 [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8) | |
| 2293 (match_operand:SPE64 1 "input_operand" "r,m"))] | |
| 2294 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode) | |
| 2295 || (TARGET_SPE && <MODE>mode != DFmode)" | |
| 2296 "* | |
| 2297 { | |
| 2298 switch (which_alternative) | |
| 2299 { | |
| 2300 default: | |
| 2301 gcc_unreachable (); | |
| 2302 case 0: | |
| 2303 return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\"; | |
| 2304 case 1: | |
| 2305 if (!offsettable_nonstrict_memref_p (operands[1])) | |
| 2306 return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\"; | |
| 2307 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
| 2308 operands[1], 0)) | |
| 2309 return \"{l|lwz} %Z0,%L1\;{l|lwz} %Y0,%1\"; | |
| 2310 else | |
| 2311 return \"{l%U1%X1|lwz%U1%X1} %Y0,%1\;{l|lwz} %Z0,%L1\"; | |
| 2312 } | |
| 2313 }" | |
| 2314 [(set_attr "length" "8,8")]) | |
| 2315 | |
| 2316 (define_insn "*frob_ti_tf_2" | |
| 2317 [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0) | |
| 2318 (match_operand:TF 1 "input_operand" "r"))] | |
| 2319 "TARGET_E500_DOUBLE" | |
| 2320 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1" | |
| 2321 [(set_attr "length" "16")]) | |
| 2322 | |
| 2323 (define_insn "*mov_si<mode>_e500_subreg0" | |
| 2324 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0) | |
| 2325 (match_operand:SI 1 "input_operand" "r,m"))] | |
| 2326 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2327 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2328 "@ | |
| 2329 evmergelo %0,%1,%0 | |
| 2330 evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0" | |
| 2331 [(set_attr "length" "4,12")]) | |
| 2332 | |
| 2333 ;; ??? Could use evstwwe for memory stores in some cases, depending on | |
| 2334 ;; the offset. | |
| 2335 (define_insn "*mov_si<mode>_e500_subreg0_2" | |
| 2336 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
| 2337 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))] | |
| 2338 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2339 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2340 "@ | |
| 2341 evmergehi %0,%0,%1 | |
| 2342 evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0" | |
| 2343 [(set_attr "length" "4,8")]) | |
| 2344 | |
| 2345 (define_insn "*mov_si<mode>_e500_subreg4" | |
| 2346 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4) | |
| 2347 (match_operand:SI 1 "input_operand" "r,m"))] | |
| 2348 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2349 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2350 "@ | |
| 2351 mr %0,%1 | |
| 2352 {l%U1%X1|lwz%U1%X1} %0,%1") | |
| 2353 | |
| 2354 (define_insn "*mov_si<mode>_e500_subreg4_2" | |
| 2355 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
| 2356 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))] | |
| 2357 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode)) | |
| 2358 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)" | |
| 2359 "@ | |
| 2360 mr %0,%1 | |
| 2361 {st%U0%X0|stw%U0%X0} %1,%0") | |
| 2362 | |
| 2363 (define_insn "*mov_sitf_e500_subreg8" | |
| 2364 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8) | |
| 2365 (match_operand:SI 1 "input_operand" "r,m"))] | |
| 2366 "TARGET_E500_DOUBLE" | |
| 2367 "@ | |
| 2368 evmergelo %L0,%1,%L0 | |
| 2369 evmergelohi %L0,%L0,%L0\;{l%U1%X1|lwz%U1%X1} %L0,%1\;evmergelohi %L0,%L0,%L0" | |
| 2370 [(set_attr "length" "4,12")]) | |
| 2371 | |
| 2372 (define_insn "*mov_sitf_e500_subreg8_2" | |
| 2373 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
| 2374 (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))] | |
| 2375 "TARGET_E500_DOUBLE" | |
| 2376 "@ | |
| 2377 evmergehi %0,%0,%L1 | |
| 2378 evmergelohi %L1,%L1,%L1\;{st%U0%X0|stw%U0%X0} %L1,%0" | |
| 2379 [(set_attr "length" "4,8")]) | |
| 2380 | |
| 2381 (define_insn "*mov_sitf_e500_subreg12" | |
| 2382 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12) | |
| 2383 (match_operand:SI 1 "input_operand" "r,m"))] | |
| 2384 "TARGET_E500_DOUBLE" | |
| 2385 "@ | |
| 2386 mr %L0,%1 | |
| 2387 {l%U1%X1|lwz%U1%X1} %L0,%1") | |
| 2388 | |
| 2389 (define_insn "*mov_sitf_e500_subreg12_2" | |
| 2390 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") | |
| 2391 (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))] | |
| 2392 "TARGET_E500_DOUBLE" | |
| 2393 "@ | |
| 2394 mr %0,%L1 | |
| 2395 {st%U0%X0|stw%U0%X0} %L1,%0") | |
| 2396 | |
| 2397 ;; FIXME: Allow r=CONST0. | |
| 2398 (define_insn "*movdf_e500_double" | |
| 2399 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m") | |
| 2400 (match_operand:DF 1 "input_operand" "r,m,r"))] | |
| 2401 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 2402 && (gpc_reg_operand (operands[0], DFmode) | |
| 2403 || gpc_reg_operand (operands[1], DFmode))" | |
| 2404 "* | |
| 2405 { | |
| 2406 switch (which_alternative) | |
| 2407 { | |
| 2408 case 0: | |
| 2409 return \"evor %0,%1,%1\"; | |
| 2410 case 1: | |
| 2411 return \"evldd%X1 %0,%y1\"; | |
| 2412 case 2: | |
| 2413 return \"evstdd%X0 %1,%y0\"; | |
| 2414 default: | |
| 2415 gcc_unreachable (); | |
| 2416 } | |
| 2417 }" | |
| 2418 [(set_attr "type" "*,vecload,vecstore") | |
| 2419 (set_attr "length" "*,*,*")]) | |
| 2420 | |
| 2421 (define_insn "spe_truncdfsf2" | |
| 2422 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 2423 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
| 2424 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2425 "efscfd %0,%1") | |
| 2426 | |
| 2427 (define_insn "spe_absdf2" | |
| 2428 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2429 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
| 2430 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2431 "efdabs %0,%1") | |
| 2432 | |
| 2433 (define_insn "spe_nabsdf2" | |
| 2434 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2435 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))] | |
| 2436 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2437 "efdnabs %0,%1") | |
| 2438 | |
| 2439 (define_insn "spe_negdf2" | |
| 2440 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2441 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
| 2442 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2443 "efdneg %0,%1") | |
| 2444 | |
| 2445 (define_insn "spe_adddf3" | |
| 2446 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2447 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 2448 (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
| 2449 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2450 "efdadd %0,%1,%2") | |
| 2451 | |
| 2452 (define_insn "spe_subdf3" | |
| 2453 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2454 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 2455 (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
| 2456 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2457 "efdsub %0,%1,%2") | |
| 2458 | |
| 2459 (define_insn "spe_muldf3" | |
| 2460 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2461 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 2462 (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
| 2463 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2464 "efdmul %0,%1,%2") | |
| 2465 | |
| 2466 (define_insn "spe_divdf3" | |
| 2467 [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
| 2468 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 2469 (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
| 2470 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
| 2471 "efddiv %0,%1,%2") | |
| 2472 | |
| 2473 ;; Double-precision floating point instructions for IBM long double. | |
| 2474 | |
| 2475 (define_insn_and_split "spe_trunctfdf2_internal1" | |
| 2476 [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r") | |
| 2477 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))] | |
| 2478 "!TARGET_IEEEQUAD | |
| 2479 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2480 "@ | |
| 2481 # | |
| 2482 evor %0,%1,%1" | |
| 2483 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
| 2484 [(const_int 0)] | |
| 2485 { | |
| 2486 emit_note (NOTE_INSN_DELETED); | |
| 2487 DONE; | |
| 2488 }) | |
| 2489 | |
| 2490 (define_insn_and_split "spe_trunctfsf2" | |
| 2491 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
| 2492 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r"))) | |
| 2493 (clobber (match_scratch:DF 2 "=r"))] | |
| 2494 "!TARGET_IEEEQUAD | |
| 2495 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2496 "#" | |
| 2497 "&& reload_completed" | |
| 2498 [(set (match_dup 2) | |
| 2499 (float_truncate:DF (match_dup 1))) | |
| 2500 (set (match_dup 0) | |
| 2501 (float_truncate:SF (match_dup 2)))] | |
| 2502 "") | |
| 2503 | |
| 2504 (define_insn "spe_extenddftf2" | |
| 2505 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o") | |
| 2506 (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r"))) | |
| 2507 (clobber (match_scratch:DF 2 "=X,X,X,&r"))] | |
| 2508 "!TARGET_IEEEQUAD | |
| 2509 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2510 "@ | |
| 2511 evxor %L0,%L0,%L0 | |
| 2512 evor %0,%1,%1\;evxor %L0,%L0,%L0 | |
| 2513 evldd%X1 %0,%y1\;evxor %L0,%L0,%L0 | |
| 2514 evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0" | |
| 2515 [(set_attr "length" "4,8,8,12")]) | |
| 2516 | |
| 2517 (define_expand "spe_fix_trunctfsi2" | |
| 2518 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
| 2519 (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
| 2520 (clobber (match_dup 2)) | |
| 2521 (clobber (match_dup 3)) | |
| 2522 (clobber (match_dup 4))])] | |
| 2523 "!TARGET_IEEEQUAD | |
| 2524 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2525 { | |
| 2526 operands[2] = gen_reg_rtx (DFmode); | |
| 2527 operands[3] = gen_reg_rtx (SImode); | |
| 2528 operands[4] = gen_reg_rtx (SImode); | |
| 2529 }) | |
| 2530 | |
| 2531 ; Like fix_trunc_helper, add with rounding towards 0. | |
| 2532 (define_insn "spe_fix_trunctfsi2_internal" | |
| 2533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
| 2534 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r"))) | |
| 2535 (clobber (match_operand:DF 2 "gpc_reg_operand" "=r")) | |
| 2536 (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r")) | |
| 2537 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))] | |
| 2538 "!TARGET_IEEEQUAD | |
| 2539 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2540 "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2" | |
| 2541 [(set_attr "length" "24")]) | |
| 2542 | |
| 2543 (define_insn "spe_negtf2_internal" | |
| 2544 [(set (match_operand:TF 0 "gpc_reg_operand" "=r") | |
| 2545 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))] | |
| 2546 "!TARGET_IEEEQUAD | |
| 2547 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2548 "* | |
| 2549 { | |
| 2550 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
| 2551 return \"efdneg %L0,%L1\;efdneg %0,%1\"; | |
| 2552 else | |
| 2553 return \"efdneg %0,%1\;efdneg %L0,%L1\"; | |
| 2554 }" | |
| 2555 [(set_attr "length" "8")]) | |
| 2556 | |
| 2557 (define_expand "spe_abstf2_cmp" | |
| 2558 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
| 2559 (match_operand:TF 1 "gpc_reg_operand" "f")) | |
| 2560 (set (match_dup 3) (match_dup 5)) | |
| 2561 (set (match_dup 5) (abs:DF (match_dup 5))) | |
| 2562 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3) | |
| 2563 (match_dup 5))] CMPDFEQ_GPR)) | |
| 2564 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
| 2565 (label_ref (match_operand 2 "" "")) | |
| 2566 (pc))) | |
| 2567 (set (match_dup 6) (neg:DF (match_dup 6)))] | |
| 2568 "!TARGET_IEEEQUAD | |
| 2569 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2570 " | |
| 2571 { | |
| 2572 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
| 2573 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
| 2574 operands[3] = gen_reg_rtx (DFmode); | |
| 2575 operands[4] = gen_reg_rtx (CCFPmode); | |
| 2576 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
| 2577 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
| 2578 }") | |
| 2579 | |
| 2580 (define_expand "spe_abstf2_tst" | |
| 2581 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
| 2582 (match_operand:TF 1 "gpc_reg_operand" "f")) | |
| 2583 (set (match_dup 3) (match_dup 5)) | |
| 2584 (set (match_dup 5) (abs:DF (match_dup 5))) | |
| 2585 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3) | |
| 2586 (match_dup 5))] TSTDFEQ_GPR)) | |
| 2587 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
| 2588 (label_ref (match_operand 2 "" "")) | |
| 2589 (pc))) | |
| 2590 (set (match_dup 6) (neg:DF (match_dup 6)))] | |
| 2591 "!TARGET_IEEEQUAD | |
| 2592 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128" | |
| 2593 " | |
| 2594 { | |
| 2595 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
| 2596 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
| 2597 operands[3] = gen_reg_rtx (DFmode); | |
| 2598 operands[4] = gen_reg_rtx (CCFPmode); | |
| 2599 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
| 2600 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
| 2601 }") | |
| 2602 | |
| 2603 ;; Vector move instructions. | |
| 2604 | |
| 2605 (define_expand "movv2si" | |
| 2606 [(set (match_operand:V2SI 0 "nonimmediate_operand" "") | |
| 2607 (match_operand:V2SI 1 "any_operand" ""))] | |
| 2608 "TARGET_SPE" | |
| 2609 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") | |
| 2610 | |
| 2611 (define_insn "*movv2si_internal" | |
| 2612 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r") | |
| 2613 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))] | |
| 2614 "TARGET_SPE | |
| 2615 && (gpc_reg_operand (operands[0], V2SImode) | |
| 2616 || gpc_reg_operand (operands[1], V2SImode))" | |
| 2617 "* | |
| 2618 { | |
| 2619 switch (which_alternative) | |
| 2620 { | |
| 2621 case 0: return \"evstdd%X0 %1,%y0\"; | |
| 2622 case 1: return \"evldd%X1 %0,%y1\"; | |
| 2623 case 2: return \"evor %0,%1,%1\"; | |
| 2624 case 3: return output_vec_const_move (operands); | |
| 2625 default: gcc_unreachable (); | |
| 2626 } | |
| 2627 }" | |
| 2628 [(set_attr "type" "vecload,vecstore,*,*") | |
| 2629 (set_attr "length" "*,*,*,12")]) | |
| 2630 | |
| 2631 (define_split | |
| 2632 [(set (match_operand:V2SI 0 "register_operand" "") | |
| 2633 (match_operand:V2SI 1 "zero_constant" ""))] | |
| 2634 "TARGET_SPE && reload_completed" | |
| 2635 [(set (match_dup 0) | |
| 2636 (xor:V2SI (match_dup 0) (match_dup 0)))] | |
| 2637 "") | |
| 2638 | |
| 2639 (define_expand "movv1di" | |
| 2640 [(set (match_operand:V1DI 0 "nonimmediate_operand" "") | |
| 2641 (match_operand:V1DI 1 "any_operand" ""))] | |
| 2642 "TARGET_SPE" | |
| 2643 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") | |
| 2644 | |
| 2645 (define_insn "*movv1di_internal" | |
| 2646 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r") | |
| 2647 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))] | |
| 2648 "TARGET_SPE | |
| 2649 && (gpc_reg_operand (operands[0], V1DImode) | |
| 2650 || gpc_reg_operand (operands[1], V1DImode))" | |
| 2651 "@ | |
| 2652 evstdd%X0 %1,%y0 | |
| 2653 evldd%X1 %0,%y1 | |
| 2654 evor %0,%1,%1 | |
| 2655 evxor %0,%0,%0" | |
| 2656 [(set_attr "type" "vecload,vecstore,*,*") | |
| 2657 (set_attr "length" "*,*,*,*")]) | |
| 2658 | |
| 2659 (define_expand "movv4hi" | |
| 2660 [(set (match_operand:V4HI 0 "nonimmediate_operand" "") | |
| 2661 (match_operand:V4HI 1 "any_operand" ""))] | |
| 2662 "TARGET_SPE" | |
| 2663 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") | |
| 2664 | |
| 2665 (define_insn "*movv4hi_internal" | |
| 2666 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r") | |
| 2667 (match_operand:V4HI 1 "input_operand" "r,m,r,W"))] | |
| 2668 "TARGET_SPE | |
| 2669 && (gpc_reg_operand (operands[0], V4HImode) | |
| 2670 || gpc_reg_operand (operands[1], V4HImode))" | |
| 2671 "@ | |
| 2672 evstdd%X0 %1,%y0 | |
| 2673 evldd%X1 %0,%y1 | |
| 2674 evor %0,%1,%1 | |
| 2675 evxor %0,%0,%0" | |
| 2676 [(set_attr "type" "vecload")]) | |
| 2677 | |
| 2678 (define_expand "movv2sf" | |
| 2679 [(set (match_operand:V2SF 0 "nonimmediate_operand" "") | |
| 2680 (match_operand:V2SF 1 "any_operand" ""))] | |
| 2681 "TARGET_SPE || TARGET_PAIRED_FLOAT" | |
| 2682 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") | |
| 2683 | |
| 2684 (define_insn "*movv2sf_internal" | |
| 2685 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r") | |
| 2686 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))] | |
| 2687 "TARGET_SPE | |
| 2688 && (gpc_reg_operand (operands[0], V2SFmode) | |
| 2689 || gpc_reg_operand (operands[1], V2SFmode))" | |
| 2690 "@ | |
| 2691 evstdd%X0 %1,%y0 | |
| 2692 evldd%X1 %0,%y1 | |
| 2693 evor %0,%1,%1 | |
| 2694 evxor %0,%0,%0" | |
| 2695 [(set_attr "type" "vecload,vecstore,*,*") | |
| 2696 (set_attr "length" "*,*,*,*")]) | |
| 2697 | |
| 2698 ;; End of vector move instructions. | |
| 2699 | |
| 2700 (define_insn "spe_evmwhssfaa" | |
| 2701 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2702 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2703 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) | |
| 2704 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2705 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2706 "TARGET_SPE" | |
| 2707 "evmwhssfaa %0,%1,%2" | |
| 2708 [(set_attr "type" "veccomplex") | |
| 2709 (set_attr "length" "4")]) | |
| 2710 | |
| 2711 (define_insn "spe_evmwhssmaa" | |
| 2712 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2713 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2714 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) | |
| 2715 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2716 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2717 "TARGET_SPE" | |
| 2718 "evmwhssmaa %0,%1,%2" | |
| 2719 [(set_attr "type" "veccomplex") | |
| 2720 (set_attr "length" "4")]) | |
| 2721 | |
| 2722 (define_insn "spe_evmwhsmfaa" | |
| 2723 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2724 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2725 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) | |
| 2726 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2727 "TARGET_SPE" | |
| 2728 "evmwhsmfaa %0,%1,%2" | |
| 2729 [(set_attr "type" "veccomplex") | |
| 2730 (set_attr "length" "4")]) | |
| 2731 | |
| 2732 (define_insn "spe_evmwhsmiaa" | |
| 2733 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2734 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2735 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) | |
| 2736 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2737 "TARGET_SPE" | |
| 2738 "evmwhsmiaa %0,%1,%2" | |
| 2739 [(set_attr "type" "veccomplex") | |
| 2740 (set_attr "length" "4")]) | |
| 2741 | |
| 2742 (define_insn "spe_evmwhusiaa" | |
| 2743 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2744 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2745 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) | |
| 2746 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2747 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2748 "TARGET_SPE" | |
| 2749 "evmwhusiaa %0,%1,%2" | |
| 2750 [(set_attr "type" "veccomplex") | |
| 2751 (set_attr "length" "4")]) | |
| 2752 | |
| 2753 (define_insn "spe_evmwhumiaa" | |
| 2754 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2755 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2756 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) | |
| 2757 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2758 "TARGET_SPE" | |
| 2759 "evmwhumiaa %0,%1,%2" | |
| 2760 [(set_attr "type" "veccomplex") | |
| 2761 (set_attr "length" "4")]) | |
| 2762 | |
| 2763 (define_insn "spe_evmwhssfan" | |
| 2764 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2765 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2766 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) | |
| 2767 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2768 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2769 "TARGET_SPE" | |
| 2770 "evmwhssfan %0,%1,%2" | |
| 2771 [(set_attr "type" "veccomplex") | |
| 2772 (set_attr "length" "4")]) | |
| 2773 | |
| 2774 (define_insn "spe_evmwhssian" | |
| 2775 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2776 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2777 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) | |
| 2778 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2779 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2780 "TARGET_SPE" | |
| 2781 "evmwhssian %0,%1,%2" | |
| 2782 [(set_attr "type" "veccomplex") | |
| 2783 (set_attr "length" "4")]) | |
| 2784 | |
| 2785 (define_insn "spe_evmwhsmfan" | |
| 2786 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2787 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2788 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) | |
| 2789 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2790 "TARGET_SPE" | |
| 2791 "evmwhsmfan %0,%1,%2" | |
| 2792 [(set_attr "type" "veccomplex") | |
| 2793 (set_attr "length" "4")]) | |
| 2794 | |
| 2795 (define_insn "spe_evmwhsmian" | |
| 2796 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2797 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2798 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) | |
| 2799 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2800 "TARGET_SPE" | |
| 2801 "evmwhsmian %0,%1,%2" | |
| 2802 [(set_attr "type" "veccomplex") | |
| 2803 (set_attr "length" "4")]) | |
| 2804 | |
| 2805 (define_insn "spe_evmwhumian" | |
| 2806 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2807 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2808 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) | |
| 2809 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2810 "TARGET_SPE" | |
| 2811 "evmwhumian %0,%1,%2" | |
| 2812 [(set_attr "type" "veccomplex") | |
| 2813 (set_attr "length" "4")]) | |
| 2814 | |
| 2815 (define_insn "spe_evmwhgssfaa" | |
| 2816 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2817 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2818 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) | |
| 2819 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2820 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2821 "TARGET_SPE" | |
| 2822 "evmwhgssfaa %0,%1,%2" | |
| 2823 [(set_attr "type" "veccomplex") | |
| 2824 (set_attr "length" "4")]) | |
| 2825 | |
| 2826 (define_insn "spe_evmwhgsmfaa" | |
| 2827 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2828 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2829 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) | |
| 2830 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2831 "TARGET_SPE" | |
| 2832 "evmwhgsmfaa %0,%1,%2" | |
| 2833 [(set_attr "type" "veccomplex") | |
| 2834 (set_attr "length" "4")]) | |
| 2835 | |
| 2836 (define_insn "spe_evmwhgsmiaa" | |
| 2837 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2838 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2839 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) | |
| 2840 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2841 "TARGET_SPE" | |
| 2842 "evmwhgsmiaa %0,%1,%2" | |
| 2843 [(set_attr "type" "veccomplex") | |
| 2844 (set_attr "length" "4")]) | |
| 2845 | |
| 2846 (define_insn "spe_evmwhgumiaa" | |
| 2847 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2848 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2849 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) | |
| 2850 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2851 "TARGET_SPE" | |
| 2852 "evmwhgumiaa %0,%1,%2" | |
| 2853 [(set_attr "type" "veccomplex") | |
| 2854 (set_attr "length" "4")]) | |
| 2855 | |
| 2856 (define_insn "spe_evmwhgssfan" | |
| 2857 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2858 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2859 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) | |
| 2860 (clobber (reg:SI SPEFSCR_REGNO)) | |
| 2861 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2862 "TARGET_SPE" | |
| 2863 "evmwhgssfan %0,%1,%2" | |
| 2864 [(set_attr "type" "veccomplex") | |
| 2865 (set_attr "length" "4")]) | |
| 2866 | |
| 2867 (define_insn "spe_evmwhgsmfan" | |
| 2868 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2869 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2870 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) | |
| 2871 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2872 "TARGET_SPE" | |
| 2873 "evmwhgsmfan %0,%1,%2" | |
| 2874 [(set_attr "type" "veccomplex") | |
| 2875 (set_attr "length" "4")]) | |
| 2876 | |
| 2877 (define_insn "spe_evmwhgsmian" | |
| 2878 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2879 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2880 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) | |
| 2881 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2882 "TARGET_SPE" | |
| 2883 "evmwhgsmian %0,%1,%2" | |
| 2884 [(set_attr "type" "veccomplex") | |
| 2885 (set_attr "length" "4")]) | |
| 2886 | |
| 2887 (define_insn "spe_evmwhgumian" | |
| 2888 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
| 2889 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
| 2890 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) | |
| 2891 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] | |
| 2892 "TARGET_SPE" | |
| 2893 "evmwhgumian %0,%1,%2" | |
| 2894 [(set_attr "type" "veccomplex") | |
| 2895 (set_attr "length" "4")]) | |
| 2896 | |
| 2897 (define_insn "spe_mtspefscr" | |
| 2898 [(set (reg:SI SPEFSCR_REGNO) | |
| 2899 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2900 722))] | |
| 2901 "TARGET_SPE" | |
| 2902 "mtspefscr %0" | |
| 2903 [(set_attr "type" "vecsimple")]) | |
| 2904 | |
| 2905 (define_insn "spe_mfspefscr" | |
| 2906 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2907 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] | |
| 2908 "TARGET_SPE" | |
| 2909 "mfspefscr %0" | |
| 2910 [(set_attr "type" "vecsimple")]) | |
| 2911 | |
| 2912 ;; FP comparison stuff. | |
| 2913 | |
| 2914 ;; Flip the GT bit. | |
| 2915 (define_insn "e500_flip_gt_bit" | |
| 2916 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2917 (unspec:CCFP | |
| 2918 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))] | |
| 2919 "!TARGET_FPRS && TARGET_HARD_FLOAT" | |
| 2920 "* | |
| 2921 { | |
| 2922 return output_e500_flip_gt_bit (operands[0], operands[1]); | |
| 2923 }" | |
| 2924 [(set_attr "type" "cr_logical")]) | |
| 2925 | |
| 2926 ;; MPC8540 single-precision FP instructions on GPRs. | |
| 2927 ;; We have 2 variants for each. One for IEEE compliant math and one | |
| 2928 ;; for non IEEE compliant math. | |
| 2929 | |
| 2930 (define_insn "cmpsfeq_gpr" | |
| 2931 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2932 (unspec:CCFP | |
| 2933 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2934 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2935 1000))] | |
| 2936 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2937 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 2938 "efscmpeq %0,%1,%2" | |
| 2939 [(set_attr "type" "veccmp")]) | |
| 2940 | |
| 2941 (define_insn "tstsfeq_gpr" | |
| 2942 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2943 (unspec:CCFP | |
| 2944 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2945 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2946 1001))] | |
| 2947 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2948 && flag_finite_math_only && !flag_trapping_math" | |
| 2949 "efststeq %0,%1,%2" | |
| 2950 [(set_attr "type" "veccmpsimple")]) | |
| 2951 | |
| 2952 (define_insn "cmpsfgt_gpr" | |
| 2953 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2954 (unspec:CCFP | |
| 2955 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2956 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2957 1002))] | |
| 2958 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2959 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 2960 "efscmpgt %0,%1,%2" | |
| 2961 [(set_attr "type" "veccmp")]) | |
| 2962 | |
| 2963 (define_insn "tstsfgt_gpr" | |
| 2964 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2965 (unspec:CCFP | |
| 2966 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2967 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2968 1003))] | |
| 2969 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2970 && flag_finite_math_only && !flag_trapping_math" | |
| 2971 "efststgt %0,%1,%2" | |
| 2972 [(set_attr "type" "veccmpsimple")]) | |
| 2973 | |
| 2974 (define_insn "cmpsflt_gpr" | |
| 2975 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2976 (unspec:CCFP | |
| 2977 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2978 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2979 1004))] | |
| 2980 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2981 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 2982 "efscmplt %0,%1,%2" | |
| 2983 [(set_attr "type" "veccmp")]) | |
| 2984 | |
| 2985 (define_insn "tstsflt_gpr" | |
| 2986 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 2987 (unspec:CCFP | |
| 2988 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
| 2989 (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
| 2990 1005))] | |
| 2991 "TARGET_HARD_FLOAT && !TARGET_FPRS | |
| 2992 && flag_finite_math_only && !flag_trapping_math" | |
| 2993 "efststlt %0,%1,%2" | |
| 2994 [(set_attr "type" "veccmpsimple")]) | |
| 2995 | |
| 2996 ;; Same thing, but for double-precision. | |
| 2997 | |
| 2998 (define_insn "cmpdfeq_gpr" | |
| 2999 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3000 (unspec:CCFP | |
| 3001 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3002 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3003 CMPDFEQ_GPR))] | |
| 3004 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3005 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3006 "efdcmpeq %0,%1,%2" | |
| 3007 [(set_attr "type" "veccmp")]) | |
| 3008 | |
| 3009 (define_insn "tstdfeq_gpr" | |
| 3010 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3011 (unspec:CCFP | |
| 3012 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3013 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3014 TSTDFEQ_GPR))] | |
| 3015 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3016 && flag_finite_math_only && !flag_trapping_math" | |
| 3017 "efdtsteq %0,%1,%2" | |
| 3018 [(set_attr "type" "veccmpsimple")]) | |
| 3019 | |
| 3020 (define_insn "cmpdfgt_gpr" | |
| 3021 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3022 (unspec:CCFP | |
| 3023 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3024 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3025 CMPDFGT_GPR))] | |
| 3026 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3027 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3028 "efdcmpgt %0,%1,%2" | |
| 3029 [(set_attr "type" "veccmp")]) | |
| 3030 | |
| 3031 (define_insn "tstdfgt_gpr" | |
| 3032 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3033 (unspec:CCFP | |
| 3034 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3035 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3036 TSTDFGT_GPR))] | |
| 3037 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3038 && flag_finite_math_only && !flag_trapping_math" | |
| 3039 "efdtstgt %0,%1,%2" | |
| 3040 [(set_attr "type" "veccmpsimple")]) | |
| 3041 | |
| 3042 (define_insn "cmpdflt_gpr" | |
| 3043 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3044 (unspec:CCFP | |
| 3045 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3046 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3047 CMPDFLT_GPR))] | |
| 3048 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3049 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3050 "efdcmplt %0,%1,%2" | |
| 3051 [(set_attr "type" "veccmp")]) | |
| 3052 | |
| 3053 (define_insn "tstdflt_gpr" | |
| 3054 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3055 (unspec:CCFP | |
| 3056 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
| 3057 (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
| 3058 TSTDFLT_GPR))] | |
| 3059 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
| 3060 && flag_finite_math_only && !flag_trapping_math" | |
| 3061 "efdtstlt %0,%1,%2" | |
| 3062 [(set_attr "type" "veccmpsimple")]) | |
| 3063 | |
| 3064 ;; Same thing, but for IBM long double. | |
| 3065 | |
| 3066 (define_insn "cmptfeq_gpr" | |
| 3067 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3068 (unspec:CCFP | |
| 3069 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3070 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3071 CMPTFEQ_GPR))] | |
| 3072 "!TARGET_IEEEQUAD | |
| 3073 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3074 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3075 "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2" | |
| 3076 [(set_attr "type" "veccmp") | |
| 3077 (set_attr "length" "12")]) | |
| 3078 | |
| 3079 (define_insn "tsttfeq_gpr" | |
| 3080 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3081 (unspec:CCFP | |
| 3082 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3083 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3084 TSTTFEQ_GPR))] | |
| 3085 "!TARGET_IEEEQUAD | |
| 3086 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3087 && flag_finite_math_only && !flag_trapping_math" | |
| 3088 "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2" | |
| 3089 [(set_attr "type" "veccmpsimple") | |
| 3090 (set_attr "length" "12")]) | |
| 3091 | |
| 3092 (define_insn "cmptfgt_gpr" | |
| 3093 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3094 (unspec:CCFP | |
| 3095 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3096 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3097 CMPTFGT_GPR))] | |
| 3098 "!TARGET_IEEEQUAD | |
| 3099 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3100 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3101 "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2" | |
| 3102 [(set_attr "type" "veccmp") | |
| 3103 (set_attr "length" "20")]) | |
| 3104 | |
| 3105 (define_insn "tsttfgt_gpr" | |
| 3106 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3107 (unspec:CCFP | |
| 3108 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3109 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3110 TSTTFGT_GPR))] | |
| 3111 "!TARGET_IEEEQUAD | |
| 3112 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3113 && flag_finite_math_only && !flag_trapping_math" | |
| 3114 "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2" | |
| 3115 [(set_attr "type" "veccmpsimple") | |
| 3116 (set_attr "length" "20")]) | |
| 3117 | |
| 3118 (define_insn "cmptflt_gpr" | |
| 3119 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3120 (unspec:CCFP | |
| 3121 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3122 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3123 CMPTFLT_GPR))] | |
| 3124 "!TARGET_IEEEQUAD | |
| 3125 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3126 && !(flag_finite_math_only && !flag_trapping_math)" | |
| 3127 "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2" | |
| 3128 [(set_attr "type" "veccmp") | |
| 3129 (set_attr "length" "20")]) | |
| 3130 | |
| 3131 (define_insn "tsttflt_gpr" | |
| 3132 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3133 (unspec:CCFP | |
| 3134 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r") | |
| 3135 (match_operand:TF 2 "gpc_reg_operand" "r"))] | |
| 3136 TSTTFLT_GPR))] | |
| 3137 "!TARGET_IEEEQUAD | |
| 3138 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128 | |
| 3139 && flag_finite_math_only && !flag_trapping_math" | |
| 3140 "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2" | |
| 3141 [(set_attr "type" "veccmpsimple") | |
| 3142 (set_attr "length" "20")]) | |
| 3143 | |
| 3144 ;; Like cceq_ior_compare, but compare the GT bits. | |
| 3145 (define_insn "e500_cr_ior_compare" | |
| 3146 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
| 3147 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y") | |
| 3148 (match_operand 2 "cc_reg_operand" "y")] | |
| 3149 E500_CR_IOR_COMPARE))] | |
| 3150 "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
| 3151 "cror 4*%0+gt,4*%1+gt,4*%2+gt" | |
| 3152 [(set_attr "type" "cr_logical")]) | |
| 3153 | |
| 3154 ;; Out-of-line prologues and epilogues. | |
| 3155 (define_insn "*save_gpregs_spe" | |
| 3156 [(match_parallel 0 "any_parallel_operand" | |
| 3157 [(clobber (reg:P 65)) | |
| 3158 (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3159 (use (reg:P 11)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3160 (set (match_operand:V2SI 2 "memory_operand" "=m") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3161 (match_operand:V2SI 3 "gpc_reg_operand" "r"))])] |
| 0 | 3162 "TARGET_SPE_ABI" |
| 3163 "bl %z1" | |
| 3164 [(set_attr "type" "branch") | |
| 3165 (set_attr "length" "4")]) | |
| 3166 | |
| 3167 (define_insn "*restore_gpregs_spe" | |
| 3168 [(match_parallel 0 "any_parallel_operand" | |
| 3169 [(clobber (reg:P 65)) | |
| 3170 (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3171 (use (reg:P 11)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3172 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3173 (match_operand:V2SI 3 "memory_operand" "m"))])] |
| 0 | 3174 "TARGET_SPE_ABI" |
| 3175 "bl %z1" | |
| 3176 [(set_attr "type" "branch") | |
| 3177 (set_attr "length" "4")]) | |
| 3178 | |
| 3179 (define_insn "*return_and_restore_gpregs_spe" | |
| 3180 [(match_parallel 0 "any_parallel_operand" | |
| 3181 [(return) | |
| 3182 (clobber (reg:P 65)) | |
| 3183 (use (match_operand:P 1 "symbol_ref_operand" "s")) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3184 (use (reg:P 11)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3185 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
3186 (match_operand:V2SI 3 "memory_operand" "m"))])] |
| 0 | 3187 "TARGET_SPE_ABI" |
| 3188 "b %z1" | |
| 3189 [(set_attr "type" "branch") | |
| 3190 (set_attr "length" "4")]) |